JPS6142299B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly, to an improvement in a configuration for recording failure information of an information processing apparatus.

Generally, in an information processing device, changes in internal signals at predetermined time intervals are recorded in a memory element, and when an abnormal phenomenon such as a failure occurs, writing to this memory element is stopped and the contents of the memory element are saved. It is equipped with a so-called stage tracer that outputs information for tracing the cause up to the occurrence of a failure. Usually, this stage tracer is realized with a signal to be measured of several tens to hundreds of words, and one word is approximately 100 bits.

On the other hand, LSI technology has made remarkable progress in recent years, and _one LSI can now accommodate from several hundred gates to tens of thousands of gates. However, in the conventional technology, the signal under test to the stage tracer is connected to a fixed internal signal of the information processing device, so in order to convert the many signals in the ISI into the signal under test, the internal signal must be connected to the LSI output pin. The problem was that it had to be output, which caused a pin-neck in LSI implementation and was difficult.
Furthermore, it is difficult to obtain fault information that satisfies all faults, and increasing the number of signals to be measured has the problem of increasing manufacturing costs. Furthermore, even if there is a case where you want to check the operating status of an internal register that is not output to a pin inside the LSI, conventional technology uses external means such as the register under test of a tracer or a synchroscope to check the registers before and after that register. There was no other way than to infer the operating state from the registers that could be observed.

It is an object of the present invention to provide a system that allows the contents of registers and latches at arbitrary locations in an information processing device to be changed to multiple words and stage tracers without changing the connection of the stage tracer's avoidance measurement signal from the conventional device-fixed signal using a jumper wire or the like. It is an object of the present invention to provide an information processing device that is improved so that the measured signal can be written.

Therefore, in the present invention, registers and latches in an information processing device are divided into a plurality of blocks (one block is a unit of _one VLSI, a unit of several packages, or a unit of a device). A scan address register is provided in each unit, and the address of the corresponding bit of the register and latch to which the address is assigned in the block is set in advance in the scan address register, and the information processing device During operation, the contents of the corresponding one bit are always scanned out and read onto the output bus. By connecting the output bus signal read from each block to the stage tracer's written signal under test in this way, a common scanout bus can be used without connecting a fixed signal line from the information processing device to the stage tracer. Using this, it becomes possible to record the contents of one bit of any register in the stage tracer for each block.

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 shows a block diagram of the entire information processing according to the present invention. FIG. 1 shows a group of registers and latches constituting an information processing device: block (A) 1, block (B) 2, block (C) 3, and block (D) 4.
In this example, the readout lines 5a, 5b, 5c, and 5d from each block are connected to the input of the stage tracer 6. Writing and reading control of the storage element 7 of the stage tracer 6 is performed by a control circuit 8. On the other hand, a readout line 9 from this stage tracer 6 is connected to a hard copy control circuit 10 and further connected to a hard copy device 12 through an interface line 11. FIG. 2 shows the detailed configuration of one block among the plurality of blocks shown in FIG. 1.

Now, an information processing device has registers within the processing device,
It has a function to start and read the latch status from a microprogram, console panel, or external device. Hereinafter, this will be referred to as a scan control section. Using the scan control section of this processing device, the scan address line 16 is set in advance to each scan address register 13 in blocks 1 to 4 by activation from a microprogram, console panel, or external device. A flip-flop (FF) 2 in the processing device to be stored in the storage element 7 of the stage tracer 6 through
Set the scan address of 4. During the operation of the processing device, the output line 14 of the scan address register 13 is selected by the scan address selector 15 and transferred to the scan address bus 17, and becomes an input to the decoder 18. The output lines of the decoder 18 correspond to each FF in the register or latch group 20 that stores information processed by the combinational circuit 19 and are specified by the scan address bus 17.
Used to select FF information. Note that when the scan control section of the information processing device performs the original diagnostic operation, the scan address line 16 connected to this scan control section is connected to the scan address select 1.
The scan addresses selected by 5 and specified by the scan control unit are sequentially transferred to the scan address bus 1.
I will be riding 7.

An AND gate 22 takes the logical product condition of the output of the decoder 18 and the output of the FF 24, and the information of the FF 24 is read out to the output line 23 of the AND gate 22. This read content is output to the outside through the OR gate 25 and the read line 5a. This information becomes the input to the stage tracer 6 in FIG. The control circuit 8 controls the writing of the stage tracer 6, and normally has the function of storing input information at the timing of the processing device and stopping storage when a failure occurs. When a failure occurs, the cause of the failure is investigated by analyzing the information from the stage tracer 6. The control circuit 1 outputs the information of the stage tracer 6 to an external device (hard copy device 12 in this embodiment).
It is 0. This control circuit 10 operates when a machine check occurs or upon instructions from an external device.
The memory element 7 of the stage tracer 6 is connected to the hardcopy unit 12 through an interface line 11.
Outputs the information.

Since the configuration is as described above, according to the present invention, the signal of any register can be obtained by the stage tracer while the processing device is operating by simply changing the contents of the scan address register in each divided block. It becomes possible to obtain the status of internal registers and latches that are not exposed to LSI pins or package pins via a stage tracer.
Furthermore, by combining the signal under measurement of the stage tracer with information such as important registers fixed to the information processing device and the data obtained by the present invention, it becomes possible to obtain effective data without increasing the number of signals under measurement. .

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a detailed configuration diagram of one block among a plurality of blocks in FIG. 1. DESCRIPTION OF SYMBOLS 1-4... Division block, 6... Stage tracer, 7... Storage element, 8... Control circuit, 10... Hard copy control circuit, 12... Hard copy device, 13
...Scan address register, 15...Scan address selector, 18...Decoder, 19...Combination circuit, 20...Register or latch group, 22...
AND gate, 25...OR gate.

Claims (1)

[Claims] 1. In an information processing device that is equipped with a function (hereinafter referred to as a scan control section) for reading out the status of registers, latches, etc. in the processing device by starting it from a microprogram, console panel, or external device, Divide the registers and latches into multiple blocks, and for each block select a scan address register for specifying the registers and latches in the block, and select the register and latch specified by the scan address register. and a means for reading out the contents is provided, and an address is set in advance in the scan address register in each block using the scan control section, and during operation of the processing device, the address is set in advance from each block to the scan address register. An information processing apparatus characterized in that the contents of the same designated register or latch are continuously read out and stored in a storage means.