JPS6236269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for collecting error information in a log memory for recording errors during testing of storage devices used in computers, etc., and in particular, a method for collecting error information in a log memory that records errors during testing of storage devices used in computers, etc. Concerning the method of recording to memory.

Conventionally, in a memory test, a method has been adopted in which all memory errors are recorded in a log memory without distinguishing the contents of the error.
However, with the recent increase in the density of semiconductor memory devices, the frequency of soft errors caused by external factors cannot be ignored, and the error details of both newly generated soft errors and conventional hard errors are recorded. In the conventional error logging method, a problem arises in that a memory test cannot be performed correctly due to insufficient log memory.

Here, soft errors are caused by external factors.
The stored contents are inverted and can be restored to normal by rewriting the correct information, and error addresses tend to be random and discontinuous. A hard error becomes a fixed error for some reason, and even if correct information is rewritten once again, the normal state cannot be restored, and the error addresses are often continuous.

The purpose of the present invention is to perform memory testing in a memory test.
Efficient use of log memory by arbitrarily selecting error contents and recording them in log memory without the log memory for recording errors being occupied by soft or hard error contents. It provides a method.

According to the present invention, when write data is written to the memory under test, read data is obtained again by reading it, and a mismatch occurs when the read data and write data are compared, the results of this all-bit comparison and means for sequentially storing error contents consisting of memory addresses and comparing the previous error contents with the current error contents to determine the error mode; and selecting the error mode determined by the above means. This provides an error information collection system that includes means for arbitrarily selecting and recording error details in a log memory in response to a selection signal.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Connected to the memory under test 1 are a tester 2 for testing it, a log memory 3 for recording memory errors, and an error determination circuit 4 for determining error contents. The memory under test 1, the tester 2, and the error determination circuit 4 are connected by a signal line l1 for transmitting memory address signals, read and write data, and control signals. The error determination circuit 4 receives the signal line l1, further determines the contents of the memory error, sends the error contents to be recorded in the log memory 3 through the signal line l2, and sends the error determination signal to the signal line l2. ′ is sent. The log memory 3 selectively records the error contents sent from the error determination circuit 4 according to the error mode selection signal l3 sent from the tester 2.

In addition, the log memory 3 reads the error contents according to the read instruction sent from the tester 2, and outputs the error contents to the signal line l.
4 to the tester 2. Here tester 2
sequentially provides test data and addresses to the memory under test 1, and sends test data (write/write) to be read out in advance to the error judgment circuit 4.
data) and memory read results.
In addition to sending the data, it also sends an error mode selection signal to the log memory 3 for selectively recording the error contents sent out by the error determination circuit 4.

FIGS. 2 and 3 are circuit and flow diagrams showing one embodiment of the present invention. The same parts as in FIG. 1 are given the same reference numerals.

In this example, the number of bits to be tested in the memory under test 1 is m bits, and the memory address is n bits. In the figure, the logic of the reset signal IRS of tester 2 is changed from “1” to “0”.
→ When it changes to "1", the outputs Q of flip-flops (hereinafter abbreviated as FF) 20, 21 to 27 become logic "0". Memory with memory under test 1
Each bit T ₁ to _{T n} of write data T is written to the address indicated by address A ₁ to A _o , and each bit M ₁ to M _n of read data M is obtained by reading it again. , these are connected to the EOR (exclusive OR) gate 10 of the error judgment circuit 4,
In step 11, compare each bit correspondingly, and if there is a mismatch between write data T and read data (T≠M),
The outputs of EOR gates 10 and 11 become logic "1" and therefore the output of m-bit OR gate 12 becomes logic "1". This discrepancy signal thus indicates that an error has been detected in the test results. This mismatch signal is passed through AND gate 13 to FF2 by error set signal ERT sent from tester 2.
The results of comparing all bits of write data T and read data M and the memory address where the error occurred are sent to FFs 20, 21 to 27 as error contents.
4, 26. Further, the clock signal at this time shifts the old storage contents of each FF 20, 22, 24, 26 to FF 21, 23, 25, 27. And EOR gate 14, 15, 16, 1
7 has FF20, 22, 24, 26 and FF21, 2
3, 25, and 27 respectively, and if any of the m bits of test data do not match, OR
The output of the gate 18 becomes logic "1" and it is determined that the previous comparison result and the current comparison result are not the same.

Next, when the second error occurs, the contents of the first error are shifted to FF21, 23, 25, and 27, and the contents of the second error are shifted to FF20, 2.
2, 24, and 26. So EOR again
Comparing gates 14, 15, 16, and 17, for example, if the same bit out of m bits of the test data is in error in the previous and current tests, the memory
When comparing n bits of addresses, if it is determined that the previous and current addresses are not the same address, OR
The gate 18 output becomes logic "0" and the OR gate 19 output becomes logic "1". That is, this indicates that the previous comparison result and the current comparison result are the same, and that the previous error address and the current error address are not the same.

To summarize, the signals A and B output from the OR gates 18 and 19 indicate the error mode as the error determination result of the memory under test 1. That is, the signal A indicates whether the previous error result and the current error result are the same or not regarding the test result of m bits of test data, and the signal B indicates the memory indicating the previous error. Memory indicating address and current error. This is an error determination signal indicating whether the addresses are the same or not.

The error mode selection signal l3 sent from the tester to the log memory control unit 6 consists of independently selectable signals S ₁ , S ₂ , S ₃ , and S ₄ , and includes the above-mentioned error judgment signals A and B. 4 made by the combination of
Select the error mode accordingly.

The log memory control unit 6 decodes the signals A and B and transmits a write control signal to the log memory array 5 through the signal line l5 when the mode matches the error mode selection signal l3.
The error contents sent through 2 are recorded in the log memory array 5.

To read the contents of the log memory array 5, send a read signal LRS from the tester 2 to the log memory controller 6.
to read the recorded contents. Although not shown, the log memory array 5 includes an address decoder and the memory control unit 6 includes an address counter, which increments in response to a read or write control signal and instructs the log address. At the same time, it is initialized by a reset signal IRS.

FIG. 3 briefly shows the operational flow of error determination.

First, test data is written from the tester 2 to the memory under test 1, and then the data is read out. The error determination circuit 4 compares the write data and the read data to determine whether or not there is an error, and if it is an error (T≠M), the error details are stored. The error determination circuit 4 compares the currently stored error content with the previously stored error content to determine the error mode.

This determined error mode is compared with the error mode selection signal, and if a match is found, the content of the currently detected error is written into the log memory 3. Here, if the collation result does not match or the test result is not an error (W=M), the test cycle is ended without writing to the log memory 3.

As is clear from the above embodiments, according to the present invention, when recording memory errors in the log memory during a memory test, the memory errors can be selected and recorded using the selection signal.
A method is provided in which memory is used efficiently without being exclusively occupied by soft or hard errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIGS. 2 and 3 are a circuit diagram and a flow diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory under test, 2...Test device, 3...Log memory, 4...Error determination circuit, 5...Log memory array, 6...Log memory control unit, 10, 11, 1
4-17...EOR gate, 12,18,19...OR
Gate, 13...AND gate, 20, 21-27
...Flip-flop, _T1 to _Tn ...Write data bit, _M1 to _Mn ...Read data bit, _A1
~A _n ...Memory address bit.

Claims (1)

[Claims] 1. Writing write data to the memory under test,
If read data is obtained by reading again and a mismatch occurs when the read data and write data are compared, the error contents consisting of all bit comparison results and the memory address are sequentially stored and the previous error contents are stored. Compare the current error contents with the following A and B2 conditions Condition A: The comparison result of all the bits that caused an error last time is the same as the current error or is not the same. Condition B: a means for determining which of four error modes is selected by combining whether the memory address at the time of the previous error and the memory address at the time of the current error are the same or not; An error information collection system comprising: a selection signal for selecting an error mode; and means for recording error details in a log memory when the determination results match.