JPH0326480B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory testing device.

A conventional device of this type is shown in FIG.

In the figure, 1 and 2 are X and Y address selectors, respectively, and 3 is a fail memory, which stores failure occurrence information in a portion corresponding to a failure occurrence address. 4 is a data generator that generates write data and comparison data during reading; 5 is a multi-address controller; 6 is pin electronics containing drivers and comparators; 7 is a semiconductor memory under test; It has a plurality of bit memory elements arranged in a matrix.

Next, the operation will be explained.

The test execution address for testing the semiconductor memory under test 7 is the X, Y address selector 1, 2.
The address information is transmitted to the fail memory 3 and pin electronics 6. If the semiconductor memory under test 7 is an address multiplex element, the multi-address control 5
Therefore, X and Y address information are carried on the same signal line, but if the semiconductor memory under test 7 is a device that is not an address multiplex device, the information is transmitted to the pin electronics 6 independently for X and Y. Write data and comparison data at the time of reading are generated by the data generator 4 and sent to the semiconductor memory under test 7.
The write data is once written into the memory element at the determined address, and the pin electronics 6 compares the read data with the comparison data to determine whether or not the memory element is defective. If there is a defect, its address information is stored in the fail memory 3. This is repeated for all bits of memory elements.

At the end of the test, the address information of the defective bits is stored in the fail memory 3, so it is possible to read the contents of the fail memory 3 and recognize the address and number of defective bits present in each row and each column.

Conventional memory test equipment is configured as described above, so if you want to recognize the number of defective bits in each row and each column after the test, if the semiconductor memory
In the case of bits, the fail memory 3 must be accessed at least 2N times, which has the drawback of requiring a lot of time to recognize the number of defective bits in each row and each column.

The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional device, and an object of the present invention is to provide a semiconductor memory testing device equipped with a device for independently storing the number of defective bits in each row and each column.

An embodiment of the present invention will be described below.
In FIG. 2, 8 is provided independently in rows and columns, and each row,
A defective bit number memory circuit stores the number of defective bits for each column, and 8 is an arithmetic unit that increments the contents by one.

Since the semiconductor memory under test 7 is tested in the same manner as shown in FIG. 1 above,
The explanation thereof will be omitted, and the operation of the defective bit number storage circuit 8 will be mainly described.

The number of defective bits storage circuit 8 is composed of a high-speed memory, and according to the test address, the number of defective bits for each row or column containing the test address is always outputted, the output data is incremented by 1 by the arithmetic unit 9, and this is used as the input data. It is becoming. When a defect occurs, an error signal becomes a write signal to the defective bit storage circuit 8, and each time a defect occurs, the number of defective bits stored in the row and column corresponding to the address where the defect occurs is incremented by one. If no defects occur, the previous number of defective bits is retained.

In the case of this invention, if the memory element of the semiconductor memory under test 7 has N bits, the address of the defective bit in each row and column can be determined by accessing the defective bit number storage circuit 8 2√ times in total for rows and columns. and can recognize numbers. This means that when N=10 ⁶ (megabit memory), the access time can be reduced to 1/1000 of that of the conventional device.

Although the +1 arithmetic unit 9 is used in the above embodiment, the same effect can be obtained even if it is configured with a counter.

As described above, according to the present invention, since the number of defective bits in each row and each column is independently stored during the execution of a functional test, the time required to recognize the number of defective bits in each row and each column after the test is completed is greatly reduced. can do.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a conventional semiconductor memory testing device, and FIG. 2 is a configuration diagram showing a semiconductor memory testing device according to an embodiment of the present invention. 1... Mail address selector, 2... Y address selector, 3... Fail memory, 4... Data generator, 5... Multi address control, 6... Pin electronics, 7... Semiconductor memory, 8... Defective bit Number memory circuit, 9...+
1 arithmetic unit. Note that in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] 1. A semiconductor memory under test having multiple bit memory elements arranged in X rows and Y columns, an X address selector that determines the X address of the memory element, a Y address selector that determines the Y address of the memory element, and the memory a data generator that generates test data for testing the device;
a detection means for sequentially testing the memory element at a predetermined address determined by each of the address selectors for each address based on the test data and detecting a defective bit; A semiconductor memory testing device comprising storage means for independently counting and storing the number of rows and columns.