JPS585681A - Testing device for semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a time required for recognizing the number of inferior bits after completion of a test, by providing inferior bit number memorizing units separately for each line and column. CONSTITUTION:The number of inferior bits in every line or column is added by +1 according to test addresses by operators 9 and stored in an X inferior bit memory 8 or a Y inferior bit memory 8. Accordingly, the number of inferior bits is recognized only by accessing the memories 8, 8 in (1/2)XN<1/2> times, without accessing a fail memory 3 storing the addresses of the inferior bits after completion of a test in the same number of times with the bit number N of a memory 7, and thus a time required for recognition of the number of inferior bits is sharply shortened in comparison with the case when no inferior bit memory is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory testing device.

Conventionally, there was a device of this type as shown in Figure O1.

In the figure, fi+ +21 is an X and Y address selector, and a 1:II fail memory, which stores failure occurrence information in a portion corresponding to a failure occurrence address.

141 is a data generator that generates data to be read and comparison data when reading, (5) is a multi-address controller, (6) is a pin electronics containing a dryer/( and a humperator), (71 is a semiconductor memory under test, It has multiple bit memory elements arranged in a matrix of X rows and Y columns.

Next, the operation will be explained.

The test execution address for testing the semiconductor memo under test (January 7) is determined by the X and Y address selectors, and the address information is stored in the fail memory (31, 31,
It is transmitted to the pin electronics (8). Address multiplex elements transmit X and Y address information to the same signal J+ line by the multi-address control (5), but elements that are not address multiplex transmit that information independently to the pin electronics (6). Conveyed. Write data and comparison data during reading are generated by the data generator (
4), the self-write data is once written to the memory element at the determined address of the semiconductor memory under test (7), and the subsequently output data and the comparison data are compared at pin electronics f6. By doing so, it is determined whether or not the memory element is defective. If there is a defect,
The address information is stored in the fail memo (January 3). This is repeated for all bits of memory elements.

At the end of Tetos, the address information of the defective bits is stored and viewed in the fail memory (3), so read the contents of the fail memory (3) and recognize the address and number of defective bits existing in each row and column. can do.

Conventional memory test equipment is configured as described above, so if you want to recognize the number of defective bits in each row and each column after the test, if the semiconductor memory is N bits, it must be tested at least N times.
The fail memory (31) has to be accessed, and there is a drawback that it takes a lot of time to recognize the number of defective bits in each row and each column.

The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional device, and an object of the present invention is to provide a semiconductor memory testing device equipped with a device for independently storing the number of defective bits in each row and each column.

An embodiment of the present invention will be described below.

In Figure 8 (81 is provided independently in 9 rows and 9 columns for each row).

This is a defective bit number storage circuit that stores the number of defective bits for each column, and is an arithmetic unit that increments the contents of (91 decimals) by 1.

The defective bit number storage circuit (8) is composed of high-speed memory,
Depending on the test address, the number of defective bits for each row or column containing the test address is always output 1,
1 increments the output data by 1, which is connected to the input data. When a defect occurs, the error signal becomes a write signal to the defective bit storage circuit (81), and each time a defect occurs, the defective pit bit storage value 73 of the row and column corresponding to the address where the defect occurs is incremented by +1.If no defect occurs holds the previous number of defective bits.

In the case of this invention, if the memory element of the semiconductor memo under test (January 7) has N bits, each η
, the address and number of defective bits in each column can be recognized. This is for N-101 megabit memory).
This means that the access time can be shortened compared to the conventional device 11500.

In the above embodiment, the +1 arithmetic unit (9) is used, but the same effect can be obtained even if it is configured with a kakuunter.

As described above, according to this structure, the number of defective bits is stored independently in each row and column during the mock test, so the time required to recognize the number of defective bits after the test is completed can be greatly reduced. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional semiconductor memory testing device, and FIG. 8 is a block diagram showing a semiconductor memory testing device according to the present invention. Il+ --- Mail address selector, +21 --- Y
Address selector, +31---7 Air memory, +4
1--data generator, (5)-m-multi-address control, r6+--pin electronics, +71--1 semiconductor memory, +81--1 defective bit number memory circuit, +91--+1 arithmetic unit. Note that in the figures, the same reference numerals indicate the same parts. Agent Shin Kuzuno - Figure 1, 2nd arc

Claims (1)

[Claims] A semiconductor memory under test having a plurality of bits of memory elements arranged in X rows and Y columns, a mead address selector that determines a mere F address of the memory element, a Y address selector that determines the Y address of the memory element, and the memory A data generator that generates test data for testing the device; a detection device that sequentially tests the memory device at a predetermined address determined by each of the address selectors for each address based on the test data to detect defective bits; A semiconductor memory testing device comprising a storage means for independently counting and storing the number of detected defective bits for each row and each column each time the means detects a defective bit.