JPH05342113A - Fault detecting method for ram for built in system - Google Patents

Abstract

PURPOSE:To shorten the test time by checking the write or the read-out of one test pattern in one cycle time by using (n+1) test patterns when the number of bits of one word is 2<n>. CONSTITUTION:In the beginning, data (a) are written in all addresses in advance (step S1), and subsequently, A='0'-th address is set (step S2), the data (a) are read out in one cycle time ad checked, and also, after (a) are read out, data (b) are written in one cycle time (step S3). Whether A=Nth address or not is checked (step S4), and when it is negative, (A=A+1) is set (step S5), and the step S3 is repeated. When A=Nth in the step S4, it is migrated to a step S6, and the read-out of the data (b) and the write of data (c) are executed (step S6). The operation of the step S6 is executed successively extending from A=N address to A='0'-th address. In such a manner to the memory cell of a one-word portion of A-th address, the write or the read-out of the data (a)-(e) is executed in one cycle time by one data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an embedded system; a system in which a computer system is incorporated and used as part of a system for controlling various devices and equipment and collecting data. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a read / write memory (RAM) used at any time, and particularly to shortening a test time.

[0002]

RAM used in embedded systems
Marching Test (Marching Tes
t) is well known, so
I will explain. First, all RAM addresses (0 to N)
0 is written in the file (step S₁). Then add
Address A = 0 (Step S₂), A = 0
Written in one of the S-bit cells that make up one word
Data 0 is read, and 0 is read
Check whether or not, and read 1 and then 1
Write. This 0 read, 1 write operation is S bit
For each cell (step S₃). Next, A
= Check if it is N address (step S_Four), No
For example, A = A + 1 (step S_Five), Step S₃
Repeat the operation of. Step S_FourAt A = N
If there is, write to one of the cells for 1 word at address A = N
Read the rare data 1 and surely read 1
Check whether or not it has been read, and after reading 1
Write data 0. This 1 read, 0 write operation
Are sequentially performed for S-bit cells forming one word
(Step S₆). Next, check if A = 0.
(Step S₇), If not, set A = A-1 (step
Up S₈), Step S₆Repeat the operation of. Step
S ₇If A = 0, the next step S₉Transition to
To do. Step S₉~ S₁₆Then step S₁~ S₇To
Data and complementary data read and
Since only writing is performed, the description is omitted.

Memory faults include address decoder faults in the memory, word drive and sense circuit faults,
It is roughly divided into cell failures. The address decoder failure includes a failure in which a specific row or column is multiply selected. The failure of the word drive circuit and the sense circuit is a failure such as the opening of the word or the sense line. Even if the row or the column is accessed, the writing is impossible and the reading is only fixed data. (A) Non-selection failure and physically adjacent word lines, sense lines, or circuits such as drivers and sense amplifiers interfere with each other, and adjacent rows or columns are simultaneously accessed (b) multiple selection failure.

For cell failure, the contents of the cell are 1 or 0.
(B) cell fixation failure, short circuit with adjacent cell, sneak from sense line, or interference with other cells due to leakage of defective cell (b) inter-cell interference, etc. .. The marching test is effective for detecting various memory failures.

[0005]

In the conventional marching test, as can be seen from FIG. 4, writing or reading is performed 10 times in total for each bit unit cell. This write or read cycle time is t
_c , memory size is M words, 1 word data length is S
If it is a bit, the time T required for the marching test
_t becomes T _t = 10t _c MS (1). For example, t _c = 1/20 MHz = 50 ns, M = 64
If K word, S = 16 bits or 32 bits,
T _t = 524 ms or 1049 ms, which takes a considerable time.

[0006] By the way, in the embedded system, since the real-time processing is often performed, the marching test described above takes a long time, has a great influence on the work, and the marching test may be difficult to carry out. The present invention has been made in view of such circumstances, and an object thereof is to reduce the test time.

[0007]

[Means for Solving the Problems]

(1) In the test method of claim 1, when the number of bits (word length) of one word at the same address in the RAM under test of the embedded system is S = 2 ⁿ (n is 1 or an integer of 1 or more), Using the 1st to (n + 1) th test patterns of each S bit, 1 is set for the memory cell for 1 word at the same address.
The operation of writing one test pattern at the cycle time, reading the test pattern at one cycle time and checking it is executed for all addresses, and the execution is performed by the first
Through (n + 1) th test pattern are sequentially performed.

Then, the first pattern is set to the upper S /
All 2 bits are "0", all lower S / 2 bits are "1"
And the second test pattern is defined by the upper and lower S
The upper S / 4 bits of the / 2 bit are all set to "0" and the lower S / 4 bits are set to "1", and the third
In the test pattern, all the upper S / 8 bits in the upper and lower S / 4 bits in the upper and lower S / 2 bits are all “0”, and the lower S / 8 bits are all “1”,
In the same manner, the fourth to nth test patterns are created,
In the (n + 1) th test pattern, MSB is “1”, LSB is “0”, and each bit in between is arbitrary.

(2) In the test method of claim 2, in the method (1), an arbitrary pattern in the first to n-th test patterns is changed to a complement pattern and the first to n-th test patterns are changed. Corresponding to the bit at the common position of the pattern being fixed to “1” or “0”,
The bit at the common position of the (n + 1) th test pattern is set to "0" or "1".

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a CPU of an embedded system
Considering that the (central processing unit) accesses the RAM in word units, consider a marching test in word units. The number of 1-word test patterns used should be kept to the minimum necessary. So first of all, word table S = 2,4
The number of data patterns in the case of 8 and 16 will be considered successively with reference to FIG.

In the case of word length S = 2 bits There is no interference between 2-bit cells forming one word and they are independent of each other by writing and reading data a = 01 (1 is LSB). .. However, in that case, the LSB is fixed to 1 and the MSB is fixed to 0. Since it is necessary to write and read different data of 1 and 0 to and from the same cell in order to improve the defect detection capability, the complement data b = 10 of the data a is also written and read. Therefore, the number of patterns is N _D = 2.

In the case of word length S = 4 bits To check the independence between the cells of 4 bits forming one word, (a) to check the independence between the cells of the upper 2 bits and the cells of the lower 2 bits 1-word data a = upper 2-bit data 00 and lower 2-bit data 11
0011 is required. To check the independence of each cell of the upper 2 bits, it is sufficient to have the data 01 as described in the above. The same applies to the cell of the lower 2 bits.
One word of data b = 0101 is required. However, since the MSB is fixed to 0 and the LSB is fixed to 1 only with the data a and b, it is necessary to add the data 1xx0 (x may be 1 or 0) in which the MSB is 1 and the LSB is 0 as described in. .. Therefore, in FIG. 2B, the complement data c = 1100 of the data a is used.

When Word Length S = 8 Bits Data a in FIG. 2C is data for checking independence between cells of upper 4 bits and cells of lower 4 bits,
The data b is the upper 2 bits in each of the upper and lower 4 bits.
The data for checking the independence between the bit cell and the cell of the lower 2 bits, and the data c is the data for checking the independence between adjacent cells of 2 bits which are the same 0 or 1 in b. The data d has the MSB fixed to 0 and the LSB fixed to 1 only for the data a, b, and c, so that the complement data of the data a is added to avoid it. When S = 8, the required number of patterns is N _D = 4.

When word length S = 16 bits: Five kinds of data a to e are obtained in the same manner as. The data e is the complement data of the data a. In addition, the 16 numbers of each digit of the hexadecimal number are 0, 1, 2,
... When represented by 9, A, B, C, D, E, and F, data a to e
Is hexadecimal (HEX; hexadecimal), a = HEX (00FF); b = HEX (0F0F); c
= HEX (3333); d = HEX (5555); e =
It can also be expressed as HEX (FF00). The number of patterns required is N _D = 5.

Assuming that the word length S is S = 2 ⁿ (2), when S = 2, 4, 8 and 16, n = 1, 2,
Since the numbers are 3 and 4, it is understood that n + 1 data patterns are enough to perform the marching test in word units.

The set of test patterns shown in FIGS. 2B to 2D is an example, and the present invention is not limited to this. For example, complement data of arbitrary data can be used, but it is necessary to set the (n + 1) th data so that no cell in one word is fixed to 0 or 1.
As another example of the set of test patterns, the complement data of all the patterns in FIGS. 2B to 2D can be used.

The marching test in units of words is carried out, for example, in accordance with the flowchart of FIG. 1, using the data a to e when the word length S = 16 bits. First, the data a is written in all the addresses (step S ₁ ), then A = 0 is set (step S ₂ ), and the data a is read in one cycle time and checked. the writing in one cycle time (step S _3). It is checked whether or not the address is A = N (step S ₄ ), and if it is not, A = A + 1 is set (step S ₅ ), and step S ₃ is repeated. If A = N in step S ₄ , the process proceeds to step S ₆ to read data b and write data c (step S ₆ ). The operation of step S ₆ is sequentially performed from address A = N to address A = 0. Even operation from the following steps S ₉ to S ₁₈ omitted because it is similar. Like this one at address A
The writing or reading of the data a to e in the memory cells for words is performed in 1 cycle time per data.

The software for executing the flowchart of FIG. 1 is stored in the program memory 2 in the embedded system 1 of FIG. The test patterns (check data) a to e are also stored in the program memory 2. The CPU 3 executes the software stored in the program memory 2, and the RAM (memory to be checked)
Read / write check 5 is performed. The result of the read / write check is output to the outside via the I / O 6.

The time T _t required for marching test of the word unit of the invention, the (n + 1) number of one word of the memory cells of sequential same address test pattern write cycle time t _c, read cycle time t _c Since this is done for all addresses, it is expressed as T _t = 2t _c M (n + 1) (3). M is a memory size. For example, as in the conventional example, word length S = 16 bits or 32 bits (n = 4 or 5), M = 64K words, t _c = 1/2
If 0 MH _Z = 50 ns, then T _t = 32.8 ms or 39.
It will be 3 ms. T _t = 524 ms or 1049 in the conventional example
Each is shortened to 1/10 or less compared to ms. In the conventional example, the test time T _t increases in proportion to the word length S, but in the present invention, T _t is proportional to n + 1 = (log ₂ S) +1, so that the word length S is changed from 16 bits to 32 bits. _However, the increase in the test time T _t is slight.

[0020]

As described above, according to the present invention, when the word length is S = 2 ⁿ , n + 1 S-bit test patterns are used, and 1 word is used for one word of memory cells at the same address. By writing or reading one test pattern for all addresses in cycle time sequentially for n + 1 test patterns, it is possible to significantly reduce the test time compared to the conventional bit-unit marching test. Becomes

[Brief description of drawings]

FIG. 1 is a flowchart showing a RAM testing method of the present invention.

FIG. 2 is a diagram showing an example of a test pattern used in the present invention.

FIG. 3 is a block diagram of an embedded system to which the RAM testing method of the present invention is applied.

FIG. 4 is a flowchart of a conventional marching test.

Claims (2)

[Claims] 1. The number of bits (word length) of one word at the same address of the RAM under test of the embedded system is S = 2.
^{When n} (n is 1 or an integer greater than or equal to 1), the first to (n + 1) th test patterns of each S bit are used, and one test is performed at one cycle time with respect to one word of memory cells at the same address. The operation of writing a pattern, reading the test pattern in one cycle time and checking the pattern is executed for all addresses, and the execution is performed for the first to (n +) th.
1) The test patterns are sequentially performed, and the upper S / 2 bits of the first test pattern are all “0”, the lower S / 2 bits are all “1”, and the second test pattern is each of the upper and lower bits. All the higher S / 4 bits in the S / 2 bit are set to “0” and all the lower S / 4 bits are set to “1”, and the third test pattern is set to the upper position in each of the upper and lower S / 2 bits. And higher S in each lower S / 4 bit
/ 8 bits are all “0”, lower S / 8 bits are all “1”, and in the same manner, the fourth to nth test patterns are created, and the (n + 1) th test pattern is set to MSB “1”, A method for detecting a failure of a RAM in an embedded system, characterized in that the LSB is "0" and each bit in between is arbitrary. 2. The method according to claim 1, wherein an arbitrary pattern in the first to nth test patterns is changed to a complement pattern, and a bit at a common position of the first to nth test patterns is "1". Or, the bit at the common position of the (n + 1) th test pattern is set to "0" or "1" in response to being fixed to "0". RAM failure detection method.