JPS59101100A - Data comparing system - Google Patents

Data comparing system

Info

Publication number
JPS59101100A
JPS59101100A JP57211884A JP21188482A JPS59101100A JP S59101100 A JPS59101100 A JP S59101100A JP 57211884 A JP57211884 A JP 57211884A JP 21188482 A JP21188482 A JP 21188482A JP S59101100 A JPS59101100 A JP S59101100A
Authority
JP
Japan
Prior art keywords
data
comparison
written
memory
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57211884A
Other languages
Japanese (ja)
Other versions
JPS6356570B2 (en
Inventor
Yukiharu Tsukada
塚田 幸春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57211884A priority Critical patent/JPS59101100A/en
Publication of JPS59101100A publication Critical patent/JPS59101100A/en
Publication of JPS6356570B2 publication Critical patent/JPS6356570B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To execute the comparison test without noticing a write data at the comparison of data by writing the data of an optional repetitive pattern as a write data and comparing a part of the data and other readout data at readout. CONSTITUTION:A data pattern written in a write data memory 4 is written from a processor MPU7 at WRITE. As the data pattern, for example, a repetitive data of ''1234'' is used. A data is written from the memory 4 to a test device 1. The repetitive pattern of 16-Byte is written by using a low-cost 4-bit of a Byte counter 3 as an address. The 1st 16-Byte of a READ data is written in a comparison data memory 5 at READ. Data after the next and succeeding data are written in an READ data memory 6 and compared with the data written in the memory 5 at the same time by a comparator circuit 8. The repetitive data in 16-Byte attains the comparison by using a low-order 4-bit of the Byte counter as the address data of the memory 5 in this case.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はデータ比較方式、特に記憶装置のデータ書き込
み、読み出し試験におけるデータ比較方式に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data comparison method, particularly to a data comparison method in a data write/read test of a storage device.

(2)従来技術と問題点 従来、記憶装置のデータ書込み、読み出し試験において
は比較データは試験機であらかじめ用意されたデータと
の比較のみによシ試験を行っていた。そのために、特定
のデータパターンの試験しかできなくて、試験内容が不
充分であるばかシか、試験機側には比較用のデータを設
ける必要があった0 (3)発明の目的 本発明は上記従来の欠点に鑑み、任意のデータパターン
により書込み/読み出し試験を行い、データの比較時に
曹き込みデータを意識することなく、比較試験が行える
データ比較方式を提供することを目的とするものである
(2) Prior Art and Problems Conventionally, in data writing and reading tests of storage devices, comparison data has only been compared with data prepared in advance by a testing machine. For this reason, either the test content was insufficient because only a specific data pattern could be tested, or it was necessary to provide data for comparison on the testing machine side. (3) Purpose of the Invention The present invention In view of the above conventional drawbacks, the purpose of this invention is to provide a data comparison method that allows writing/reading tests to be performed using arbitrary data patterns and making it possible to perform comparison tests without having to be aware of scrapped data when comparing data. be.

(4)発明の構成 そしてこの目的は本発明によれば記憶装置のデータ書き
込み、読み出し試験において、該書き込みのデータとし
て任意の繰返しパターンのデータを用いて誓き込む手段
と、読み出し時には該誉き込まれたデータの一部とそれ
以外の読み出しデータを比較する比較手段を有し、鳴き
込み、読み出し試験を行うことを特徴とするデータ比較
方式を提供することによって達成される。
(4) Structure and object of the invention According to the present invention, in a data writing/reading test of a storage device, there is provided a means for using data of an arbitrary repeating pattern as data for writing, and a means for using data of an arbitrary repeating pattern when reading data. This is achieved by providing a data comparison method characterized in that it has a comparison means for comparing a part of the stored data with the other read data, and performs a reading test.

(5)発明の笑施例 以下本発明の実施例を図面によって詳述する。(5) Examples of inventions Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明によるデータ比較方式を実現するための
ブロック構成図、第2図は本発明によるデータ比較方式
の説明図である。
FIG. 1 is a block diagram for realizing the data comparison method according to the present invention, and FIG. 2 is an explanatory diagram of the data comparison method according to the present invention.

第1図において、1は試験装置を示し、記憶装置へのデ
ータ書き込み及び読み出し試験の操作を実行指令する。
In FIG. 1, reference numeral 1 denotes a test device, which commands execution of data write and read test operations to the storage device.

2はビット−バイト変換回路、3はバイトカウンタ、4
は書き込みデータメモリであシ、誉き込みデータパター
ン全書き込むメモリ、5は比較データメモリであシ、読
み出しデータのうちの最初の16バイト分を予め書き込
んでおくメモリ、6は読み出しデータメモリ、7は開側
1月プロセッサ、8は比較回路である。以下に、本発明
##:手段を用いて、記憶装置のデータ曹込み、及びデ
ータ睨み出しについて説明する。
2 is a bit-byte conversion circuit, 3 is a byte counter, 4
is a write data memory, a memory in which all the honorary write data patterns are written, 5 is a comparison data memory, a memory in which the first 16 bytes of read data are written in advance, 6 is a read data memory, and 7 1 is the open side processor, and 8 is the comparison circuit. Below, using the means of the present invention, data swarming and data surfacing of a storage device will be explained.

(1ン WRITE 時 まず制御用プロセッサ7よシデータバスを経由して書き
込みデータメモリ4にWRITEするデータパターンを
警き込む。データパターンとしては、例えば12341
234・・・・・・・・・1234”の1234”の繰
シ返しデータを用いる。次に省き込みデータメモリ4よ
シ試験装置にデータを省き込む。この時Byteカウン
タ3の下位4ビツトをアドレスとして使用することによ
り、16Byteの繰シ返しパターンを書くことができ
る。
(At the time of WRITE, the control processor 7 first warns the data pattern to be written to the write data memory 4 via the data bus.The data pattern is, for example, 12341.
234...... 1234'' of 1234'' repetition data is used. Next, the data is saved from the save data memory 4 to the test device. At this time, by using the lower 4 bits of the Byte counter 3 as an address, a 16-byte repeating pattern can be written.

(+D  READ時 まずREADデータの最初の16 Byteを比較デー
タメモリ5に曹き込む。次のREADデータからはRE
ADデータメ七り6に書き込むと同時に先に比較データ
メモリ5に誉き込んであるデータと比較回路8にて比較
する。この時、Byteカウンタの下位4ビットt−比
較データメモリ5のアドレスデータとして使用すること
によ516Byteの緑シ返しデータで比較ができる。
(+D At the time of READ, the first 16 Bytes of READ data are saved to the comparison data memory 5. From the next READ data, RE
At the same time as writing into the AD data memory 6, a comparison circuit 8 compares the data with the data previously written into the comparison data memory 5. At this time, by using the lower 4 bits of the Byte counter as the address data of the comparison data memory 5, the comparison can be made with 516 bytes of green return data.

尚、比較結果が一致しなかった時、 Byteカウンタ
を制御用プロセッサ7に通知することでエラーのByt
e位協°ヲ知ることができる。さらにその値より比較デ
ータメモリ5および耽出しデータメモリ6をアクセスす
ることによシ、比較データエラーデータを知ることがで
きる。
Furthermore, when the comparison results do not match, the Byte counter is notified to the control processor 7 so that the error Byte can be detected.
You can learn about e-rank cooperation. Further, by accessing the comparison data memory 5 and the indulgence data memory 6 from the value, the comparison data error data can be known.

本実施例においては、WRITE/READデータとし
て1セクタ単位データ数256Bytet−使用してい
る。
In this embodiment, 256 bytes of data are used in one sector unit as WRITE/READ data.

(6)発明の効果 以上、詳細に説明したように、本発明のデータ比較方式
によれば試験データとして誉き込むデータは、任意のデ
ータパターンで良く、データの読み出し比叡時に試験機
でデータのパターンの意識をすることなくデータの比較
試験が行える。また、試験機側に比較用のデータを設け
る必要がなくなシ、試験機の構成が簡単になるといった
効果大なるものである。
(6) Effects of the Invention As explained in detail above, according to the data comparison method of the present invention, the data to be read as test data may be any data pattern, and the data can be read by the testing machine at the time of data reading. Data comparison tests can be performed without being aware of patterns. Furthermore, there is no need to provide data for comparison on the testing machine side, and the configuration of the testing machine becomes simpler, which is a great advantage.

°4、図面の簡単な説明 第1図は本発明によるデータ比較方式を実現するための
一構成図、第2図は読出しデータとして使われる繰返し
データの一例を説明する図である。
4. Brief Description of the Drawings FIG. 1 is a block diagram for realizing the data comparison method according to the present invention, and FIG. 2 is a diagram illustrating an example of repeated data used as read data.

図面において、1は試販装置、2はビット−バイト変換
回路、3はバイトカウンタ、4は書き込みデータメモリ
、5は比較データメモ1八 6は欣与出しデータメモリ
、7は制御用プロセッサ、8は比較回路をそれぞれ示す
In the drawings, 1 is a trial sales device, 2 is a bit-byte conversion circuit, 3 is a byte counter, 4 is a write data memory, 5 is a comparison data memory 18, 6 is a reward data memory, 7 is a control processor, 8 indicate comparison circuits, respectively.

Claims (1)

【特許請求の範囲】[Claims] 記憶装置のデータ省き込み、読み出し試験において、該
書き込みのデータとして任意の繰返しノくターンのデー
タを用いて書き込む手段と、読み出し時には訳書き込ま
れたデータの一部とそれ以外の読み出しデータを比較す
る比較手段を有し、書き込み、読み出し試験を行なうこ
とを特許とするデータ比較方式。
In a data write/read test of a storage device, there is a method for writing data using any number of repeated turns of data as the write data, and when reading data, a part of the written data is compared with other read data. A patented data comparison method that includes comparison means and performs write and read tests.
JP57211884A 1982-12-02 1982-12-02 Data comparing system Granted JPS59101100A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57211884A JPS59101100A (en) 1982-12-02 1982-12-02 Data comparing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57211884A JPS59101100A (en) 1982-12-02 1982-12-02 Data comparing system

Publications (2)

Publication Number Publication Date
JPS59101100A true JPS59101100A (en) 1984-06-11
JPS6356570B2 JPS6356570B2 (en) 1988-11-08

Family

ID=16613218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57211884A Granted JPS59101100A (en) 1982-12-02 1982-12-02 Data comparing system

Country Status (1)

Country Link
JP (1) JPS59101100A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123555A (en) * 1984-11-20 1986-06-11 Alps Electric Co Ltd Printer-controlling system
JPS6195540U (en) * 1984-11-28 1986-06-19

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03150372A (en) * 1989-11-02 1991-06-26 Mitsubishi Electric Corp Method and apparatus for etching
JPH03149777A (en) * 1989-11-02 1991-06-26 Tokyo Electric Power Co Inc:The Load control device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247345A (en) * 1975-10-13 1977-04-15 Advantest Corp Pattern generating equipment
JPS5743252A (en) * 1980-08-28 1982-03-11 Toshiba Corp Method for generating test pattern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247345A (en) * 1975-10-13 1977-04-15 Advantest Corp Pattern generating equipment
JPS5743252A (en) * 1980-08-28 1982-03-11 Toshiba Corp Method for generating test pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123555A (en) * 1984-11-20 1986-06-11 Alps Electric Co Ltd Printer-controlling system
JPS6195540U (en) * 1984-11-28 1986-06-19
JPH0525893Y2 (en) * 1984-11-28 1993-06-30

Also Published As

Publication number Publication date
JPS6356570B2 (en) 1988-11-08

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