JPS6321999B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory testing device.

Semiconductor memories (hereinafter referred to as IC memories) are becoming increasingly larger in capacity, supported by demands for smaller devices and higher performance. Generally, as the capacity of IC memory increases, the cost per bit and system performance improve. However, IC
Increasing the capacity of memory is faced with the limits of manufacturing technology,
It has become extremely difficult to expect perfect quality products, improve yield, and achieve cost per bit advantage. However, even if an IC memory contains some defective bit cells, if the cost per bit and memory performance are superior, it may not be discarded.
It is expected that utilization technology that masks such defective bits will be promoted.

The purpose of the present invention is to collect information on whether or not the number of defective bits in IC memory is within an allowable range and to minimize the number of addresses that should be masked, thereby making it possible to test even semiconductor memories that include defective bits. The purpose of the present invention is to provide testing equipment for

The present invention is characterized by comprising means for determining whether the number of defective bits among the bits of a semiconductor memory is within a predetermined range, and means for collecting information for minimizing the number of addresses containing defective bits. at the point,
For example, there is a means for counting the fail bits of the IC memory under test, a means for parallel accessing the map memory of the fail bits, a means for calculating the minimum number of included lines based on the row line and column line of the fail bit, and a means for counting the number of lines included in the row line and column line of the fail bit. The present invention is characterized in that it is provided with a means for adding information in the map memory of the corresponding fail bit to all bit fail and applying it as a pass/fail determination mask signal for subsequent tests.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an IC memory testing apparatus according to an embodiment of the present invention. Computer 1 in the upper left block is a computer built into the test equipment (hereinafter referred to as CPU), which transfers various test conditions to each hardware, imports results, etc. according to the interpretation of the test program. It has the function of controlling the progress of the test. The block below it, Interface 2, is an interface circuit between the computer 1 and the tester hardware. The timing generator 3 in the leftmost block sends timing signals to the memory 8 and the like. The pattern generator 4 in the block on the right is a pattern generator for memory testing.
It algorithmically generates input/output data, clock timing control, and other real-time control signals at high speed. The driver 5 in the block below is a high-speed pulse driver that converts digital to analog level as a signal to the IC memory under test 6 (hereinafter referred to as MUT 6). Block 7 to the right of MUT 6 is a comparator and judgment logic circuit that slices the output signal from the MUT at an analog level, converts it to a digital value, compares it with the expected output from the pattern generator, and generates a match/mismatch signal. be. The memory 8 in the lower left block is a fail bit map memory (hereinafter referred to as FAIL BIT MEM) that is accessed in accordance with the address of the MUT 6 and stores defective bit information in the defective bit position of the MUT 6.
It is. The bit information is transferred to the CPU 1 through the interface 2 after one series of tests is completed,
It is possible to display bitmaps. The counter 9 in the lower right block is a fail bit counter and is capable of counting the total number of defective bits in the MUT 6.

FIG. 2 shows a block diagram of a large-capacity IC memory to be tested in an embodiment of the present invention. Address signals X (X ₁ , X ₂ , ..., X _N ) 13, Y (Y ₁ , Y ₂ , ...,
Y _M ) 14 is applied to the memory cell 11 via the X line decoder 12 and the Y line decoder 10, respectively, and as the capacitance increases, the number of signals increases. Therefore, the address of the large capacity IC memory is
Multiplex Xi and Yj to send and receive signals, and
Efforts are being made to reduce the number of memory pins. IC memories that include some defective bits are X ₁ , X ₂ , ..., X _N ,
Included in the specific combination of Y ₁ , Y _{2 .} . . , Y _M. That is, it can be defined by the address of the X line decoder 12 (hereinafter referred to as a row line) and the address of the Y line decoder 13 (hereinafter referred to as a column line). However, a column line and a low line that include some defective bits in IC6 are detected,
By selecting a line that minimizes the sum of the lines and using that line as a mask, it becomes possible to apply it to a device that takes advantage of the characteristics of large-capacity IC memory. In particular, the test equipment in this embodiment performs the primary determination of the conditions for partial bit defective memory using the fail bit counter 9, and the FAIL BIT counter 9.
Transfer to CPU1 by high-speed access of MEM8,
A CPU calculation function that minimizes the total sum of row lines and column lines that include defective bits, and a secondary judgment as to whether the sum of the selected line is within the allowable range, and if this is a part of the allowable range. If the MUT is a bit defective, the selected row line and column line are transferred to the pattern generator 4,
It is equipped with a function that allows failure information to be written at high speed into the FAIL BIT MEM 8 corresponding to the line in question, and this information to be applied as a pass/fail judgment mask signal for the output of the MUT 6 during subsequent testing. That is, a primary judgment is performed and if the number of defective bits is less than a specified value, it is not discarded but is treated as a good product. However, defective bits among them must be masked to destroy their memory function. On the other hand, some of the detected defective bits are included in the same column line or the same row line. Therefore, instead of using the total number of defective bits as the total number of addresses to be masked, defective bits included in the same column line and row line are considered to be common, and all bits on that column line or row line are masked. It is like a mask. For this purpose,
All you have to do is look at the row/column addresses of the defective bits stored in the FAIL BIT MEM8 and make the same addresses common. As a result, all detected defective bits located at the same row address or column address are shared, and it is only necessary to mask the minimum number of addresses necessary, improving the efficiency of using good bits. . FAIL BIT MEM8 performs the same access to the MUT6 address in real time during a series of MUT6 tests, but when transferring this information to CPU1, parallel access is possible according to the bit length of CPU1. High-speed information transfer (DMA)
mode). The fail bit counter 9 operates in real time to test a series of MUTs 6, and has the function of single counting the occurrence of duplicate failure bits in response to repeated accesses to the same address of the MUT 6. According to the example memory block in FIG. 2, the memory capacity is 2N+M, the number of row lines is ^2N , and the number of column lines is ^2M . If R row lines or column lines or both are masked and used, the MUT6 operates correctly, and if R is an acceptable standard, then R is the required fail bit count number for the primary judgment.
The larger value of either ×2 ^N or R×2 ^M may be used.
Then, if the first judgment is passed, FAIL BIT
According to the information in MEM8, the minimum row line column line mask data is calculated. Naturally, the standard for the secondary determination is R.

Thus, according to the test device according to the invention,
It is now possible to not only test completely non-defective products, but also to sort out partially defective products, making it possible to supply large-capacity IC memories that were previously discarded at a low cost, which has a significant effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a test device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a large capacity memory to which the present invention is directed. In the figure, 1...computer, 2...interface, 3
...Timing generator, 4...Pattern generator, 5...
High-speed pulse driver, 6... IC memory under test, 7
...Comparator and judgment logic circuit, 8...Memory for fail bit map, 9...Fail bit counter, 10...Y line decoder, 11...memory cell, 12...X line decoder, 13...X
(X ₁ , X ₂ , ..., X _N ), 14...Y (Y ₁ , Y ₂ , ...,
_YM ).

Claims (1)

[Claims] 1. means for detecting defective bits in a semiconductor memory; means for determining whether the total number of detected defective bits is within a predetermined range; and means for determining whether the total number of defective bits is within the range. 1. A semiconductor memory testing device comprising means for obtaining information that minimizes the number of address lines containing defective bits when it is determined.