JP2002042485A - Test apparatus for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory test apparatus in which the defect relieving and analyzing time is shortened. SOLUTION: This semiconductor memory test apparatus for analyzing a defective memory cell of a DUT in a defect relieving and analyzing section and replacing as defective memory cell by a spare memory cell is provided with: a fail memory of an address fail memory for transferring the normal/ defective conditions of a plurality of bits existing in the same address as an address having a defective memory cell of the DUT to a fail buffer memory of the defect relieving and analyzing section with the prescribed format; and a fail buffer memory of the defect relieving and analyzing section for storing the prescribed format data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which is a DUT (semiconductor memory device under test) in which a spare memory cell for repairing a defective memory cell is prepared.
The present invention relates to a device for testing a UT, and a semiconductor memory test device having a defect repair analysis unit.

[0002]

2. Description of the Related Art First, an outline of a semiconductor memory test apparatus will be described. FIG. 4 shows a basic block diagram of the semiconductor memory test apparatus. The test processor 31 controls the entire apparatus, and supplies a control signal to each unit via a tester bus. The pattern generator 32 generates an applied pattern to be applied to the DUT (semiconductor memory device under test) 30 and an expected value pattern to be applied to the pattern comparator 37. In a semiconductor memory test apparatus, a pattern generator 32 is generally used.
ALPG (Algorithmic Pattern Generator). The ALPG is a pattern generator that generates a test pattern by calculation using a register having an internal calculation function.

A timing generator 33 generates a timing pulse signal to obtain a test period signal and a test timing of the entire apparatus and supplies the timing pulse signal to a pattern generator 32, a waveform shaper 34, a comparator 36, a pattern comparator 37 and the like. Take the timing of the test. The waveform shaper 34 shapes the applied pattern from the pattern generator 32 into a test signal waveform, and supplies a test signal to the DUT 30 via the driver 35.

[0004] The response signal read from the DUT 30 is:
The voltage is compared by the comparator 36, and the resulting logic signal is given to the pattern comparator 37. Pattern comparator 37
Performs a logical comparison between the logical pattern of the test result from the comparator 36 and the expected value pattern from the pattern generator 32 to detect a match / mismatch, and determines the quality of the memory cell of the DUT 30. The test result fail information is stored in an address fail memory (AFM) 38 in a pattern generator 32.
Is stored in the storage position corresponding to the address information from the server.

[0005] The address fail memory 38 is a DUT 3
“1” is written to the address corresponding to the 0 fail cell. That is, it is a one-to-one fail bitmap with the DUT 30.

When the test is completed, the fail memory 3
The information of 8 is sent to a defect repair analysis unit (MRA: Memory Repair Analysis) 10 by a dedicated bus for MRA shown in FIG.
Is transferred to the fail buffer memory (FBM) 11 at high speed. Based on the data information in the fail buffer memory 11 of the failure repair analysis unit 10, failure analysis can be performed by the CPU (electronic computer) of the failure repair analysis unit 10, by a personal computer, by a workstation (WS: Work Station) 20, or the like. Done. The present invention relates to a failure analysis of the failure repair analysis unit 10.

In order to perform these failure analysis, a so-called bitmap data processing method has been conventionally used. This bitmap data processing method is a method of checking whether each cell of the fail buffer memory 11 is normal or defective and reading out defective cell information.

FIG. 5 is a conceptual diagram of bitmap data. The word configuration of the fail buffer memory 11 includes a 4-bit configuration, an 8-bit configuration, a 16-bit configuration, and the like in accordance with the configuration of the DUT 30, and has a memory card for each bit. In this specification, description will be made with a 4-bit configuration. The word configuration refers to a plurality of bit configurations stored at the same address of the DUT. As shown in FIG. 5, the memory cells of the memory card are arranged in a two-dimensional array, and have a column (Row) address and a row (Column: Co).
lumn) address and specified. Assuming that the number of rows (C) and the number of columns (R) are 1 to n, the memory cell is RiC
i (i = 1 to n). This memory card is provided for each bit, and the four cards are a bit 0 memory 40, a bit 1 memory 41, a bit 2 memory 42, and a bit 3 memory 43. In the case of a 32-bit configuration, there are 32 memory cards. Then, if each cell of each memory card is defective, “1” is set, and if it is normal, “0” is set.
Is written.

FIG. 6 shows an example of a description of a defective bit. The bit 0 memory 40 has R1, C1, R2, C2..., The bit 1 memory 41 has R1, C2, R2, C3, and so on, the bit 2 memory 42 has R1, C3, R2, C4. In the memory 43, R1, C1, R2, C5,... And “1” are written in defective bits up to the address n.

[0010] In the test of the development department, since defective memory cells may occur irregularly, the cause of the defective occurrence is clarified and the aim is to eradicate the defective memory cells. Since the manufacturing department manufactures and tests the semiconductor memory device completed by the development department, defective memory cells are generated in the manufacturing process, and a defective memory cell for each bit, a defective memory cell of a row address line, There are many defective memory cells in the column address line. Therefore, the test of the DUT 30 is performed at the wafer stage in the manufacturing process, and a partially defective chip is rescued to make a good semiconductor memory device.

FIG. 7 is a diagram for explaining the remedy of a defect in a wafer in a manufacturing process. FIG. 7A shows a remedy when there are many defective memory cells at the column (R) address. Defective memory cells are indicated by x. The Ri address having the defective memory address is replaced with a spare memory cell in a non-defective spare row. FIG. 7B shows a remedy when there are many defective memory cells at the row (C) address. The Ci address having the defective memory address is replaced with a spare memory cell in a spare column.

[0012]

The test of the DUT 30 performed at the stage of the wafer in the manufacturing process can be sufficiently performed by the conventional apparatus to perform the defect repair analysis. However, in the above-described bitmap data processing method, data is read out from the fail buffer memory 11 for each bit at each address, and the CPU checks whether or not the memory cell is defective, performs an operation, and performs a defect repair analysis. There is a drawback that it takes a long time.

For example, there is a calculation result that a transfer time including a read time and a write time when the number of failures is 1% is 400 ms in a DUT of 8 M words and 8 bits of 64 M bits. SUMMARY OF THE INVENTION An object of the present invention is to reduce the time required for defect repair analysis of a semiconductor memory device as a DUT.

[0014]

In order to achieve the above object, the present invention provides a method for storing a fail buffer memory included in a defect repair analysis unit from a conventional bit map system of a DUT memory to a defective memory cell of the DUT. In this method, the address is stored in a predetermined format that describes the good and bad of a plurality of bits existing at the same address. Address and good / bad bits are “0” and “1”
Described as

The predetermined format data is generated by the hardware of the fail memory, and is transferred from the fail memory to the fail buffer memory of the failure repair analysis unit and then from the fail buffer memory to the CPU to perform the failure repair analysis. This is for high-speed operation. The transfer time including the read time and the write time is 2.25 m when calculated under a constant condition using a 64 Mbit (8 M × 8 bit) DUT.
There is a calculation example in which s can be reduced to about 1/180 times the conventional value. Further, the defect repair analysis time can be reduced as compared with the conventional case.

Further, in order to obtain a high-speed operation, a new defect repair operation means is provided in the operation section of the defect repair analysis section so as to operate with the above-mentioned predetermined format data. Further, a defect repair control means may be newly provided in the control unit of the defect repair analysis unit so as to perform the defect repair operation using the above-mentioned predetermined format data as required. Next, the configuration of the present invention will be described.

The first invention is an invention in which data used for defect repair analysis is converted into a predetermined format data which is newly generated by hardware from a conventional bitmap system. That is, a test signal is applied to the DUT, a logical pattern of a response signal from the DUT and an expected value pattern from the pattern generator are logically compared by a pattern comparator, and the result is temporarily stored in a fail memory of an address fail memory. A semiconductor memory test apparatus for performing a transfer to a fail buffer memory of a failure repair analysis unit, a failure memory analysis of the DUT by the failure repair analysis unit, and an analysis for replacing the defective memory cell with a spare memory cell. A fail memory of an address fail memory for transferring to a fail buffer memory of a failure repair analysis unit in a predetermined format describing an address having a defective memory cell and a plurality of bits of good / bad present at the same address; A failure buffer memory of a defect repair analysis unit for storing data That is a semiconductor memory test equipment.

The second invention is a new predetermined format.
This is the optimal configuration for handling data. That is, the test signal is applied to the DUT, the logical pattern of the response signal from the DUT and the expected value pattern from the pattern generator are logically compared by the pattern comparator, and the result is temporarily stored in the fail memory of the address fail memory. The data is transferred to the fail buffer memory of the defect repair analysis unit,
A semiconductor memory test apparatus for analyzing a defective memory cell of a UT and performing an analysis for replacing a defective memory cell with a spare memory cell, comprising: an address having a defective memory cell stored in a fail buffer memory of a defect repair analysis unit; A semiconductor memory test apparatus including a calculation unit having a built-in defect repair analysis unit for performing a defect repair analysis using predetermined format data describing a plurality of bits of good or bad existing at the same address.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a diagram showing the status of a defective address and a defective memory cell in a DUT of the present invention, and FIG. 3 is an implementation of predetermined format data used in the present invention. An example diagram is shown.

First, a description of a defective memory cell will be described with reference to FIGS. In order to make the description easy to understand, the description will be made using 4-bit data.
In the case of a 32-bit configuration, the number of bits is 32 bits. FIG. 2 is a situation diagram in which the defective bits for each bit shown in FIG. 6 are collectively described for each address of the DUT 30 at the address having the defective bit.

FIG. 3 is a diagram showing an embodiment in which the situation diagram in which the addresses of the DUT 30 in FIG. That is,
An address having a defective memory cell of the DUT 30 and a plurality of bits of good or bad present at the same address are described, and the data is formed into predetermined format data. The present invention transfers format data using the predetermined format data from the conventional bitmap system,
The calculation is performed using it.

FIG. 1 shows an embodiment of the present invention. 4 are denoted by the same reference numerals. Pattern comparator 37
Logically compares the response logic pattern from the DUT 30 with the expected value pattern from the pattern generator 32, and gives the result of the pass / fail to the fail memory 38. The number of memory cells at the same address of the DUT 30 is, for example, 4 bits or 3 bits.
There are two or more such as two bits, which are output simultaneously. Therefore, there are also a plurality of pattern comparators 37, and logic comparison is performed simultaneously in parallel.

The fail memory 38 includes the pattern comparator 3
7, and stores the data along with various information such as address information from the pattern generator. According to the present invention, only data having a defective memory cell in a semiconductor memory cell at the same address is stored in a predetermined format by hardware, and is transferred to and stored in the fail buffer memory 11 of the defect repair analysis unit 10.

That is, in this semiconductor memory test apparatus,
New predetermined format data is generated by the hardware of the fail memory 38 of the address fail memory, and the generated predetermined format data is sent to the defect repair analysis unit 1.
0 to the fail buffer memory 11, and the fail buffer memory 11 stores the data in the predetermined format / data format. This is the first invention.

In order to efficiently and quickly perform defect repair analysis using predetermined format data stored in the fail buffer memory 11, a new defect repair analysis means 13 is added to the operation unit 12 of the defect repair analysis unit 10. Provide. This is the second invention. The defect repair control means 1 is newly added to the control unit 14.
When 5 is provided, it is desirable to provide 5 because control becomes easy.

[0026]

As has been described in detail above, the present invention provides a new bitmap processing method which describes an address having a defective memory cell and a plurality of bits of good or defective at the same address. Predefined format
It is a method of processing with data. In order to realize this, it was possible to reduce the processing time by solving the problem with hardware without using software. The semiconductor memory test apparatus further includes a defect repair analysis unit 13 newly provided in the operation unit 12 of the defect repair analysis unit 10 in order to increase the operation speed.

DUT is 64M bits (8M × 8 bits)
Then, when the transfer time including the read time and the write time is calculated under a certain condition such as the number of failures of 1%, for example, it is reduced to about 1/180 times as compared with the conventional bitmap data processing method as described above. High-speed processing.
Although the high speed ratio depends on the conditions, if the DUT has a higher degree of integration and has 32 bits, the transfer time will be further reduced. As described above, since the present invention can greatly reduce the time required for the defect repair analysis, the technical effect is large in practical use.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a state of a defective address and a defective memory cell (bit) in a DUT according to an embodiment of the present invention.

FIG. 3 is an embodiment diagram of predetermined format data used in the present invention.

FIG. 4 is a block diagram of a semiconductor memory test apparatus.

FIG. 5 is a conceptual diagram of bitmap data.

FIG. 6 is a situation diagram showing an example of a description of a defective bit;

FIG. 7 is an explanatory diagram of remedy for a wafer in a manufacturing process.

[Explanation of symbols]

10 Defective repair analysis unit (MRA: Memory Repair Anal
ysis) 11 Fail buffer memory (FBM: Failure Bu
ffer Memory) 12 operation unit 13 defect repair analysis means 14 control unit 15 defect relief control means 16 I / O (input / output) 20 workstation (WS: Work Station) 23 storage unit 30 DUT (semiconductor memory device under test) 31 Test Processor 32 Pattern Generator 33 Timing Generator 34 Waveform Shaper 35 Driver 36 Comparator 37 Pattern Comparator 38 Fail Memory (Failure Memory) 40 Bit 0 Memory 41 Bit 1 Memory 42 Bit 2 Memory 43 Bit 3 Memory

Claims (2)

[Claims] A test signal is applied to a DUT, a logical pattern of a response signal from the DUT and an expected value pattern from a pattern generator are logically compared by a pattern comparator, and the result is stored in a fail memory of an address fail memory. In a semiconductor memory test apparatus for temporarily storing and transferring the data to a fail buffer memory of a defect repair analysis unit, analyzing the defective memory cell of the DUT by the defect repair analysis unit, and replacing the defective memory cell with a spare memory cell, A fail memory of an address fail memory for transferring to a fail buffer memory of the defect repair analysis unit in a predetermined format describing an address having a defective memory cell of the DUT and a plurality of bits of good / bad present at the same address; Failure buffer of failure repair analysis unit that stores specified format data The semiconductor memory test apparatus characterized by comprising memory and, the. 2. A test signal is applied to a DUT, a logical pattern of a response signal from the DUT and an expected value pattern from a pattern generator are logically compared by a pattern comparator, and the result is stored in a fail memory of an address fail memory. In a semiconductor memory test apparatus for temporarily storing and transferring the data to a fail buffer memory of a defect repair analysis unit, analyzing the defective memory cell of the DUT by the defect repair analysis unit, and replacing the defective memory cell with a spare memory cell, A defect for performing a defect remedy analysis using predetermined format data describing an address having a defective memory cell stored in a fail buffer memory of the defect remedy analysis unit and a plurality of bits of good / bad present at the same address. A semiconductor memory test apparatus, comprising: an arithmetic unit having a built-in repair analysis unit.