JPH05242695A - Semiconductor test device - Google Patents

Abstract

PURPOSE:To suppress memory capacity of a buffer memory of a test device required for testing a large capacity DUT. CONSTITUTION:This device is provided with a fail memory 5 which stores a test result concerning a tested device having a reserve memory, mask memories 11 and 13 which have capacity of same extent as the reserve memory and store data for masking an address to be stored, and a controller 4 which mutually transfers data between any line or row of the fail memory 5 and the mask memory 11, 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, it is used for testing a device having a redundant circuit, especially a memory.

[0002]

2. Description of the Related Art Generally, a semiconductor device with a redundant circuit, especially a memory, is tested by an apparatus having a structure shown in FIG. That is, first, in the first test, the device under test 2 (hereinafter referred to as DUT) is the pattern generator 1
It receives the address and data output from and outputs the corresponding output data. The comparator 3 compares the output data with the address from the pattern generator 1 and, as a result, when it is determined that a specific element of the DUT 2 is defective, this result is output to the controller 4. In response to this, the controller 4 receives the fail memory 5 as a buffer memory corresponding to the address from the pattern generator 1.
Write defect information to the address. Here, the fail memory 5 has the same memory capacity as the memory capacity of the DUT 2.

After the completion of the first test, the content of the fail memory 5 is read to output a defective address, and based on the defective address, it is determined whether or not the redundant circuit of the DUT 2 can be replaced. There is.

If the result of determination is that replacement is possible, a second test is executed. In this case, in order to reduce the test time, D
A mask memory 6 as a buffer memory having the same capacity as the memory capacity of the UT 2 is provided, the contents of the fail memory 5 are transferred to the mask memory 6, and the contents of the mask memory 6 are written when the defect information is written to the fail memory 5. Compared with the above, if the same address is defective, it is not written, thereby omitting the pass / fail judgment process for the same defective address.
However, the contents of the fail memory 5 are all erased after being transferred to the mask memory 6. The above processing is summarized in FIG.
It becomes like

[0005]

In the above-mentioned test apparatus, one test of the DUT requires two memory capacity.
A buffer memory with double the memory capacity is required. This is because as the capacity of the DUT increases and the number of simultaneous measurements of a large number increases, the memory capacity of the buffer memory necessary for the test apparatus also becomes enormous.

The semiconductor test apparatus of the present invention has been made in view of such a problem, and its purpose is to reduce the memory capacity of the buffer memory required for the test to the DUT.
It is possible to suppress the memory capacity of the buffer memory of the test apparatus, which is required at the time of testing the large capacity DUT, by making it possible to perform the test with the same capacity as.

[0007]

In order to achieve the above-mentioned object, a semiconductor test apparatus of the present invention comprises a first memory for storing a test result of a device under test having a spare memory, and a capacity of the spare memory. Data having a capacity similar to that of the second memory for storing data for masking an address, an arbitrary row or column of the first memory, and the second memory are stored. And means for transferring them to each other.

[0008]

That is, according to the present invention, the data for storing the test result of the device under test having the spare memory by the first memory and masking the address by the second memory having the same capacity as the spare memory. And further transfer data between any row or column of the first memory and the second memory.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of one embodiment of the present invention will be described with reference to FIG.

Generally, the capacity of the spare memory of the redundant circuit of the DUT is about 4 columns × 4 rows or 8 columns × 8 rows, and if there are more defective addresses, replacement becomes impossible. Therefore, in this embodiment, the row and column mask memories 11 and 13 having the same capacity as the spare memory of the DUT are provided, and the contents of arbitrary columns or rows of the fail memory 5 are transferred to the mask memories 11 and 13. Have a function. At the same time, it also has a function of transferring the address to the dedicated replacement row and column registers 10 and 12. As a result, the mask memory can be configured only with the same memory capacity as the spare memory of the DUT. Hereinafter, it will be described in more detail with reference to FIGS. 1 and 2.

As shown in FIG. 1, the test result of the DUT is written in the fail memory 5. D based on this information
It is determined whether or not replacement is possible with the spare memory of the UT, and as a result, as the replacement target, for example, the row address 01,0
3, when the column addresses 02 and 04 are obtained, the data in the corresponding row or column is transferred to the row mask memory 11 and the column mask memory 13 based on this address, and the addresses are respectively replaced to the row address registers. 10, stored in the replacement column address register 12. After transfer, fail memory 5
All the data in will be deleted.

By this operation, the mask data is set in the mask memories 11 and 13, and in the next test, based on the data in the replacement address registers 10 and 12 and the mask memories 11 and 13, the fail memory 5 having the defective address is set. Write. However, if the same address is defective, writing to the fail memory 5 is not performed.

Further, in the case where the determination as to whether replacement is possible is made again in the subsequent tests, the mask memories 11 and 13 are used.
This is possible by re-transferring the data of 1 to the original address of the fail memory 5.

FIG. 2 is a block diagram of FIG.
3 is a circuit configuration example of the controller 4 of FIG. The row address input to the controller 4 is the replacement row address register 1
By taking the negation of the exclusive OR with 0, the result of agreement or disagreement of both data is obtained. Further, the column address input to the controller 4 is input to the selector 14, the corresponding address in the row mask memory 11 is selected, and the data of that address is read.

A write inhibit signal is obtained by taking the logical product of the read mask data and the comparison result of the row addresses. Inverted signal of this signal and controller 4
Mask processing is performed by taking the logical product of the write signals input to. In this way, it is possible to write the test result in the fail memory 5 by performing the mask processing in real time during the test execution.

[0016]

According to the present invention, when mask data is used to store a defective address in the test of a semiconductor device with a redundant circuit, the buffer memory of the test apparatus, which has conventionally required twice the capacity of the DUT, has almost the same capacity as the DUT. It is possible to test with only the memory capacity.

For example, in the test of 1M DRAM, conventionally, 2
Although Mbit buffer memory was required, in the present invention, 1 Mbit fail memory and 0.006 Mbit (51
2 bits x 4 rows, 1024 bits x 4 columns), total 1.006 Mb
It can be tested with the buffer memory of it.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a semiconductor test apparatus of the present invention.

FIG. 2 is a diagram showing a configuration of a controller shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional semiconductor test apparatus.

FIG. 4 is a diagram for explaining the operation of the semiconductor test device of FIG.

[Explanation of symbols]

1 ... Pattern generator, 2 ... DUT, 3 ... Comparator, 4 ... Controller, 5 ... Fail memory, 6 ... Mask memory,
10 ... Substitution row address register, 11 ... Row mask memory, 12 ... Substitution column address register, 13 ... Column mask memory, 14 ... Selector, 15 ... EX-NOR circuit, 16
... AND circuit, 17 ... NOT circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 11/413 11/401 29/00 301 B 9288-5L 6628-5L G11C 11/34 341 C 6628 -5L 371 A

Claims (1)

[Claims] 1. A first memory for storing a test result of a device under test having a spare memory, and a memory having a capacity similar to that of the spare memory and storing data for masking an address. 2. A semiconductor test apparatus comprising: a second memory; an arbitrary row or column of the first memory; and means for mutually transferring data between the second memory.