JPH05144297A - Memory tester - Google Patents

Abstract

PURPOSE:To facilitate creation of program by writing a test pattern signal for a memory to be tested into an emulator and reading out the test pattern data, while interlocking with reading operation of the memory to be tested, at the time of read/write operation. CONSTITUTION:A main pattern generator 12 generates a signal PA which is fed to the RAM part 1 and the pseudo-PAM part 31 of a memory MUT to be tested thus transferring data to an SAM part 2 and a pseudo-SAM part 32 from the same address. Consequently, data read out from the same address, of the RAM part 1 and the pseudo-SAM part 31 are stored in the SAM part 2 and the pseudo-SAM part 32. The data are subsequently read out in the form of signals PSAM, PD from the SAM part 2 and the pseudo-SAM part 32 and a sub-logic comparator 23 compares the signal PD, as a sub-expected value signal, with the signal PSAM thus making a decision of go/no go.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a testing device for a memory used, for example, for displaying a graphic screen.

[0002]

2. Description of the Related Art As a memory used for capturing an image signal and generating an image signal, a memory capable of capturing a serial signal at a high speed and reading data stored in the memory as a serial signal at a high speed is provided. is there. As shown in FIG. 8, this memory includes a random access memory section (hereinafter referred to as a RAM section) and a serial memory section 2 (hereinafter referred to as a SAM).
(Referred to as a section), and the RAM section 1 and the SAM section 2 can read independently and write data D ₁ , D ₂ , D ₃ ... In the RAM section 1 as shown in FIG. Data D ₁ , D ₂ , D ₃ written in the RAM section 1 in a cycle
Is transferred to the SAM unit 2, and the transferred data D ₁ ,
An operation of serially reading D ₂ , D ₃ ... From the SAM section 2 at high speed (hereinafter referred to as a read transfer operation), and serial data D ₁ , D at the SAM section 2 at high speed as shown in FIG.
_{, 2} , D _3, ..., and the serial data D ₁ , D ₂ , D _3, ... taken at high speed are transferred to the RAM section 1 in parallel and written to an arbitrary address of the RAM section 1, and the data from the RAM section 1 is transferred. An operation of reading D ₁ , D ₂ , D _3, ... In parallel (hereinafter referred to as a write transfer operation) can be performed.

This type of memory can perform more complicated operations, but since it is a function not directly related to the present invention, its explanation is omitted here. FIG. 11 shows a schematic configuration of a conventional test apparatus for testing this type of memory. In the figure, MUT indicates a memory under test. The memory under test MUT has the RAM section 1 and the SAM section 2 as described above.

A main timing generator 11, a main pattern generator 12 and a main logic comparator 13 are provided for the RAM section 1. The main timing generator 11 outputs timing signals T _A and T _B, and
_A is input to the main pattern generator 12, and the main pattern generator 12 outputs a main pattern signal P _A and a main expected value signal P _B. The main pattern signal P _A is R
It is input and written in the AM section 1. The read output of the RAM section 1 is given to the main logic comparator 13, and compared with the main expected value signal P _B given from the main pattern generator 12 in the main logic comparator 13, and it is determined that a defective unit is owned by the detection of a mismatch. ..

Since the RAM part 1 has been tested independently, the main pattern generator 12 has only to output the main pattern signal P _A and the main expected value signal P _B given to the RAM part 1. There is a correspondence relationship between P _A and the expected value signal, and a program for generating the main expected value signal P _B can be created relatively easily.

[0006]

On the other hand, the program for generating the expected value signal necessary for testing the read transfer operation and the write transfer operation described above has a drawback that it becomes considerably complicated. That is to test the read transfer operation, generates a main pattern signal P _A from the main pattern generator 12, the main pattern signal P _A is temporarily stored in the RAM section 1, the transfer from the storage address to the SAM unit 2 Then, the operation is read out from the SAM unit 2 as a serial signal, and the serial logical signal is compared by the sub logical comparator 23.

A sub expected value signal given to the sub logical comparator 23.
Issue P_DMust be given by the sub-pattern generator 22
Absent. This is a timing that RAM 1 and SAM 2 are different.
This is to enable testing even in asynchronous (asynchronous). See you
Of the in-pattern generator 12 and the sub-pattern generator 22
Since there is no means to send and receive signals between
The pattern generator 22 independently outputs from the main pattern generator 12.
Main pattern signal P applied_AThe sub associated with
Expected value signal P_DMust occur. I mean, Mei
Pattern signal P_AConsidering what was output as
Expected value signal P _DMust be generated. others
From the sub pattern generator 22 to the sub expected value signal P_DTo
It's a hassle to write programs to generate
ing.

On the contrary, when the write transfer operation is tested, the sub pattern signal P _C from the sub pattern generator 22 is changed to S.
The sub pattern signal P _C is transferred from the SAM section 2 to the RAM section 1 while being written in the AM section 2, and an arbitrary address of the RAM section 1 (this write address is the main pattern generator 12
(Provided from the above), the sub pattern signal P _C is written, the sub pattern signal P _C is read and input to the main logic comparator 13, and the main logic comparator 13 outputs the main expectation signal from the main pattern generator 12. Compare with the value signal P _B.

Therefore, in this case as well, the main pattern generator 1
2 has to generate the main expected value signal P _B in consideration of the contents of the sub pattern signal P _C output by the sub pattern generator 22, so a program for generating the main expected value signal P _B is created. Is troublesome. As described above, conventionally, it is troublesome to create a program for generating the expected value signal used for the read transfer test and the write transfer test, and the time and effort required for creating the program are large.

[0010]

According to the present invention, an emulator that operates in the same manner as the memory under test MUT is provided, and the same test pattern signal as the test pattern signal given to the memory under test MUT is provided to the emulator. Similarly to the above, the read transfer and the write transfer operations are performed, and the read transfer output or the write transfer output is given to the logical comparator as an expected value signal.

According to the structure of the present invention, the read-transferred data and the write-transferred data can be obtained in the emulator, so that the read-transferred data and the write-transferred data can be used as expected value signals. .. Therefore, the main pattern generator and the sub pattern generator need only generate the test pattern signal, and need not generate the expected value pattern signal. Therefore, it is not necessary to create a program for generating an expected value signal, and thus a program for operating this type of memory test apparatus can be inexpensively created.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an outline of a memory testing device according to the present invention. In FIG. 1, parts corresponding to those in FIG. 11 are designated by the same reference numerals. EML shown in FIG. 1 represents an emulator. The emulator EML is composed of a device having the same function as the memory under test MUT. Even if the functions are the same, the writing and reading speeds are several times faster than those of the memory under test MUT.

That is, a RAM section (hereinafter referred to as a pseudo RAM section) 31 having a storage capacity equal to or larger than that of the RAM section 1 of the memory under test MUT, and an SA of the memory under test MUT.
A SAM unit having the same function as the M unit 2 (hereinafter, pseudo SA
The memory under test MU
Test pattern signals P _A and P _C exactly the same as the test pattern signals P _A and P _C given to T are simulated R of the emulator EML.
It is given to the AM section 31 and the pseudo SAM section 32, and the same operation as the memory under test MUT is performed.

Therefore, for example, the RAM of the memory under test MUT
When performing the operation test of only the unit 1, the memory under test MU
A RAM unit 1 T, then gives a main pattern signal P _A to the pseudo RAM unit 31 from the main pattern generator 12, a main pattern signal P _A to the desired address of the RAM portion 1 and the pseudo SAM unit 31 of the memory under test MUT Write and read this.

The pattern signal P _B read from the pseudo RAM unit 31 is applied to the main logic comparator 13 as the main expected value signal P _B , and the main logic comparator 13 reads the pattern signal P _B from the RAM unit 1 of the memory under test MUT. Read output P
Compare with _RAM to judge pass / fail. By this comparison operation, the quality of the RAM section 1 of the memory under test MUT can be tested.

The test of the read transfer operation is performed as follows. The main pattern generator 12 generates a main pattern signal P _A. The main pattern signal P _A is the memory under test MUT
Of the RAM section 1 and the pseudo RAM section 31. RA
The pattern signal P provided to the M section 1 and the pseudo RAM section 31.
_A includes a read transfer command, and the read transfer command causes the RAM unit 1 and the pseudo RAM unit 31 to start from the same address, respectively, from the SAM unit 2 and the pseudo SAM unit 3.
The operation of transferring data to 2 is executed.

By the execution of this transfer operation, the SAM section 2 and the pseudo SAM section 32 store the data read from the same address in the RAM section 1 and the pseudo RAM section 31. The stored data is read from the SAM unit 2 and the pseudo SAM unit 32 as the signals P _SAM and P _D , and input to the sub logical comparator 23. In the sub-logical comparator 23, the pseudo SAM
The signal P _D read from the unit 32 is used as a sub-expected value signal,
The quality is judged by comparing with the signal P _SAM read from the SAM unit 2. By this comparison operation, R of the memory under test MUT is
It is possible to test whether the data written in the AM section 1 is correctly transferred to the SAM section 2 and read correctly from the SAM section 2.

The write transfer test is performed by the sub pattern generator 22.
Sub-pattern signal P output from _CSuspected to be SAM part 2
A similar SAM unit 32 is provided and RA is provided from each SAM unit 2 and 32.
Addresses specified by the M section 1 and the pseudo RAM section 31
Data to the computer. RAM unit 1 and pseudo RAM unit 31
The data transferred to and stored in the
P from the similar RAM section 31_RAMAnd P_BRead as
It is then input to the main logic comparator 13. Pseudo at this time
The signal P read from the RAM section 31_BIs the main expected value
Issue P_BAnd this main expected value signal P_BAnd RAM section 1
Signal P read from_RAMAnd to judge the quality
It Based on this judgment, the write transfer operation of the memory under test MUT
You can test the work.

From the above description, it can be understood that the emulator EML operates as a generator of the expected value signal in a pseudo manner. The present invention further proposes the configuration of the emulator EML. Here, problems that occur when the emulator EML is configured will be described. When a read transfer and a write transfer are performed in the memory under test MUT, the memory under test M in the emulator EML.
Similar to the UT, it is difficult to transfer data at one time.

For example, when the RAM unit 1 of the test memory MUT has a structure of, for example, 256 K words × 4 bits (1 M bits), if the row address and the column address are both 9 bits, the data transferred at one time is 1 Row address, that is, 512 words x 4 bits = 2048
This is because the bit data must be sent at once.

In other words, in the memory under test MUT, 204
It can be seen that an 8-bit data bus is formed. Therefore, in the emulator EML, a data bus of 2048 bits must be provided in the same way as the memory under test MUT. However, if the 2048-bit data bus is formed by actual wiring other than the integrated circuit, the emulator becomes large and expensive. Further, as the generation of the memory under test increases, the capacity also increases, and the amount of transferred data also increases accordingly, so that the emulator becomes larger and more expensive.

For this reason, in the emulator EML, the number of bits of the transfer data bus between the pseudo RAM unit 31 and the pseudo SAM unit 32 must be reduced as much as possible. The present invention also proposes a configuration of an emulator EML which can transfer multi-bit data at a high speed with a bit number as small as possible. The emulator EML proposed by the present invention divides all data to be transferred into a bit number which is an integer fraction of this data bit number, and the divided bit number data is time-divided and sequentially transferred as a data block. It was done.

FIG. 2 shows the configuration of the emulator EML that employs this sequential transfer method. Emulator EML is pseudo R
The point configured by the AM unit 31 and the pseudo SAM unit 32 is as described above. The pseudo RAM unit 31 includes a RAM buffer memory 31A, an address selector 31B, an address controller 31C, and a mask controller 31.
D, a data multiplexer 31F, and a write data formatter 31E.

The RAM buffer memory 31A has a storage capacity equal to or larger than that of the RAM section 1 of the memory under test MUT by a plurality of memories. At the time of data transfer, all the memories are accessed at once to read and write. For example, if the RAM buffer memory 31A has a data width of 1
When configured with 64 bit memories, it is possible to read and write 64 bits at a time and transfer the data.
It corresponds to a data block (hereinafter, described as 64 bits unless otherwise specified).

The RAM controller 31H controls the entire emulator EML and divides the operation cycle of the emulator EML into n + 1 units as shown in FIG. 3 by the first transfer instruction from the main pattern generator 12 (see FIG. 1). Then, in this first cycle, the RAM buffer memory 31
A control signal is sent to each control unit such that A is a cycle for random access and the remaining n cycles are cycles for accessing the RAM buffer memory 31A for data transfer. The value of n can be taken from 0 to an appropriate value in proportion to the test cycle of the MUT.

The address selector 31B receives the address signal MAR supplied from the main pattern generator 12 as shown in FIG.
The RAM buffer memory 31A is rearranged into a format as shown in FIG. 1 and sent to the address controller 31C as an address for accessing the RAM buffer memory 31A, and the memory select address bits are given to the SAM controller 32A via the RAM controller 31H.

The mask controller 31D is a write per bit of the RAM buffer memory 31A (bits masked in the multi-bit data memory are not written,
The mask data for the function is generated, and the mask data for the write mask transfer is generated. The pseudo SAM unit 32 includes a SAM controller 32A and a write data formatter 32E.
, A data multiplexer 32B, a SAM buffer memory 32C, and a read data formatter 32D.

The SAM buffer memory 32C is shown in FIG.
Multiple register files RF _A~ RF_DBy
Composed. In the example of FIG. 5, four register files RF
_A~ RF_DAnd a multiplexer MUX
Shows the case. Each register file RF_A~ RF_DHaso
Reads in RAM buffer memory 31A at once
And the number of bits that can be written (in this example,
It has a capacity of 64 bits) and has a pseudo RAM unit 31 and a pseudo S
When data is transferred to and from the AM unit 32, the reading and
Write. Each register file RF_A~ RF_DHaso
The SAM controller provided in each SAM controller 32A
Right pointer SWP and SAM read pointer SRP
One of them is designated to read and write.
It

The SAM controller 32A controls the SAM buffer memory 32C under the control of the RAM controller 31H. The data multiplexer 32B performs an operation of switching between a read transfer state and a data flow in a state other than the read transfer state. The write data formatter 32E and the read data formatter 32D match the data width of the emulator with the data width of the memory under test MUT, and the RAM buffer memory 31A is composed of a large number of memories. Perform the action.

The read transfer operation is executed as follows.
Be done. RA is executed by the first read transfer instruction after the test is started.
The M controller 31H is an operating system for the emulator EML.
The random access cycle T as shown in FIG.
_RAMAnd the data transfer cycle T ₁.... T_nDivide into
It (Subsequent division will be performed even in cycles that are not transfer operations.
).

The data transfer address is latched by the address controller 31C, and the memory select address is SA.
It is latched by the M controller 32A. Read transfer instructions are sent from the RAM controller 31H to the SAM controller 3
Sent to 2A. The SAM controller 32A internally includes a status flag register RF-SFR for each register file RF _{A to} RF _D as shown in FIG.
A data transfer request signal is sent to the M controller 31H. R
The AM controller 31H receives the data transfer request signal RE
In response to Q, all the 64 memory bits of the RAM buffer memory 31A are read in the data transfer cycles T _{1 to} T _n ,
It is sent to the pseudo SAM unit 32C. SAM controller 32A
Status flag register RF-S, for example the register file RF _A in the register file RF _A ～RF _D
FR is set (data is valid), and the data sent to this register file RF _A is written at once. R
When the AM controller 31H transfers data once, the AM controller 31H shown in FIG.
The transfer block address shown in (1) is advanced by 1 to make an address for accessing the next data block.

In this example, four register files RF _{A to} RF _D are provided in the SAM buffer memory 32C,
SAM controller 3 until data is sent to all of them
2A keeps outputting the data transfer request signal REQ. When the data is written in all the four register files RF _{A to} RF _D , the output of the data transfer request signal REQ (see FIG. 2) is stopped.

When the data is sent to the SAM buffer memory 32C, the sub pattern generator 22 (see FIG. 1) outputs S data.
The sub-control signal SUBC is given to the AM controller 32A, the register files RF _{A to} RF _D in the SAM buffer memory 32C are read by the sub-control signal SUBC, and the read data is sent to the sub logical comparator 23 as the sub expected value signal P. Give as _D.

In the present invention, when one register file, for example, RF _A is read, the next register file R
In order to read F _B , the SAM read pointer SRP is incremented by 1, and the status file register of the register file which has been read, for example, RF _A is reset. By resetting the status flag register, the SAM controller 32A outputs the data transfer request signal REQ to the RAM controller 31H. When the data transfer request signal REQ is output, the RAM controller 31H transfers data from the RAM buffer memory 31A in any of the divided transfer cycles T _{1 to} T _n .

In this way, the SAM buffer memory 32
When even one of the register files RF _{A to} RF _{D in} C becomes empty, data is sequentially transferred to the empty register file, and the sub-expected value can be generated from the pseudo SAM unit 32. In this example, 64-bit data is sent to the register file at one time and is read out in 4-bit units from the pseudo SAM unit 32, so that an expected value for 16 words in the SAM unit 2 can be created by one transfer. That is, it is sufficient that the data transfer is performed once for the expected value 16 times output of the SAM unit 2. The reading of the register files RF _{A to} RF _D is not performed by the control of the main pattern generator side, but
Since the sub-pattern generator 22 is controlled similarly to the memory under test MUT, reading can be performed asynchronously with the timing on the main pattern generator 12 side.

After the transfer of the memory under test MUT, the RAM section 1 and the SAM section 2 are asynchronously accessed at different timings. On the emulator EML side as well, the access to the buffer memories 31A and 32C is performed similarly to the memory under test MUT in the divided random access cycles, so that the asynchronous emulator EML is realized. The main expected value signal and the sub expected value signal can be obtained by reading the pseudo RAM unit 31 and the pseudo SAM unit 32 of the emulator EML. That is, the memory under test MU
In the state in which the read transfer output P _SAM is output from the SAM unit 2 of T and the sub-expected value signal P _D is output from the pseudo SAM unit 32, the RAM unit 1 of the memory under test MUT and the pseudo RAM of the emulator EML. The unit 31 can arbitrarily read and write. Therefore, even during the test of the read transfer operation, it is possible to independently perform the writing and reading in the RAM unit 1 and the pseudo RAM unit 31 while the SAM unit 2 and the pseudo SAM unit 32 are reading the data. , A read test can be performed.

The write transfer operation is executed as follows. As with the read transfer operation, the test is started and the RAM controller 31H (see FIG. 2) operates the emulator EML with the first write transfer instruction as shown in FIG. 3 in the random access cycle T _RAM and the data transfer cycle T.
Divide into _{1 to} T _n .

The address of the data transfer destination is latched by the address controller 31C by the write transfer command from the main pattern generator 12. Memory select address is S
It is latched by the AM controller 32A. The mask data is latched by the mask controller 31D. When the data transfer destination address is latched in the address controller 31C, the input data from the sub-pattern generator 22 to the register file is provided in the SAM buffer memory 32C RF _A ~RF _D (see FIG. 5) is made possible. For example, a memory select address of RF _{A in} the register file (see FIG.
The writing of data is started from the write start address indicated by (reference). One register file eg RF _A
Is filled with data, the status flag register RF
-SFR is set (data is valid), the state of the SAM write pointer SWP is advanced by 1, and the next register file R
Enter the data in F _B. Subsequent register file R
F _C , RF _D , RF _A , RF _B ...

Status flag register (RF-SF
If even one R) is set, the SAM controller 32A outputs the transfer request signal REQ to the RAM controller 31H. Upon receiving this transfer request signal REQ, the RAM controller 31H writes 64-bit data to the RAM buffer memory 31A at a time during the divided transfer cycles T ₁ ... T _n (FIG. 3). When this writing is completed, the status flag register (RF-SFR) of the written data is reset (data invalid), and a signal is sent to the SAM controller 32A to advance the state of the SAM read pointer SRP (FIG. 5) by one. To send.

Each time the sub pattern generator 22 inputs 4 × 16-bit data to each of the register files RF _{A to} RF _D , 1 is added in addition to the write data (4 bits).
Each data has a bit flag bit, and this flag bit is set every time data is input. As a result, even if 64 bits are simultaneously transferred from the pseudo SAM section 32 to the pseudo RAM section 31 at a time, data in which the flag bit is not set is input to the SAM section 2 unless it is written in the RAM buffer memory. The start address can be arbitrary, not every 16 words (in the case of the data width of 4 bits in this example).

When data is written to the RAM buffer memory 31A by a write transfer operation, the mask data in the data bit direction is masked by the mask data set in the mask controller 31D. FIG. 6 shows the operation status of the register files RF _{A to} RF _D , SRP, and SWP during read transfer. FIG. 7 shows the operation status of the register files RF _{A to} RF _D , SRP, and SWP during write transfer.

[0042]

As described above, according to the present invention, the emulator EM which operates in the same manner as the memory under test MUT.
Since L is provided, the test pattern signal to be written in the memory under test MUT is written to the emulator, transferred by the read transfer operation and the write transfer operation, and the transferred data is read in conjunction with the read operation of the memory under test MUT. By outputting, the main expected value signal P _B and the sub expected value signal P _D can be generated.

As a result, the main pattern generator 12 and the sub pattern generator 22 need only generate the test pattern signal, and need not generate the expected value signal. Therefore, it becomes easy to create a program relating to pattern generation, and it can be expected that the cost required for creating the program will be reduced. After the read transfer, the memory under test MUT is a RAM.
Since it becomes possible to freely access Part 1,
In consideration of this point, according to the present invention, after the read transfer, the RAM part 1 of the memory under test MUT and the pseudo RAM part 31 of the emulator EML are written, and read and compared to test the read transfer operation. Even if there is, the writing and reading test of the RAM section 1 can be performed. Therefore, different types of tests can be executed in parallel at the same time, so that the time required for the tests can be shortened. Further, even if the capacity of the SAM unit 2 (the number of words) increases as the generation of the memory under test MUT progresses, this device can cope with it only by increasing the number of data block transfers, so that this device can be used as it is. can get.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a block diagram for explaining an embodiment of the main part of the present invention.

FIG. 3 is a timing chart for explaining an operating state of the present invention.

FIG. 4 is a diagram for explaining a form of an address signal used in the embodiment of the present invention.

FIG. 5 is a block diagram for explaining the structure of a register file used in the embodiment of the present invention.

FIG. 6 is a diagram for explaining a read transfer operation of a main part of the present invention.

FIG. 7 is a diagram for explaining the operation of the present invention.

FIG. 8 is a block diagram for explaining the configuration of a memory under test.

FIG. 9 is a diagram for explaining a read transfer operation of the memory under test.

FIG. 10 is a diagram for explaining a write transfer operation of the memory under test.

FIG. 11 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 MUT Memory under test 1 RAM section 2 SAM section 11 Main timing generator 12 Main pattern generator 13 Main logic comparator 21 Sub timing generator 22 Sub pattern generator 23 Sub logic comparator 31 Pseudo RAM section 31A RAM buffer memory 32 Pseudo SAM department

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[Procedure amendment]

[Submission date] September 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art As a memory used for capturing an image signal and generating an image signal, a memory capable of capturing a serial signal at a high speed and reading data stored in the memory as a serial signal at a high speed is provided. is there. As shown in FIG. 8, this memory includes a random access memory unit (hereinafter referred to as RAM unit) and a serial access memory unit 2 (hereinafter referred to as SAM unit), and the RAM unit 1 and the SAM unit 2 are independent. In addition to being able to read, RAM as shown in Fig. 9
Part 1 data _{D 1, D 2, D 3} ... writing, data D ₁ that has been written to the RAM unit 1 in the data transfer cycle, D
₂ and D ₃ ... Are transferred to the SAM unit 2 and the transferred data D ₁ , D ₂ , D ₃ ... Are read serially from the SAM unit 2 at high speed (hereinafter referred to as a read transfer operation). ,
FIG serial data D ₁ at a high speed to the SAM unit 2 as shown in 10, D _2, D ₃ ... uptake, the serial data D ₁ of the taken fast, D _2, D ₃ ... parallel to the RAM section 1 Transfer and write to any address in RAM section 1, RA
The operation of reading the data D ₁ , D ₂ , D ₃ ... In parallel from the M section 1 (hereinafter referred to as a write transfer operation) can be performed.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11

Claims (1)

[Claims] 1. A RAM unit capable of random access,
Part of the data written in the RAM section is transferred, the transferred data is stored, and the stored data can be sequentially read as serial data at high speed,
Further, a memory test for testing a memory provided with high-speed serial data that can be externally fetched, and the fetched serial data can be transferred to the RAM unit at a time and stored in the RAM unit. In the device, a pseudo RAM unit in which a memory having a capacity equivalent to that of the RAM unit of the memory to be tested is configured by a plurality of memories capable of simultaneously reading and writing over a plurality of bits, and a memory of the pseudo RAM unit. A plurality of register files having the same capacity are provided and configured, the plurality of register files sequentially enable data transfer to and from the memory of the pseudo RAM unit, and the data transferred from the memory of the pseudo RAM unit is sequentially transferred to each register. Can be read from a file,
A read transfer operation for transferring data from the above memory to another register file while one register file is being read, and data written in each register file are sequentially transferred to the memory constituting the above pseudo RAM unit. A pseudo SAM unit capable of executing a write transfer operation to be stored is provided, and an operation equivalent to a memory to be tested is executed by the pseudo RAM unit and the pseudo SAM unit, and transferred from the pseudo RAM unit to the pseudo SAM unit. The sub-expected value signal for testing the read transfer operation of the memory under test is generated by reading the data from the pseudo SAM section, the data is transferred from the pseudo SAM section to the pseudo RAM section, and the transferred data is transferred to the RAM. By storing the data in the buffer memory and reading the stored data, the memory for testing the write transfer operation of the memory to be tested is tested. Memory test apparatus characterized by being configured to generate an expected value signal.