JP3243763B2 - Memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for a memory used, for example, for displaying a graphic screen.

[0002]

2. Description of the Related Art There is a memory capable of high-speed writing and high-speed reading as an image display memory. As shown in FIG. 2, the memory includes a random access memory unit 1 (hereinafter, referred to as a RAM unit) and a serial access memory unit 2 (hereinafter, referred to as a SAM unit), and the RAM unit 1 and the SAM unit 2 are independent. outside that can be reading Te, the data D ₁ in the RAM section 1 as shown in FIG. 3, D _2, D _3, write ..., data D ₁ that has been written to the RAM unit 1 together with the data transfer cycle, D ₂ ,
D _3, forwards ...... the SAM unit 2, the transferred data D _1, D _2, D _3, referred to as a reading operation (hereinafter this read transfer operation in high speed ...... from SAM 2 serially )
When the serial data D ₁ at a high speed to the SAM unit 2 as shown in FIG. 4, D _2, D _3, captures ..., serial data D ₁ of the taken in this fast, D _2, D _3, the ...... RAM unit 1
To write the data D ₁ , D ₂ , D ₃ ,... From the RAM 1 (hereinafter referred to as the write transfer function). it can.

Although this kind of memory can perform a more complicated operation, it is a function which is not directly related to the present invention, and a description thereof will be omitted here. FIG. 5 shows a schematic configuration of a conventional test apparatus for testing this type of memory. In the figure, MUT indicates a memory under test. The memory under test MUT has the RAM unit 1 and the SAM unit 2 as described above.

A main timing generator 11, a main pattern generator 12, and a main logical comparator 13 are provided for the RAM unit 1. Main timing generator 11
Outputs timing signals T _A and T _B , inputs the timing signal T _A to the main pattern generator 12, and outputs a main pattern signal P _A and a main expected value pattern signal P _B from the main pattern generator 12. Main pattern signal P _A is input to the RAM unit 1.

[0005] The test pattern signal input to the RAM unit 1 is transferred to the SAM unit 2 by a read transfer operation.
The data is read out serially from the section 2 and input to the sub-logic comparator 23. The sub logical comparator 23 is input sub expected value signal P _D from the sub-pattern generator 22, and the sub expected value signal P _D and serially read data is logically compared.

On the other hand to output the sub-pattern signal P _C from the sub-pattern generator 22 during the test of the write transfer operation,
Writing this sub-pattern signal P _C to the SAM unit 2. SA
Subpattern signal written in the M unit 2 P _C is transferred to the RAM unit 1 by the write transfer operation, the input is read from the RAM section 1 to the main logical comparator 13. At this time, the main logical comparator 13 is given a main expected value signal P _B from the main pattern generator 12, and the main expected value signal P _B and the data read out from the RAM unit 1 is logically compared.

[0007]

As described above, conventionally, in order to test the read transfer operation, the sub-pattern based on the main pattern signal written from the main pattern generator 12 to the RAM unit 1 of the memory under test MUT. generator 22 should not not generate a sub expected value signal P _D from and sub-pattern generator to test the write transfer operation 22
It must generate a main expected value signal P _B from the main pattern generator 12 on the basis of the sub-pattern signal written in the SAM unit 2 of the memory under test MUT from. This is to enable testing of the RAM unit 1 and the SAM unit 2 at different timings (asynchronous).

Since there is no means for transmitting and receiving signals between the main pattern generator 12 and the sub-pattern generator 22, the sub-pattern generator 22 independently outputs the main pattern signal P output from the main pattern generator 12. It must generate a sub expected value signal P _D that matches the _a. That must generate a sub expected value signal P _D by considering whether what the output as the main pattern signal P _A. Thus creating a program for generating the sub expected value signal P _D from the sub-pattern generator 22 has become cumbersome to.

[0009] The sub-pattern signal P _C from the sub-pattern generator 22 when testing a write transfer operation in the reverse S
With writing to the AM unit 2 transfers the sub-pattern signal P _C from the SAM unit 2 to the RAM section 1, any address of the RAM portion 1 (the write address main pattern generator 12
With the given) writing sub-pattern signal P _C from the inputs to the sub-pattern signal P _C is read into the main logical comparator 13, a main expected output from the main pattern generator 12 in the main logical comparator 13 compared to the value signal P _B.

Therefore, also in this case, the main pattern generator 1
Since 2 must generate main expected value signal P _B in consideration of the contents of the sub-pattern signal P _C of sub-pattern generator 22 is output, the creation of a program for generating the main expected value signal P _B Is also troublesome. As described above, conventionally, it is troublesome to create a program for generating an expected value signal used for a read transfer test and a write transfer test, and the time and labor required for creating the program are large.

[0011]

According to the present invention, two buffer memories having the same memory capacity as the RAM unit 1 of the memory under test MUT, and two buffer memories provided before and after the two buffer memories are provided. An emulator is constituted by a set of multiplexers and a controller for controlling the operation of these two sets of multiplexers and two buffer memories. The two buffer memories constituting the emulator are equivalent to the pattern signals to be written to the memory under test. Are written and read out from the buffer memory to generate a main expected value signal and a sub expected value signal.

Therefore, according to the present invention, the main pattern generator and the sub pattern generator need only generate a test pattern signal, and do not need to generate an expected value pattern signal. Therefore, since it is not necessary to create a program for generating the expected value pattern signal, a program for operating this type of memory test apparatus can be created at low cost.

[0013]

1 shows an outline of a memory test apparatus according to the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are denoted by the same reference numerals. EML shown in FIG. 1 indicates an emulator. In the present invention, the emulator EML includes two buffer memories 33A and 33B having the same memory capacity as the RAM unit 1 of the memory under test MUX, and multiplexers 32A and 32B provided before and after the buffer memories 33A and 33B, respectively. 34A and 34B, and controllers 31A and 31B for controlling the reading and writing of the buffer memories 33A and 33B and controlling the multiplexers 32A, 32B, 34A and 34B.

The input terminal of the controller 31A is connected to the main pattern generator 12, and the main pattern generator 12
Given main pattern signal P _A from the controller 31
The input terminal of the B gives the sub pattern signal P _C from the sub-pattern generator 22. Controllers 31A and 31B
Are multiplexers 32A and 32B and 34A and 34A in addition to read / write control of buffer memories 33A and 33B.
B switching control is performed.

To test the read transfer operation, read transfer data is written to the RAM unit 1 of the memory MUT under test (the RAM unit 1 is initialized by this writing). The same data is written to the buffer memory 33A of the emulator EML in parallel with writing the read transfer data to the RAM unit 1 of the memory under test MUT. At this time, a signal is sent from the controller 31A to the controller 31B to cause the multiplexer 32B to write the data of the controller 31A into the buffer memory 33B. The same data is written to the buffer memories 33A and 33B by this switching control.

When the writing (initialization) of the memory MUT under test to the RAM unit 1 and the buffer memories 33A and 33B is completed, the memory MUT under test is transferred from the RAM unit 1 to the SAM unit 2.
The data is read from the SAM unit 2 and the read data is output to the sub-logic comparator 23. At the same time, on the emulator EML side, the buffer memory 33B executes a read operation,
4B, the sub expected value signal P _D is supplied to the sub logical comparator 23.
And a test of the read transfer operation is executed.

After operating in the read transfer operation mode, the memory MUT under test transfers data from the RAM unit 1 to the SAM unit 2 once, and reads data from the RAM unit 1 until the next read transfer operation. The operation and the writing operation can be independently executed. For this reason, the present invention is configured such that the RAM unit 1 itself can be tested between read transfer operations. Emulator EM for this
The configuration of L is that the buffer memories 33A and 33B are provided and the multiplexers 32A and 34A and 32B and 34B are provided before and after the buffer memories 33A and 33B.

[0018] That is in the middle of outputting the sub expected value signal P _D for read transfer test from the buffer memory 33B through the multiplexer 34B, the memory under test MUT R
When rewriting the AM unit 1, the write data is supplied from the controller 31A to the buffer memory 33A through the multiplexer 32A, and the data is written to the buffer memory 33A. From the same time the buffer memory 33A as reading data rewritten from the RAM unit 1 after the writing, reading now incorporated elaborate data, the main logic comparator through a multiplexer 34A of the read output as the main expected value pattern signal P _B To the RAM unit 1
Can be independently tested. When the data newly written in the RAM unit is transferred to the SAM unit and read, the multiplexers 32A, 34A and 32A are used.
B and 34B are switched at the same time, and the controller 31B
To access the buffer memory 33A and supply the same to the sub logical comparator 23 through the multiplexer 34B.

As described above, by simultaneously executing the read transfer operation test and the test of the RAM section 1, the test time can be reduced. The write transfer operation test is performed as follows. Before testing the write transfer operation,
RA of memory under test MUT performed before read transfer operation
The initialization of the M unit 1 and the initialization of the buffer memories 33A and 33B are similarly performed.

[0020] Light subpatterns signal P _C for the transfer of the memory under test MUT SAM unit 2 to the sub-pattern generator 2
When two are writing, you write to the buffer memory 33B through the same sub-pattern signal P _C controller 31B- multiplexer 32B. Memory under test M
When a write transfer operation is performed in the UT, the multiplexers 32A, 34A and 32A of the emulator EML are used.
B, 34B simultaneously switched reads the buffer memory 33B by the controller 31A, taken out the read output by multiplexer 34A, by providing a main expected value signal P _B into the main logical comparator 13, the write in the main logical comparator 13 The result of the transfer can be compared, and a test of the write transfer operation can be performed.

[0021] with reading data from the RAM unit 1, while that generated the main expected value signal P _B from the buffer memory 33B, the sub to be subsequently write transfer to the SAM unit 2 of the memory under test MUT pattern it can be written signal P _C. At this time this sub-pattern signal P _C controller 31 B - written in the buffer memory 33A through the multiplexer 32A, the memory under test MUT is operated forward, it reads the data transferred from the RAM unit 1 Te, the data main logic When given to the comparator 13, the multiplexers 32A, 34A and 32B, 34B are switched simultaneously, and the buffer memory 3 is controlled by the controller 31B.
3A reads out, taken out the read output as the main expected value pattern signal P _B through the multiplexer 34A, gives the main logical comparator 13.

In this way, the buffer memories 33A and 33A
3B can be generated main expected value signal P _B during a write transfer operation by utilizing alternately.

[0023]

As described above, according to the present invention,
A bus having the same capacity as the RAM unit 1 of the memory under test MUT
Buffer memories 33A and 33B, and
Control with the multiplexers 32A, 34B and 32B, 34B.
The emulator EML is composed of the rollers 31A and 31B.
And write a test pattern signal to this emulator EML.
And reading it out to generate an expected value signal
The main pattern generator 12 and the sub-pattern
Both the turn generators 22 provide the expected value signal P_BAnd P _DDepart
There is no need to live.

Therefore, the program relating to the generation of the expected value signal can be simplified and the program can be easily created.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory under test.

FIG. 3 is a diagram for explaining a read transfer operation of a memory under test.

FIG. 4 is a diagram for explaining a write transfer operation of a memory under test.

FIG. 5 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

MUT MUT EML emulator 1 RAM unit 2 SAM unit 31A, 31B controller 32A, 34A multiplexer 32B, 34B multiplexers 33A, 33B buffer memory P _B main expected value signal P _D sub expected value signal

Claims (1)

(57) [Claims] 1. A main pattern signal is fetched from outside.
A random access RAM section and a part of data written in the RAM section are transferred, the transferred data is stored, and the stored data is sequentially converted to serial data at high speed. High-speed serial data as a sub-pattern signal can be fetched from the outside, and the fetched serial data can be transferred to the RAM unit at a time and stored in the RAM unit A memory test apparatus for testing a memory having a simple SAM section, the main pattern signal is input, and the output is
Each is input to the second multiplexer, and
The first and third multiplexers and the first buffer memory
A first controller to be controlled, the sub-pattern signal being input, and an output from the first controller
And the second multiplexer respectively.
The second and fourth multiplexers and the second buffer
A second controller for controlling the memory, and the second controller for outputting its output to the first buffer memory.
1 multiplexer and the second multiplexer for outputting its output to the second buffer memory.
2 multiplexers and their outputs to the third and fourth multiplexers, respectively.
Input and the capacity equivalent to the RAM part of the memory under test
Having the first buffer memory and the output thereof to the third and fourth multiplexers, respectively.
Input and the capacity equivalent to the RAM part of the memory under test
Having the second buffer memory and outputting the output to the main logical comparator as an expected value.
And a third multiplexer for outputting the output of the third multiplexer as an expected value to the sub-logic comparator.
A fourth multiplexer, the thus constitute an emulator that works equivalent to the memory under test, writes the main pattern signal and the sub-pattern signal written into the memory under test to the emulator, reads the pattern signal memory testing apparatus configured to generate a main expected value signal and the sub expected value signal from the error <br/> emulator by.