JP3284949B2 - Apparatus and method for storing bus trace in storage device and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for storing a bus trace in a storage device. The present invention relates to a device and method for storing a bus trace in a device.

[0002]

2. Description of the Related Art Conventionally, in order to observe the state of a bus in the development of an apparatus, the state of the bus has been observed with an external measuring instrument. Observation at has become difficult.

For this reason, a tracer for storing and observing information on a bus has been increasingly provided inside the apparatus. For example, as disclosed in Japanese Patent Application Laid-Open No. 62-286136, a special storage device for tracing is used as a storage device for trace data, and the trace data is stored in the storage device.

Next, a conventional bus trace to a memory device will be described with reference to the drawings.

FIG. 3 is a block diagram showing a bus trace to a conventional memory device.

The trace data register 2 is a register for temporarily storing the trace data. The trace data is transferred from the trace data register 1 to the shift register 3 and the condition of the data in the trace condition register 4 is compared with the condition of the comparison circuit 5. . If the comparison results match, data is stored in the trace memory 1 from the trace data register 2. In such a configuration, unnecessary hardware (HW) has increased in normal operation. Therefore, the capacity of the storage device for storing the trace data is generally limited, and it has not been possible to store sufficient trace data.

[0007]

The first problem with the conventional bus trace to a memory device is that if a trace storage device is separately provided, an unnecessary hardware trace is required during normal operation.
Will increase.

The reason is that the trace memory, which is a storage device for tracing, is not used during normal operation.

The second problem is that if the amount of unnecessary HW is reduced, the traceable area is limited.

The reason is that the capacity of the storage device for storing the trace data is reduced.

An object of the present invention is to use a commonly used storage device as a storage area for tracing, thereby reducing the amount of unnecessary hardware and storing a bus trace in a storage device having a large trace area. And to provide a method.

[0012]

SUMMARY OF THE INVENTION According to the present invention, there is provided an apparatus and method for storing a bus trace in a storage device, comprising: a storage device connected to a bus; Means, data generating means for generating data from bus information, tracing data generating means for generating data for tracing bus information, and tracing for generating an address for storing a data tracing result Address generation means, n address selection and holding means corresponding to each of the n storage means for selecting and holding an address from the address generation means and an address generated from the trace address generation means, and n storage means For each of them, n pieces of data that select and hold data from the data generating means or data from the trace data generating circuit. Output selection means for selecting the output of the storage means by the address of the address generation means during normal operation and selecting the output of the storage means by the address generated from the trace address generation means at the time of trace output; Output holding means for temporarily storing data selected by the above and also serving as a shift register at the time of trace data output, and an instruction for storing data on the bus in the corresponding storage means at the time of writing of normal operation, and a trace result of data on the bus. Is output to the corresponding storage means, and at the time of reading out the normal operation, a data output instruction to the corresponding storage means, an instruction to the output selection means for selecting the output of the corresponding storage means, and an The instruction to store the trace result in the corresponding storage means and the output holding means to the bus Outputting an instruction to operate as output holding means, performing a trace data output instruction to the corresponding storage means at the time of toasting operation, and instructing the selection means to select an output of the corresponding storage means; A control circuit is provided for instructing the output holding means to store the output of the selecting means, and instructing the output holding means to operate as a shift register when the trace data is output.

[0013]

FIG. 1 is a block diagram showing an embodiment of an apparatus and a method for storing a bus trace in a storage device according to the present invention.

Referring to FIG. 1, the bus management circuit 1 determines whether the information from the bus 19 is address information or data for an address.

The address generation circuit 2 generates an address to be given to the storage means 14, 15, 16, 17 from the information of the bus management circuit 1.

The data generation circuit 3 generates data to be written into the storage means 14, 15, 16, 17 indicated by the address generated by the address generation circuit 2 based on the information of the bus management circuit 1. .

The tracing data generation circuit 4 receives the address information and the data information from the bus management circuit 1, and according to the conditions determined by the control circuit 5.
Generate data for tracing.

The control circuit 5 operates according to an external instruction.
Storage means for storing trace data,
Storage means 14, 1 for storing data of the bus 17 and the bus 19;
5, 16, 17 and address selection and holding means 6, 7, 8, 9;
A write address is generated for a storage unit for controlling traces 12 and 13 to store trace data, a write / read control signal is written for storage units 14, 15, 16, and 17, and an output storage unit 18 is controlled. Is controlled to switch to a data register or a shift register.

The address selection holding means 6, 7, 8, 9
In accordance with an instruction from the control circuit 5, an address from the address generation circuit 2 or a trace address from the control circuit 5 is selected and stored.

Data selection holding means 10, 11, 12, 1
Reference numeral 3 selects and stores data from the data generation circuit 3 or data from the trace data generation circuit 4 according to an instruction from the control circuit 5.

The storage means 14, 15, 16, 17 store the address selection holding means 6,
Data selection holding means 1
Data from 0, 11, 12, and 13 are stored, and data is output by a read signal.

The output selection circuit selects one of the outputs of the storage means 14, 15, 16, 17 according to the control circuit 5.

When the output holding means 18 operates as a data output holding means in accordance with an instruction from the control circuit 5, the output holding means 18 temporarily stores data from the output selector 20 and outputs it to the bus 19, and the control circuit 5 operates as a shift register. In this case, the temporarily stored data is sequentially shifted and output.

Next, the operation of the embodiment of the present invention will be described in detail.

In an interleaved storage device, the storage device is divided into several independently readable and writable banks,
By shifting the reading and writing of the banks little by little, access to continuous addresses can be apparently performed at high speed. Memory 14, 15, 16, 17
When each of them is regarded as one bank, the control circuit 5 determines which of the memories 14, 15, 1
6, 17 are determined as storage memory units for trace data or data storage units for buses. According to the determination, the address registers 6, 7, 8, and 9 determine whether to select an address from the address generation circuit 2 or an address from the control circuit 5.

The data registers 10, 11, 12, and 13 also determine whether to select data from the data generation circuit 3 or information from the trace data generation circuit 4 according to an instruction from the control circuit 5.

For example, the memories 14 and 15 are memory units for storing trace data, and the memories 16 and 17 are memory units for storing data on the bus 19.

First, consider the case where writing from the bus 19 is instructed. Information from the bus 19 is transmitted to the bus management circuit 1
After that, the information is input to the address generation circuit 2 and the trace data generation circuit 4. The address generation circuit 2 generates an address from the input information, and the address is input to the memory 17 through the address register 6.

The control circuit 5 generates a write address for tracing, and the write address is input to the memory 15 through the address register 8. Information on the address is input from the bus 19 to the bus management circuit 1, and the data from the bus management circuit 1 is taken in by the data generation circuit 3 and the trace data generation circuit 4. The data fetched by the data generation circuit 3 is stored in a write address line of the memory 17 to which a write signal is given from the control circuit 5 through the data register 10 when writing is instructed. On the other hand, the data captured by the trace data generation circuit 4 is stored in the data register 12.
, A write signal is given from the control circuit 5 and is stored in the line of the write address generated from the control circuit 5.

Since the writing speed of the memory is lower than the operating speed of the bus, the next bus data cannot be written to the same memory. Therefore, the next bus data is
After being input to the bus management circuit 1, the address generation circuit 2,
The data is input to the trace data generation circuit 4. The address generation circuit 2 generates an address from the input information, and the address is input to the memory 16 through the address register 7. The control circuit 5 generates a write address for tracing, and the write address is input to the memory 14 through the address register 9. Information on the write address is input from the bus 19 to the bus management circuit 1, and the data from the bus management circuit 1 is captured by each of the data generation circuit 3 and the trace data generation circuit 4. The data fetched by the data generation circuit 3 is stored in a write address line of the memory 16 to which a write signal is given from the control circuit 5 through the data register 11 when writing is instructed. On the other hand, the data fetched by the trace data generation circuit 4 is supplied with a write signal from the control circuit 5 through the data register 13 and is stored in the line of the write address generated by the control circuit 5.

The operation in the above case will be described in detail with reference to FIG. FIG. 2 is a time chart showing the operation of an embodiment of the apparatus and method for storing a bus trace in a storage device according to the present invention.

The data 1 for the write register input to the address register 6 is stored in the memory 17 at the timing of the bus cycle 3, and the data 2 for the next write address is the memory of the address designated by the address register 7. 16 is stored.

On the other hand, in the trace data, the address n + 1 generated by the control circuit 5 is input to the address register 8 and stored in the memory 15 at the timing of the bus cycle 3, and the next trace data is generated by the control circuit 5. The address n + 1 is input to the address register 9 and stored in the memory 14 at the timing of the bus cycle 4. Since then
The same operation is repeated, and the bus data, memory,
Trace data is stored.

Next, consider the case where reading from the bus is instructed. After the information from the bus 19 is input to the bus management circuit 1, the information is input to the address generation circuit 2 and the trace data generation circuit 4. The address generation circuit 2 generates an address from the input information, and the address is input to the memory 17 through the address register 6.

When an address is input and a read signal is given from the control circuit 5, the output selector 2
Through 0, data is temporarily stored in the register 18 and output from the register 18 to the bus 19 in accordance with an instruction from the control circuit 5. At this time, the trace data is sequentially stored as in the case of writing. The above is the normal operation.

When the user wants to refer to the trace information and is instructed to output the trace data from outside, the control circuit 5 generates a read address and outputs the read address to the address register 8.
A read address and a read signal from the control circuit 5 are supplied to the memory 15 in which the trace data is stored. The data is temporarily stored in the register 18 from the control circuit 5 through the output selector 20. Thereafter, the register 18 set as the shift register scans out the trace data according to the instruction of the control circuit 5.

Similarly, when the next trace data is to be output, a read address of the memory 14 is generated by the control circuit 5, and the read address is input to the memory 14 in which the trace data is stored through the address register 9; When the read signal from 5 is given, the data is temporarily stored in the register 18 through the output selector 20. After that, the register 18 set as the shift register scans out the next data according to an instruction from the control circuit 5.

In the embodiment of the present invention, the memories 16 and 17 are used as memory units for storing bus data,
15 is a memory unit for storing trace data,
The memories 14, 15, 16, 17 can be used as a memory unit for storing bus data. That is, the number of memory units for storing bus data and the number of memory units for storing trace data can be arbitrarily selected.

At this time, there may be a case where the trace data of the bus cannot be stored every cycle with the number of memory units for the trace. In such a case, the output of the trace data generation circuit is combined with the trace data of a plurality of cycles. If output is performed, information on the trace data itself is reduced, but data for each cycle can be stored.

The above-described processing is executed by the computer 21.
Recording medium 22 storing a program to be executed by
Is provided.

[0041]

As described above, the first and second effects of the apparatus and method for storing a bus trace in a storage device according to the present invention are that unnecessary circuits can be reduced during normal operation and a large amount of trace data is obtained. be able to.

The reason is that there is no need to provide a memory for storing special trace data.

The second effect is that trace data at a critical timing can be stored without reducing the operation speed of the bus.

The reason is that the storage device has a memory for tracing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an apparatus and a method for storing a bus trace in a storage device according to the present invention.

FIG. 2 is a time chart showing the operation of an embodiment of the apparatus and method for storing a bus trace in a storage device of the present invention.

FIG. 3 is a block diagram showing a bus trace to a conventional memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Bus management circuit 2 Address generation circuit 3 Data generation circuit 4 Trace data generation circuit 5 Control circuit 6, 7, 8, 9 Address selection holding means, address registers 10, 11, 12, 13 Data selection holding means, data register 14 , 15, 16, 17 storage means, memory 18 output holding means, register 19 bus 20 output selector 21 computer 22 recording medium

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 13/00 301 G06F 11/28 310 G06F 11/30 320 G06F 11/34

Claims (3)

(57) [Claims] 1. A storage device connected to a bus, wherein n
Storage means, address generation means for generating an address from bus information, data generation means for generating data from bus information, and tracing data generation means for generating data for tracing bus information. A trace address generating means for generating an address for storing a data trace result, and an address from the address generating means and an address generated from the trace address generating means corresponding to each of the n storage means. Address selection and holding means for selecting and holding data, and n data selection for selecting and holding data from the data generation means or data from the trace data generation circuit corresponding to each of the n storage means During normal operation, the output of the storage means is selected and traced according to the address of the address generation means during normal operation. Output output means for selecting the output of the storage means according to the address generated from the trace address generation means at the time of output of the data, and also serves as a shift register for temporarily storing the data selected by the output selection means and for outputting the trace data. The output holding means outputs an instruction to store data on the bus in the corresponding storage means at the time of writing in the normal operation and an instruction to store the trace result of the data on the bus in the corresponding storage means. A data output instruction to the storage means to be executed, an instruction to the output selection means to select the output of the storage means concerned, an instruction to store the trace result of the data on the bus in the storage means concerned, and the output holding means. Output an instruction to operate as output holding means to the bus,
At the time of the toasting operation, a trace data output instruction is given to the corresponding storage means, an instruction is given to the selection means to select the output of the storage means, and the output of the selection means is stored in the output holding means. And a control circuit for instructing the output holding means to operate as a shift register when the trace data is output. 2. A storage device connected to a bus, wherein n
Storage processing, address generation processing for generating an address from bus information, data generation processing for generating data from bus information, and tracing data generation processing for generating data for tracing bus information. A trace address generation process for generating an address for storing a data trace result, and an address from the address generation process and an address generated from the trace address generation process corresponding to each of the n storage processes. Address selection and holding processing for selecting and holding data, and n data selection for selecting and holding data from the data generation processing or data from the trace data generation circuit corresponding to each of the n storage processings During the holding process and during normal operation, the output of the storage process is selected and traced according to the address of the address generation process. Output selection processing for selecting the output of the storage processing according to the address generated from the trace address generation processing at the time of output of the data, and temporarily storing the data selected by the output selection processing, and also serving as a shift register at the time of trace data output. An output holding process and an instruction to store the data on the bus in the corresponding storage process when writing in the normal operation and an instruction to store the trace result of the data on the bus in the corresponding storage process are output. A data output instruction for the storage processing to be performed, an instruction to an output selection processing for selecting an output of the storage processing to be performed, an instruction to store the trace result of the data on the bus in the storage processing, and the output holding processing. Output an instruction to operate as output holding processing to the bus,
At the time of the toasting operation, a trace data output instruction is given to the corresponding storage processing, an instruction is given to select the output of the storage processing corresponding to the selection processing, and the output of the selection processing is stored in the output holding processing. And a control process for instructing the computer to operate the output holding process as a shift register when the trace data is output. 3. A storage device connected to a bus, wherein n
Storage processing, address generation processing for generating an address from bus information, data generation processing for generating data from bus information, and tracing data generation processing for generating data for tracing bus information. A trace address generation process for generating an address for storing a data trace result, and an address from the address generation process and an address generated from the trace address generation process corresponding to each of the n storage processes. Address selection and holding processing for selecting and holding data, and n data selection for selecting and holding data from the data generation processing or data from the trace data generation circuit corresponding to each of the n storage processings During the holding process and during normal operation, the output of the storage process is selected and traced according to the address of the address generation process. Output selection processing for selecting the output of the storage processing according to the address generated from the trace address generation processing at the time of output of the data, and temporarily storing the data selected by the output selection processing, and also serving as a shift register at the time of trace data output. An output holding process and an instruction to store the data on the bus in the corresponding storage process when writing in the normal operation and an instruction to store the trace result of the data on the bus in the corresponding storage process are output. A data output instruction for the storage processing to be performed, an instruction to an output selection processing for selecting an output of the storage processing to be performed, an instruction to store the trace result of the data on the bus in the storage processing, and the output holding processing. Output an instruction to operate as output holding processing to the bus,
At the time of the toasting operation, a trace data output instruction is given to the corresponding storage processing, an instruction is given to select the output of the storage processing corresponding to the selection processing, and the output of the selection processing is stored in the output holding processing. And performing a control process for instructing the output holding process to operate as a shift register when the trace data is output.