JPH08327703A - Memory architecture for automatic testing device using vector module table - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a tester having a high speed flexible pattern generator which cab be implemented easily using an easily available memory. SOLUTION: The tester 100 comprises a pattern memory 116 for storing a test vector comprising modules 1,..., N. The sequence for executing the modules 1,..., N is selected from a list stored in the memory. A memory operable in burst mode is employed for implementing the pattern memory 116. In order to compensate for the delay of data rate occurring in the way of burst when the execution is switched between modules, the refresh rate of memory is modified dynamically at the time of switching the modules 1,..., N.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to automatic test equipment, and more particularly to a memory architecture for the pattern generation portion of an automatic test equipment.

[0002]

BACKGROUND OF THE INVENTION Automated test equipment (simply referred to as "testers") is used to test electronic devices and devices during manufacturing. The tester is a device under test (DU
It has a number of signal lines (referred to as "channels") connected to T). A stimulus signal is applied to some of these lines and the DUT's response is measured on the other lines. A failure in the DUT can be detected by comparing the response received from the DUT with the expected response.

State of the art test systems are controlled by a very fast computer running a program called a "pattern". The pattern contains information about the stimulation signals to be applied, the order in which these signals should be applied, and the expected response from the DUT. This information for any cycle of the tester is called a "vector". Therefore, this pattern consists of a series of vectors. VLSI
A typical pattern for a tester designed to test a device can have over a million vectors.

Testers must operate at state-of-the-art speeds for several reasons. First, manufacturers want to make as many products as quickly as possible, so it is desirable that each test be completed as quickly as possible. Second, certain failures in the device will not be detected unless the device is operated at its intended operating speed. To allow the tester to operate at state-of-the-art speeds, the patterns are stored in very fast RAM memory.

The tester uses a large amount of RAM. A typical tester needs to store approximately 4 million vectors. Each vector contains several bits of data for each channel in the tester. Up to 512 bits is a typical number of channels in a tester.
Furthermore, each vector contains several bits of control information. The net result is that testers typically include RAM in the 750 megabyte range. Using only the most advanced RAM for all of this memory would result in a too expensive tester.

Rather, there is a trade-off between speed, cost and flexibility when it comes to RAM selection. Flexibility refers to the range of memory addresses that can be accessed in consecutive memory cycles. Maximum flexibility occurs when any address can be accessed in any cycle. Minimal flexibility occurs when only sequential addresses can be accessed in consecutive cycles. For a given level of flexibility, faster memory costs more. Similarly, for a given speed, the better the memory performance, the higher the cost.

[0007] Typically, flexibility is sacrificed in order to get the proper speed at a reasonable cost.
In the tester, the vectors are executed in exactly the same order that they were written to the pattern memory. Tester users do not like such restrictions. It is sometimes difficult to develop the entire pattern in exactly the same order that it should be executed. Test technicians
We usually prefer to approach the problem of writing patterns by segmenting the DUT into various functional elements and writing patterns to test each functional element. The requirement for sequential execution of vectors in memory precludes the use of control structures such as looping and branching in patterns. Another disadvantage of sequential execution arises because the steps required to test different functional elements or different functional elements often are the same. For example, for DUTs, it is often necessary to perform an iterative initialization sequence so that the whole is tested. If the patterns are only executed in the order they are written to memory, then this initialization sequence must be written to memory each time it is used. Making multiple copies of the same set of vectors wastes space in memory and makes it difficult for a test engineer to change the test pattern because all copies must be changed.

Since the tester is connected to and controlled by a computer workstation, it provides some flexibility. The workstation includes a large-capacity storage medium such as a disk or a magnetic tape that can store a large amount of data at low cost. On the workstation, different patterns may be developed and stored and then loaded into the tester when testing needs to be done.

To facilitate the creation of different patterns, vectors are usually grouped into modules. Each module is a collection of vectors that perform one or more functions. For example, one module may include a vector to initialize the DUT. Another module contains a vector for testing registers inside the DUT, and yet another module is D
It may include a vector for testing arithmetic logic inside the UT. To create the pattern, these modules are linked together on the workstation and loaded into the tester's pattern memory.

The use of modules has the further advantage of allowing complex patterns to be decomposed into parts that are easier to develop and debug. But that doesn't completely solve the problem. The process of loading a new pattern from the workstation includes:
It can take a few minutes. Since testers are used in the manufacturing process to test as many components as quickly as possible, the delays of a few minutes for each component tested add up to unacceptable delays. Using a workstation does not eliminate the memory waste caused by repeating a sequence of vectors in the code.
Also, similarly, no branching, looping or similar non-sequential control arrangements are possible.

A restrictive non-sequential control scheme is
It is incorporated into the tester by allowing only control configurations where the address for the next vector to be executed is limited to one of a very small number of possibilities. One such approach is to allow a given vector from the pattern memory to be executed a certain number of times before the next vector in the sequence is executed. This approach provides a useful feature in that it reduces the number of vectors that must be stored in the pattern memory for some types of patterns. Also, this approach unduly complicates the circuit of the tester because the memory address for the next vector to be executed can take only one of two values: the same as the current address or one address higher. There is nothing to do. This approach does not allow the tester to execute groups of vectors iteratively or in a different order than the order in which they were placed in the pattern memory.

Another approach to provide more flexibility while limiting the number of alternatives for the next address is to provide multiple memories. One of the memories can be programmed to contain a group of repeated vectors in a test pattern, similar to a subroutine in traditional computer programming. While the pattern is being executed, the vectors in the first memory are executed sequentially until the "subroutine" vector reaches a vector that indicates that it should be executed from a different memory. Execution of the vector continues until the vector execution reaches
Switch to the memory of. After that, the vectors in the first memory are executed sequentially. There is no limit to the number of times a vector in subroutine memory can be executed, thereby reducing the need to repeat these vectors at multiple places in the pattern.

Variations on this approach are possible. U.S. Pat. No. 4502 to Garcia
No. 127 describes a variation in that a vector can be created by simultaneously obtaining data from both a large memory and a subroutine memory. Japanese Patent Publication No. 52-144125 describes a variation in which a "subroutine" is realized in a different area of the same memory as the main pattern. All of these approaches reduce the amount of memory required to store the pattern.

The need to provide additional flexibility in the order in which the vectors are executed also comes from the use of multiple memories. In a commercial system,
One memory is very large and inflexible. The second memory is much more flexible and allows branching and looping, but is very small.

Various implementations of this basic approach are possible. US Patent No. 4,451,918 to Gillette
The issue describes a tester with two banks of memory. One bank is a dynamic RAM that stores a large number of vectors. The other bank is a static RAM that stores a smaller number of vectors. The vector is executed from the smaller static RAM. To run large patterns, vectors are loaded into static RAM in blocks. To avoid the delay caused by reloading the static RAM, the bank of static RAM contains two memories, one memory being reloaded while the vector is being executed from the other. But,
This approach states that if a vector needs to be executed in non-sequential order, the next vector to be executed must be contained in the static RAM currently used to execute the vector. Limited in points.

US Pat. No. 4,875,521 to Russo et al.
Tester 0 also contains a large dynamic RAM that must execute vectors in sequential order, and a smaller static RAM that contains vectors that do not execute in sequential order.
The system is described. In this U.S. patent, the test pattern is loaded prior to being loaded into the tester.
The vector is divided into sequential and non-sequential blocks.

The use of different types of memory allows a trade-off between flexibility and cost. Flexible memory is very expensive and must be used sparingly. As a result,
The size of flexible memory is usually limited.
A typical tester has a flexible memory that stores only 1000 vectors. This limited amount of memory is often inadequate.

While many of these techniques have been used simultaneously in commercial testers, there is still a need for a tester that can be implemented using commercially programmable memory that is flexible and relatively inexpensive. ing.

[0019]

SUMMARY OF THE INVENTION With the above background in mind, it is an object of the present invention to allow large modules of vectors to be executed multiple times during a pattern without repeating these vectors within the pattern. It is to provide a tester that operates at high speed.

It is also an object of the present invention to provide a tester that operates at high speed and that allows large vector modules to be repeatedly executed in a loop.

A further object of the present invention is to provide a tester that can be quickly reprogrammed to change the execution order of large vector modules.

It is a further object of the present invention to realize the above object at a cost that can be spent.

The above and other objects are achieved in a tester having a large memory segmented into multiple modules. The tester further includes a memory location that stores the location of each module in a large memory and a memory location that indicates the order in which the memory modules should be executed in the large memory. The execution of the pattern is
This is accomplished by reading the order in which the modules are to be executed from memory and then using the information stored in the memory regarding the location of each module to determine the address in large memory of the next vector to execute.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a tester 10 according to the present invention.
Indicates 0. In operation, tester 100 is connected to some non-test device (DUT) 102. The preferred embodiment described herein is particularly useful for testing VLSI chips. However, the DUT 102 may be a printed circuit board or other electronic device.

The tester 100 is a workstation 10.
Controlled by 4. Workstation 104
It includes a computer, a user interface such as a keyboard and an image display terminal, and a mass storage device such as the disk 106. In use, the pattern is developed on the workstation 104 and loaded into the tester 100 to test the DUT 102.

The tester 100 includes a pattern generator 108. The pattern generator 108 includes a pattern memory 116 which is divided into two parts, a pattern data memory 116B and a pattern control memory 116A. Each vector stored in pattern memory 116 includes data bits and control bits. For ease of implementation, this information is stored in one or more memories.
The size of the pattern memory 116 is not important. However, it is preferably in the range of 16M to 64M vectors.

The data bits are provided to formatter 110. Formatter 110 is a conventional circuit that receives data stored in pattern data memory 116B and applies the appropriate electronic signals to DUT 102. The formatter 110 also receives an electrical signal from the DUT 102 and outputs the electrical signal to pattern data.
The data value stored in the memory 116B is compared. The result of this comparison is the failure processor 11
Provided in 2.

The fault processor 112 comprises the circuits normally found in testers. The fault processor 112 is D
An error is recognized if the expected signal from the UT 102 does not match the measured signal and information about the failure is stored. The failure information is then displayed on the workstation 10
Returned to 4.

The information in pattern control memory 116A is provided to pattern generator control circuit 114. The information in pattern control memory 116A indicates which vector stored in pattern memory 116 should be executed next. The pattern generator control circuit 114 uses this information to calculate the next address for the pattern memory 116. For example, in a tester that can be programmed to repeat a vector a certain number of times, pattern control memory 116A stores information that indicates how many times the vector should be repeated. The pattern generator control circuit 114 repeats the current address a certain number of times before moving on to the next address.

The pattern generator 108 can be controlled from the workstation 104. Workstation 10
4 is a pattern memory 1 on the system bus 120.
Provide information to 16. Also, control information is provided on control line 122. But the computer
It should be appreciated that the buses in the system are used to carry control information as well as data, and control signals may be carried on the system bus 120. The pattern memory 116 takes a long time to load, so
It is intended to be loaded on the system bus 120 before testing is done on the DUT 102. Generally,
After many similar devices have been tested, the pattern
The contents of the memory 116 are changed.

The workstation 104 also provides control information on the control line 122 to the pattern generator control circuit 114. As in traditional testers,
This information initiates the pattern. Once the pattern is started, the execution of the pattern is under the control of the pattern generator control circuit 114 rather than the workstation 104. As described in more detail below, this information may include information such as where in the memory to start or stop the execution of the pattern, which one of the plurality of patterns to execute, and the like.

FIG. 1 does not show details of the tester, such as power supply and timing generation. However, such details are well known in the art and will not be explicitly shown.

Referring now to FIG. 2, the memory architecture of tester 100 is shown. This figure shows the types of information stored in memory. This information may be stored in the same or another memory device. The distribution of the particular information presented to a particular memory device is a design choice and not critical to the invention.

FIG. 2 illustrates a large vector memory or L
A pattern memory 116, also referred to as a VM, is shown. The pattern memory 116 stores multiple modules of vectors. Only three modules are shown in this figure for clarity. However, it should be understood that the actual pattern may include multiple modules.

The size of each module is not critical to the invention. Each module typically has a length of over 500 vectors, and even more than 1000 vectors. For convenience in implementing the control circuit, it is desirable to set lower limits on the size of each module. In the preferred embodiment, each module must have a vector length of at least 256. Preferably, the program running on workstation 104 (FIG. 1) ensures that each module is at least 256 vectors long.

The location of each module in pattern memory 116 is not critical to the invention. conventionally,
A program running on workstation 104 (FIG. 1) positions the module in memory. The particular memory used to implement pattern memory 116 may impose restrictions on the location of modules in pattern memory 116. For the circuits described in more detail below, the memory device that can be used to implement the pattern memory 116 outputs data in blocks of 64 vectors, each block always
Start at an address that is a multiple of 64. Thus, some simplification is obtained if each module starts at a location that has a memory address that is a multiple of 64.

Module position table (MLT) 204
Stores the description of the position of each module in the pattern memory 116. As shown in FIG. 2, the description can be the start address and module length. Other descriptions such as final address and length, start address and end address are also possible. Each location in MLT 204 establishes a pointer to a module in pattern memory 116.

The execution order of the modules is controlled by the information in the vector module table (VMT) 206. Successive locations in VMT 206 list the modules to be executed in the order they should be executed. The information in VMT 206 indicates which module to execute by addressing the location in MLT 204 that gives the location of that module. This information is used by the tester to access the specified module. When the used specified by the first location in VMT 206 is executed, the module specified by the next location in VMT 206 is accessed and executed. VMT
Address control 208 keeps track of which is the next location to execute in VMT 206.

The VMT address control circuit may be as simple as a counter that increments as each module executes and stops when the last module is reached. However, it may also include control logic that allows iterative looping through a group of locations in VMT 206.

The MLT and VMT are also loaded with information provided by the workstation 104. Preferably, a software tool on workstation 104 keeps track of the location in pattern memory 116 where the module is stored and where the module can automatically generate the contents of MLT 204.
The order in which the modules are executed is dictated by the user who prepares the test pattern. Preferably, these software tools also provide VMT2 once the user has specified the order in which the modules should be executed.
Generate information for 06.

A number of advantages result from the memory architecture shown in FIG. It is one of the advantages that the modules in the pattern can be reused in the pattern memory 116 without repetition. VM is required each time the module is executed
There is only one entry in T206. This advantage allows the pattern memory 116 to be smaller, or alternatively allows the tester 100 to execute larger patterns in the same amount of memory. In this way, functions such as calling subroutines, all of which are generally expensive to implement, without the need for separate subroutine memory or control circuitry normally associated with calling and returning subroutines, Can be realized.

This architecture also includes a pattern
It allows changing the order of module execution without reloading the contents of memory 116. VMT2
By changing the contents of 06, the execution order of the modules in the pattern memory 116 is changed. The pattern memory 116 is too large to reload into practice during testing of one device under test, but
6 is much smaller and can be loaded quickly enough not to delay the operation of the test too much. Such performance is particularly useful when it is desired to test the device by performing multiple patterns. All modules required for both patterns are in pattern memory 1
16 and the VMT can be loaded with information about the execution order for the first pattern and then reloaded with the execution order for the second pattern.

The advantages described above primarily occur while the part is being tested. The architecture of Figure 2 also has advantages when test engineers are developing programs. While developing a pattern, the test engineer runs the pattern, observes bugs in the pattern, modifies one or more modules, reloads the pattern,
Then the process is repeated. By not having multiple copies of the same module in a pattern, it is not necessary to make the same changes multiple times. Also, adding vectors to a module is much easier than before. Since the order of execution of modules is determined by the contents of VMT 206, rather than their location in pattern memory 116, when a vector needs to be added to a module, that module is allowed to access a larger block of memory without disturbing other modules. Can be moved to. In addition, a specific module
It can be isolated for execution by simply changing the contents of 06. All of these functions can be performed without reloading the pattern into pattern memory 116. The process of debugging patterns can therefore be greatly speeded up.

Referring now to FIG. 3, the pattern generator 1
08 (FIG. 1) is shown in more detail. Figure 3 shows VM
It shows that T206 (FIG. 2) is implemented as a separate VMT RAM 304. Here, 256K
An 80 nanosecond RAM with a location of is used.
VMT RAM 304 is connected to system bus 120 for loading information. VMT RAM3
The data output line 04 is connected to the address line of the MLT RAM 306.

The MLT 204 (FIG. 2) also includes a separate M
It is implemented as the LT RAM 306. here,
An 80 nanosecond RAM with a size of 64K positions is used. The data output lines of the MLT RAM 306 are divided into two groups. One group carries the data, shown as the starting address of the module in FIG. 2, but with the input as an early LVM address.
It is given to the counter 310. The second group carries data specifying the length of each module in FIG. 2, but provides an input to the module length counter.

Here, the pattern memory 116 is divided into a pattern control memory 116A and a pattern data memory 116B. Pattern memory 116
Two parts of the pipeline (pipelinin
Addressed separately to facilitate g). Pipelines are a well-known technique in high speed digital computer systems. It requires pipeline registers to synchronize data at various locations throughout the system, and synchronized clock signals to control the operation of various parts of the system. The circuitry used to operate the system in a pipelined manner is not explicitly shown in this figure, because it is known in the art and is not critical to the operation of the invention. is there.

Early LVM address counter 310
Is the address that is conventionally used in the tester system.
It is a counter. The data is read from the memory in 64 blocks, as described in detail below. Counter 310 produces an output labeled NEW64, which is connected to memory refresh control circuit 314. This signal, when asserted, indicates that the counter 310 has advanced to an address that requires a new block of 64 bits to be read from memory. This signal is the counter x64
Asserted when crossing the bounds of (increment to address that is a multiple of 64, such as increment 63 to 64 or increment 127 to 128). The NEW64 signal indicates that the new address indicating the start of another module is the counter 31.
Asserted when loaded to 0.

As described below, the memory 116 is
Accessed in banks. The banks are called the even banks and the odd banks. Blocks of data with addresses that start at even multiples of 64 are in even banks (eg, blocks that start at 0, 128, 256, etc.). A block of data having an address that starts with an odd multiple of 64 is in an odd bank (eg, 64, 1,
Blocks starting at 92, 320, etc.). Counter 31
The 0 also causes a signal to be sent to the memory refresh control 314 to indicate whether its current address is in an even memory bank or an odd memory bank.
Preferably, the counter 310 is a semi-custom ASI.
The signal implemented as part of C and applied to the memory refresh control circuit 314 is easily derived from the value in the counter.

The pattern control memory 116A accordingly has a local memory control circuit 312A. As will be described in more detail in connection with FIG. 4, pattern data memory 116B is implemented using memory chips that output values in bursts of 8,8-bit words (64 bits per burst). There is. Local memory control 312A converts these 64 values into 64 sequential values. As described below, pattern memory 116 is implemented with DRAM chips that must be refreshed periodically.

The output of pattern control memory 116A is provided to pattern generator controller 316. The pattern generator controller 316, which is a type of controller typically used in testers, determines the next address for the pattern data memory 116B based on the information in the pattern control memory 116A. For high speed operation, the next address is preferably the next address in vector memory 116 that is the same as the current address in vector memory 116, or an address in secondary memory 322 described below. Or is limited to either. The pattern generator controller 316 outputs the INC signal if the next address is only one more than the current address. The INC signal is not asserted if execution is not to proceed to the next vector in the sequence. As shown in FIG. 3, the INC signal is connected to a counter that advances the address.

It should be appreciated that when moving from execution of one module in LVM 116 to the next, the addresses in memory from which the vector is executed are not necessarily contiguous. However, since the first address in the next module can be calculated from the information previously stored in MLT RAM 306, tester 100
Still runs at high speed. Such a configuration
It is superior to the control structure of programs such as jump statements. In the latter case, the next address cannot be calculated until the current instruction is fetched and decoded.

The pattern data memory 116B is similar to the pattern control memory 116A, with the local memory control circuit 312B also receiving control inputs from the memory refresh control 314. Pattern data memory 116B and pattern control memory 11
The length of 6A and the access speed are preferably the same. However, pattern data memory 116B may include a greater number of bits for each address. The pattern data memory 116B is used by the formatter 11
Required to identify the data provided to 0 (Figure 1),
Contains as many bits as possible per address.

The pattern generator 108 is optionally
A secondary memory 322 is included. Secondary memory 322 may be a subroutine memory known in the art. Here, the pattern control memory 116A also
The next vector to be executed may contain control instructions specifying that it should be executed from a location in secondary memory. If such an instruction is encountered, the pattern generator controller 316 changes the state of the INC line to stop the counter that advances the address to the pattern data memory 116B. Switching execution to secondary memory 322, as is conventional, involves generating consecutive addresses for secondary memory 322. The address generation circuit for secondary memory 322 is not explicitly shown.

Completion of execution of the vector from secondary memory 322 is returned by RETURN opc from secondary memory 322.
It is usually informed by the execution of ode, but at that time,
The INC signal is asserted again, which resumes sequential execution of the vector from pattern data memory 116B. Multiplexer 324 controls whether the pattern data from pattern data memory 116B or secondary memory 322 reaches formatter 110 (FIG. 1). The multiplexer 324 is
It is switched by the control line from the pattern generator controller 316.

During operation, the VMT address counter 30
2 is loaded with the first value from the control circuit 208. The control circuit 208 is connected to the workstation 104 (FIG. 1) on the system bus 120 and receives information from the workstation 104 identifying start and stop locations in the VMT RAM 304. These values are stored in the registers of the control circuit 208. At the beginning of the pattern, the first address is loaded into VMT address counter 302. As the VMT address counter 302 counts, the control circuit 20
8 compares the value in the counter 302 with the last stored address. When the last address is reached, the counter is no longer incremented and the end of the pattern is shown to workstation 104.

Control circuit 208 may optionally include other registers to indicate whether the loop should be repeated over a set range of addresses. In such a case, the control circuit 208 preferably controls the VM of the loop.
First address in TRAM 304 and V of loop
A register indicating the last address in the MT RAM 304 is included. Following execution of the last address of the loop, the first address of the loop is loaded into VMT address counter 302. This loop can be repeated indefinitely. Also, the control circuit 208 may also include a counter that counts the number of times the top address is loaded into the VMT address counter 302 and deactivates the loop when that value in the counter is reached.

As each location in the VMT RAM 304 is addressed, the contents of the addressed location are provided as an address to the MLT RAM 306.
This address stores the starting address of the module in the pattern memory 116 and its length, the MLT.
Access a location in RAM 306. The starting address is loaded into the early LVM address counter 310 and its length is loaded into the module length counter 308.

The module length counter 308 and the early LVM address counter 310 are such that the module length counter 308 counts each time the early LVM address counter 310 advances the address in the pattern memory 116 by one vector. Are clocked together. If the address in the early LVM address counter 310 has reached the end of one module, the module length
The counter 308 counts down to zero and outputs the end of the module EOM signal.

The EOM signal advances the address in the VMT address counter 302 so that the starting address of the next module is in the early LVM address counter 310 and the length of the next module is in the module length counter 308. Be triggered to be offered to. The module length counter 308 in the pattern memory 116 is thus VMT independent of its position in the pattern memory 116.
It is executed in the order specified in the RAM 304.

It should be noted that the memory architecture of FIG. 3 is suitable for use with standard pipeline design techniques. Once the EOM signal is received, the location of the next module to be executed can be calculated from VMT RAM 304 and MLT RAM 306. In this way, when the next EOM signal is received, the starting address of the next module is already available and execution of that module can begin immediately. Since pipelined designs are well known, the hardware and control circuits required to implement them are not explicitly shown.

The pattern memory 116 is preferably D
RAM is the reason for its low cost and wide availability of large capacity DRAM. DRAMs must be refreshed periodically, and during operation, read and refresh cycles are usually interleaved. The memory refresh control 314 controls the pattern control memory 116A and the pattern data memory 116.
It gives control information that allows B to be refreshed as often as not to lose data. However, refresh need not be performed every read operation.
As described below, in order to make the tester operate very fast, the time at which the refresh operation is performed is dynamically changed based on whether there is data that needs to be read. When control switches from one module to another such that the vectors are executed non-sequentially in pattern memory 116, there is a greater demand for data to be read from pattern memory 116. By dynamically changing the refresh time, the data is temporarily read from the memory at a higher speed.

Referring now to FIG. 4, the control circuitry for pattern memory 116 is shown in more detail. The circuit shown in FIG. 4 is a pattern data memory 1
16B or pattern control memory 116A.

The pattern memory 116 is composed of a plurality of memory chips, with one chip stored in the pattern memory 116 for each bit in the vector. These memories are JEDEC SDRA
These memories are called JEDEC.
It indicates that it meets the specifications set by. SDRA
The word M is a dynamic RA where these memories are synchronous.
It is shown that it is M. The synchronous memory produces an output at a time synchronized with a clock (not shown).

To realize a 200 MHz tester, 5
A 66 MHz memory clocked at 0 MHz is preferably used. The JEDEC SDRAM is organized into blocks. Each block contains 8 bytes, each of 8 bits. Therefore, one block has 64 bits. The memory is designed to operate in "burst mode". During one burst, one block
Output from memory at memory output speed. here,
Since the memory operates at 50 MHz, 1 byte is output every 20 nanoseconds and 8 bytes at 160 nanoseconds. In burst mode, the memory is 400 MH
Data is output at the effective speed of z. This is twice the speed at which the data will be used if the tester 100 operates at 200 MHz. Two things happen to prevent the data from being lost because it is being output faster than it is used. First
In addition, in normal operation, every other memory cycle is used to refresh the memory, effectively halving the data rate. Second, the output of the memory is buffered.

The output of each memory chip 402 is provided to buffer 408. The buffer 408 holds data of a plurality of blocks. Each block of data is read from the buffer 4 each time it is read from the memory chip 402.
It is stored in 08. In the preferred embodiment, buffer 408
Holds 4 blocks of data, ie 256 bits in total. These values are stored in the pattern memory 116.
Represents 256 consecutive values of 1 bit in. As shown in FIG. 4, there is one memory chip for each data bit stored in pattern memory 116.

Buffer 408 is addressed by counter 418. Since buffer 408 contains 256 positions, counter 418 has 8 bits. When counting, the counter 418 sequentially addresses the positions in the buffer 408. Counter 418 is incremented as long as the INC line is enabled. As I said, this line
It is enabled as long as the vector is read sequentially from the pattern memory 116.

Which block of 64 bits is the memory 116
Information specifying whether to be read from is provided on the address bus 410. When a 64-bit block is read, the 6 least significant address bits are in memory 1.
16 need not be provided. For a system that can access 64M vectors, there are 20 address lines, but the exact number is not critical to the invention.
These address lines are derived from early LVM address counter 310 (FIG. 3). Each successive block read from memory is stored in successive locations in buffer 408. The buffer 408 "wraps around" so that one block is written at the bottom of this buffer and then the next block is written at the top of the buffer. The circuit that controls this write operation is well known and is not explicitly shown.

Counter 418 has a control input connected to the end of the module EOM signal described in connection with FIG. Thus, at the end of a module, or more importantly at the start of the next module, the counter 41
8 is set to access the starting point of the next block of data stored in buffer 408. In the preferred embodiment, counter 418 has its 6 least significant bits (LS).
The next block is accessed by setting B) to zero and incrementing the higher order bits. For this reason, each module must start at an address with the 6 least significant bits being zero (ie, each module must be loaded into memory at an address that is a multiple of 64). However, it should be understood that the number 64 is derived from the number of bits the memory chip 402 outputs in one burst. The starting address of each module is preferably an integer multiple of the number of bits burst by the memory chip.

The memory chip 402 is preferably a dynamic RAM, which means that it needs to be refreshed. Refresh circuit is JED
It is incorporated in the chip of EC DRAM. In this preferred embodiment, however, this circuit is not used. Having a separate refresh circuit allows the memory to execute patterns faster.

The memory refresh control circuit 314 is
It has two refresh low counters, an even refresh counter 414 and an odd refresh counter. Two counters are JEDEC S
It is used because the DRAM chip has two banks, called bank 0 and bank 1 or even bank and odd bank. The even row counter 414 means that the next address will be refreshed in the even bank. Similarly, odd refresh counter 415
Means that the next address will be refreshed in an odd bank. Since the memory is refreshed in blocks of 64 bits, the refresh counter 41
4, 415 count by 64 (ie, the 6 least significant bits of the address are not provided to memory 116).

The address at refresh counters 414, 415 is provided to the input of multiplexer 412. Address bus 410 is also provided to the input of multiplexer 412. Therefore, multiplexer 4
12 selects an address of data read from the memory and stored in the buffer 408, an address refreshed in an even bank, or an address refreshed in an odd bank. All of these addresses specify the read address because the refresh operation is performed whenever data is read from memory. However, for the refresh operation, the data read from the memory is not stored anywhere. The memory address selection circuit 422 controls not only the buffer 408 but also the multiplexer 412. When the address / source selection circuit 422 selects an address on the address bus 410, it enables the buffer 408 so that the data to be read is stored. However, if the selected address is refreshed,
If it is an address, buffer 408 is deactivated,
Do not store data.

The JEDEC memory chip 402 includes two banks of memory 404 for adding operating speeds. The memory chip 402 will use the data if the low address of the data is established prior to the start of the burst.
It just bursts a row of data. Reads from memory chip 402 alternate between banks 404 in order to keep memory chip 402 operating at the fast burst rate. While one of the banks 404 is burst data, the next row address is bank 4
Established on the other of 04.

JEDEC memory chip 402 contains internal circuitry that allows this switching between banks. This circuit is shown as a multiplexer (mux) 40 in FIG.
Illustrated as 6, selects the input on bank 404 to which the bi-complementary logic signal derived from the row address is applied.

In operation, some mechanism is required to track whether the next operation will access an even bank or an odd bank. Clock generator 424 provides clocks that define even memory cycles and odd memory cycles. In the example used here, each cycle is 160 nanoseconds long. The output of the clock generator 424 is given to the address selection circuit 422. During even cycles, the memory 116 accesses even banks and during odd cycles it accesses odd banks. memory·
The address itself indicates that the data is in even or odd banks, which means that once the address is selected, the output of the clock generator does not need to be routed to other parts of the memory. I want you to understand.

Address select circuit 422 operates to select an address and access the appropriate bank during each even and odd cycle. Address selection circuit 4
22 is preferably implemented as part of a semi-custom ASIC that is programmed to perform the following functions. That is, the NEW64 signal is received from the early LVM address counter 310 and the counter 310
If the bank indication signal from the counter indicates that the address from the counter 310 should be fetched from the bank in the appropriate memory for the current memory cycle, the address on bus 410 is the multiplexer 412.
Selected at, buffer 408 enables to store data. However, if there is no NEW64 signal from counter 310, or if the address from counter 310 is in a bank that is not appropriate for the current memory cycle, then a refresh cycle occurs. During the even memory cycles, the address from the even refresh counter 414 passes through the multiplexer 412. During the odd cycles, the address from odd refresh counter 415 passes through multiplexer 412. Also, whenever a refresh address is provided, the input of buffer 408 is deactivated so that no data is stored.

Consider, in normal operation, a memory access begins on an even cycle with a read from an even memory bank. Counter 310 is intended to increment by 64 every 320 nanoseconds (2
Data rate of 00MHz) is 160 memory cycles
Since it is nanoseconds long, the counter 310 will not generate a new address on the next odd memory cycle.
Therefore, an odd number of refreshes occur. On the next even memory cycle, the counter 310 requests a read from the odd bank, so the even bank is refreshed. The next cycle is an odd cycle, the counter 310 requests a read from an odd bank,
It happens. Counter 3 is a sequential address
As long as it can be determined from 10, this cycle repeats, ie, reads from even banks, refreshes of odd banks, refreshes of even banks, reads of odd banks.

This cycle, however, begins when the module start address is the early LVM address counter 310.
Interrupted when loaded into. In order to ensure that a proper refresh occurs, such a module must be long enough to cause at least one even bank refresh and at least one odd bank refresh. The module has 64 vectors
It may end up after executing only one vector in a block, so it must be refreshed twice and given enough time to fetch one block which gives only one useful vector. This means that at least 3 other 64 vector blocks must be fetched. Therefore, there must be at least 192 vectors in each module. Any number greater than 192 can be selected. In this preferred implementation, 256 was selected.

The same conclusions arise regardless of whether the module starts in an even bank or an odd bank. Each module must have at least 1 to ensure that both banks of memory are refreshed properly.
It must contain 93 vectors. The circuitry that generates the memory cycle clock is not explicitly shown. However, it is well known in the art that digital circuits use timing circuits and conventional design techniques are used here to achieve the required timing circuits. The circuitry for loading data into pattern memory 116 is also not explicitly shown here. Memory chip 402, however, is connected to system bus 120 and data is loaded into memory on this bus.

The preferred embodiment of the present invention has been described above.
Various alternative embodiments may be constructed. VMT
It has been described above that the and MLTs are implemented as separate data structures in separate memories. Information from both of these can be combined into one memory or one data structure. The structured structure is, for example, a pattern
It may be a list of modules including the location of each module in memory.

FIG. 5 shows another configuration of the VMT 206 and the MLT 204. In FIG. 5, two 512
Kx8-bit memories 504 and 506 are used for VMT and ML.
Used to store information in both T and. The address lines of memories 504 and 506 are coupled together so that both memories are addressed together. These have a separate output data line, which effectively outputs 16 bits of data. The memory upper address is used to store information in the VMT. Some arbitrary address in the memory 504, 506,
Defined as the start of MLT. The address stored in the VMT portion of memory represents an offset from this starting address. To get the address from the VMT, the VMT controller 502 reads a location from the memories 504, 506. The VMT controller 502 then
The start address of the MLT is added to this address, and the contents of the memories 504 and 506 at that address are read. Since the information in the MLT is 52 bits long in this preferred embodiment, then three more read operations are performed:
Sequential addresses in the memories 504 and 506 are executed. All information is read and then provided by VMT controller 502 to counters 308, 310. VMT controller 502 may be implemented as a semi-custom ASIC conventionally used in the art and may include the counters, registers, and control logic described above.

As another example, VMT RAM has been described above as containing one list of modules that make up one pattern. It is possible to store multiple lists of modules in VMT RAM so that they can be executed without reloading the memory at all.
In that case, the control circuit 208 will load the VMT address counter with the address of the pattern to be executed. Another way to implement multiple patterns is to have VMT address counter 302 count up or down. The list of modules for one pattern can be stored at the top of VMT RAM 304 and the second pattern can be stored in VMT RAM 304.
Can go up and remember. By counting up from zero,
The first pattern is executed. The second pattern is executed by counting down from zero minus one (1's complement). If the memory address is stored in this manner, the up counter can easily be changed to a down counter by simply inverting the individual output bits.

A further modification is to incorporate the memory offset into the memory architecture. To start the module somewhere other than its first vector,
The offset is the early LVM address counter 31.
It is added to the start position value stored in MLT RAM 306 before it is loaded to zero. The same offset is subtracted from the length of the module before it is loaded into the module length counter 308.

Another modification is that the control circuit 208 has VMT2
It is to include hardware that goes through the list of modules in 06 only multiple times. This number may be a programmed value provided on system bus 120. In this way, the number of times the pattern is repeated is programmable by the user. Also, VMT
206 is incremented to include the iteration count for each module. Thus, the number of times the module is repeated is programmable.

As an example of further modification, it was explained above that the order of execution of modules is given from VMT RAM. Since the new module to execute is selected much slower than the next vector to execute, information about the next module to execute is provided on the system bus 120 rather than read from RAM in the tester. Can be done.

The memory architecture described here can be used with known techniques to provide a fast and flexible tester. Secondary memory 322 may be a small SRAM such as is conventionally used in testers for subroutine memory. Further, US Pat. No. 5,270,520 to Brown et al. For a fast timing generator.
Techniques such as those described in US Pat. No. 582, which is incorporated herein by reference, may be used with this technique to further speed up the tester.

Many features of the preferred embodiment are not critical to the invention. For example, opcode LVM116
Although A is shown as a data structure separate from the data LVM 116B, this difference is not material to the invention. Both data and control information can be stored in one memory or distributed in multiple memories.

The invention is therefore defined solely by the spirit and scope of the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram of a tester system according to the present invention.

FIG. 2 is a conceptual sketch of the memory architecture of the present invention.

3 is a block diagram showing the pattern generator of the tester of FIG. 1 in more detail.

FIG. 4 is a block diagram showing the memory and memory control circuit of the pattern generator of FIG. 3 in more detail.

FIG. 5 is a block diagram of another configuration of the vector module table of the present invention.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Benjamin Jay Brown, California, USA 91361, Westlake Village, Brighton Stone Court 945

Claims (21)

[Claims] 1. A tester system comprising: a) a first memory means having a plurality of address lines for storing a test pattern; and b) a second memory means having a data output and a plurality of address lines. C) an address counter connected to receive data from the data output of the second memory means and an output of the first memory means coupled to the address line; and d) an output. A second counter having an input connected to receive data from the data output of the second memory means, and e) accessing at least one location in the second memory means, At least one of the address counter and the second counter in the second memory means in response to the second counter reaching a predetermined value.
A tester system comprising: control means for loading data stored in one position; 2. The tester system according to claim 1, further comprising means for providing address information representing the position in the second memory means accessed by the control means to the control means at consecutive intervals. A tester system characterized by 3. The tester system of claim 2, wherein said means for providing address information at consecutive intervals is an ordered list of address information stored in a memory which is sequentially accessed by said control means. A tester system characterized by being equipped with. 4. The tester system according to claim 3, wherein the control means includes a loop start point index indicating an entry in the ordered list representing a start point of a loop, and a loop start index indicating an end point of the loop in the ordered list. Memory means for storing a loop endpoint index indicating an entry, and sequentially accessing the ordered list of address information until the end of the loop is reached,
And a means for sequentially accessing the entries in the ordered list from the loop start index thereafter.
system. 5. The tester system of claim 2, wherein said means for providing address information at consecutive intervals provides address information in response to said second counter reaching a predetermined value. A tester system characterized by 6. A high speed digital device for executing instructions stored in a memory, comprising: a) storing a plurality of instructions, having a first bank and a second bank, in response to a read command; A dynamic memory outputting a block; and b) an address counter having an address output and a status output, the address counter having a value indicating the start of a block of data in the memory. And an address counter indicating whether the block is in the first bank or the second bank of the memory, c) a first refresh address counter having an address output, and d) A second refresh address counter having an address output, and e) that the first bank of the memory is accessed. Means for generating a memory cycle signal that alternates between a first state indicating that the second bank of memory is accessed and a second state indicating that the second bank of memory is accessed; Address output and first
And an address selection providing a selected address to the memory at each memory cycle in response to a second refresh address counter, the means for generating a memory cycle signal, and the status output of the address counter. The selected address is i) indicating that the status output of the address counter has a value indicating that the address counter indicates the start of a block, and when accessed, the memory cycle signal is If the block of data is in the indicated bank,
The address output of the address counter, ii) the memory cycle signal indicating that the first bank is being accessed, and the address counter taking a value indicating the start of a block The address output of the first refresh counter if the state output of the address counter is not shown and the block of data is in a bank indicated by the memory cycle signal to be accessed; Iii) The status output of the address counter does not indicate that the memory cycle signal indicates that the second bank is being accessed and that the address counter has a value indicating the start of a block. , If the block of data is in the bank indicated by the memory cycle signal to be accessed Is the address output of the first refresh counter. 7. The apparatus of claim 6, further comprising a buffer having an enable input coupled to said address selection means and receiving at least one block of data coupled to said memory, said address The selecting means enables the buffer when the address counter is the selected address, and when the address output of the first or second refresh counter is the selected address. An apparatus, further comprising means for disabling the output buffer. 8. The apparatus according to claim 7, wherein the apparatus is a tester having a module of vectors loaded in the memory, further comprising selection means for selecting a non-sequential execution order of the modules, The selecting means includes means for loading the starting address of the module of the vector into the address counter, and the status output of the address counter is of data if the starting address of the module is loaded into the address counter. A device characterized by indicating the start of a block. 9. The apparatus according to claim 8, wherein the dynamic memory comprises more than 1 gigabyte of dynamic memory. 10. The device of claim 9, wherein the dynamic memory is a plurality of JEDEC SDRAMs.
A device having a chip. 11. The apparatus of claim 10, wherein each memory chip is clocked to provide a maximum burst data rate and the tester is at a predetermined maximum rate equal to half the maximum burst rate. An apparatus characterized by executing a vector. 12. The apparatus according to claim 11, wherein each memory chip is clocked to output one byte of data at a rate of at least 50 MHz. 13. A method of operating a tester, comprising the steps of: a) loading a plurality of pattern modules into memory; and b) an ordered list of pattern modules to be executed and the location of each pattern module in memory. C) i) generating an original address using the stored position of the first pattern module in the ordered list, and ii) at the end of the first pattern module. Advancing the address until it is reached, and iii) repeating steps i) and ii) for successive pattern modules in the ordered list, thereby generating the address in the memory. How to characterize. 14. The method of claim 13, wherein the step of storing the ordered list and the position of the pattern module stores the ordered list of modules and the position of each module separately in memory. A method comprising: 15. The method of claim 14, wherein the step of storing an ordered list of pattern modules comprises pattern modules in which at least one pattern module appears at a plurality of positions in the ordered list. Storing an ordered list of. 16. The method of claim 14, wherein the step of storing the location of each module stores a single record for each module in a second memory including the start address and the length of the module. And storing the ordered list comprises storing the address in the second module of a record. 17. The method of claim 16, further comprising the step of storing a different ordered list of modules after the step of generating an address in the memory. 18. The method of claim 17, wherein the step of storing a different ordered list of modules stores the different ordered list without changing a portion of the plurality of modules stored in memory. A method comprising storing. 19. The method of claim 13, wherein the step of generating an address in memory comprises: a) detecting when a given pattern module in the ordered list has been executed; and b). A pattern in the ordered list starting at a second predetermined position in the ordered list,
Repeating the execution of the module, and. 20. The method of claim 19, wherein the step of repeating the execution of the pattern module comprises repeating the execution of the predetermined pattern module a predetermined number of times. 21. A method of operating a tester, comprising: a) a plurality of pattern modules in a dynamic RAM.
Loading non-sequential locations in memory, each pattern module comprising a plurality of vectors stored in said memory in sequential order; and b) said sequential order. Retrieving a vector from one of the modules and executing the retrieved vector at execution speed; c) retrieving the vector in sequential order,
Refreshing the dynamic RAM memory at a first refresh rate; d) retrieving a vector from a second pattern module and executing the retrieved vector at the execution rate;
Thereby causing the vector to be continuously executed at the execution speed during the transition from the first module to the second module, and e) the dynamic RAM memory to store the vector in the second Initially searching from the second pattern module,
Refreshing at a second refresh rate that is slower than the first refresh rate; and f) refreshing the dynamic RAM memory at the second refresh rate, and then refreshing the dynamic RAM memory at the first rate. A step of refreshing, the method comprising: