JP3078594B2 - Image storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage device capable of simultaneously writing and reading image data to and from a storage element.

[0002]

2. Description of the Related Art For example, an image memory having one data input / output port is used as an image memory for storing image data such as medical images. However, the conventional image memory used in this case is a method of writing image data.
Since only one data input / output port for inputting / outputting data for performing reading (reading) is provided, two images, for example, a first image (referred to as # 1) are written and simultaneously a second image is written. It is impossible to read out the image (referred to as # 2). For this reason, by using two image memories, one of the problems can be solved by dedicating one for writing and the other for reading, but the hardware scale cannot be avoided.

[0003] Therefore, combining two image memories, 1
By using one unit, an increase in hardware scale can be avoided. However, at present, such a large-capacity memory can be easily realized, so that it is easy to simultaneously write two images in the memory element. Therefore, it is still impossible to perform simultaneous write and read operations as described above simply by combining a plurality of image memories into a unit. Especially recently #
There is a demand for an access technique in which the images 1 and # 2 are simultaneously read, and the added image (third image, # 3) is written on the fly while performing an operation of adding the two (an operation between images). However, it cannot be realized by the conventional address system for sequentially accessing images.

In order to avoid the above drawbacks, for example, one pixel of the # 1 image is first read out using the control operation of a CPU (Central Processing Unit), and then one pixel of the # 2 image is read out. A method is provided in which simultaneous writing and reading operations are carried out by using one data input / output port by means of time shredding, for example, by reading out one pixel of the # 3 image that has been operated on, and then writing one pixel of the calculated # 3 image. However, in the time sure system using one data input / output port as described above, in the case of the above example, (reading of the image of # 1) + (reading of the image of # 2) + (writing of the image of # 3) As described above, three cycles are required, so that one operation cycle increases and the processing becomes complicated.

[0005]

As described above, in any of the conventional image memories, there is a problem that simultaneous operation of writing and reading of image data cannot be performed simultaneously without requiring complicated processing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an image storage device capable of performing simultaneous operations of writing and reading of image data without requiring complicated processing. It is the purpose. [Configuration of the Invention]

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an image storage device which enables simultaneous writing and reading of image data to and from a storage element. A plurality of data input / output ports, a plurality of shift registers provided at each data input / output port, each of which can control the number of shift stages so that the phases of each data are aligned, and control of a write or read cycle of a storage element A timing controller for generating a cycle selection signal for performing a write operation, a read / write controller for transmitting a signal for switching a write or read timing to a storage element, and a cycle selection signal for inputting a plurality of image data addresses to be input / output to a plurality of data input / output ports. And an address controller for sending a switching signal to the storage element based on the It is an butterfly.

[0008]

After arbitrarily designating image data to be written to or read from a storage element via a plurality of data input / output ports, writing or reading from or to the storage element is performed based on a cycle selection signal output from a timing controller. The cycle is controlled by switching the address of the image data. In this case, the address is switched and sent to the storage element based on the combination of the designated image number and the pixel address of the image data corresponding to the designated image number. When reading image data from the storage element, each shift register is shifted so that the phases of the data are aligned, and the phases of the read image data are aligned.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image storage device according to the present invention. Reference numeral 1 denotes a memory element, which has a plurality of data input / output ports 2 (2 _{1 to} 2 _M ) for inputting / outputting image data. Is provided.

[0011] Data register 3 (3 ₁ to 3 for inputting each image data to the data input and output ports 2 ₁ 2 _M
M ), a shift register 4 (4 _{1 to} 4 _M ) in which the number of shift stages can be controlled by a timing controller described later so that the phases of the data are aligned, and a data transceiver 5 ( 5 _{1 to} 5
_M ).

[0012] Image data input and output respectively to each data input port 2 ₁ to 2 _M is arbitrarily designated. Wherein each input and output port 2 ₁ to 2 _M [1] to [M]
Indicates a port number. For example, the data input and output ports 2 ₁ indicates the port number of [1], the data input-output port 2 ₂ indicates the port number of [2], the data input-output port 2 _M indicates the port number of the [M] Shall be. # 1 is the first image number (image data),
# 2 indicates the second image number, and #M indicates the Mth image number. Here, the first image number # 1 is specified for the port number [1], the second image number # 2 is specified for the port number [2], and the M-th port number is specified for the port number [M]. The image number #M is designated as an example. However, the combination of the port number and the image number can be arbitrarily specified. Memory device 1 includes input and output of image data is performed between the arithmetic circuit via a respective data input and output ports 2 ₁ to 2 _M, it is enabled write and read any image data.

A timing controller 7 generates a cycle selection signal for controlling a write or read cycle of the memory element 1 and sends it to a read / write controller and an address controller, which will be described later. The timing controller 7 generates a clock for controlling the operation of the data input / output ports 2 _{1 to} 2 _M , and
₁ to 3 _M, and sends each of the shift registers 4 ₁ to 4 _M and the data transceiver 5 ₁ to 5 _M. Reference numeral 8 denotes a read / write controller which sends a signal for switching write / read timing to the memory element 1 based on the cycle selection signal.

[0014] 9 is the address controller sends the address of a plurality of image data to be input to the data input and output ports 2 ₁ to 2 _M, a signal for switching on the basis of the cycle selection signal to the memory element 1. The address controller 9 outputs a single address by combining pixel address of the image data corresponding to the image number and the image number assigned to each data input port 2 ₁ to 2 _M, a plurality of address input register 10 (10 ₁
To 10 _M ) and each address input register 10 _{1 to} 1 _M
And it is configured to 0 _M output from the address multiplexer 11 for outputting switching based on the cycle selection signal.

That is, in this embodiment, the memory element 1
The address of the image data to be written or read into the memory is treated as if it were a single address obtained by packing the image number and the pixel address of the image data. For example, if the address of the image number is set to 2 bits and the pixel address is set to 10 bits, it is recognized as a 12-bit address, and nothing else is required. Next, the operation of the present embodiment will be described.

In order to facilitate understanding of the description, an example in which M = 3 in the configuration of FIG. 1 will be described. Therefore, three data input / output ports [1], [2] and [3] are provided. Also, an example will be described in which image data is read from the first and second image numbers # 1 and # 2, and the calculation result of these two images is written into a third image number # 3. Further, it is assumed that the image numbers of [1] and [2] are designated as # 1 and # 2, respectively, and the image number of [3] is designated as # 3. The correspondence between the port numbers and the image numbers is an example, and any combination is possible. For example, by specifying # 3 in [1], for writing, [2],
It is also possible to designate # 1 and # 2 in [3] for reading.

As shown in FIG. 2, the image memory 6 of the present embodiment
Is connected to each of the input / output ports 2 ₁ , 2 ₂ , 2 ₃ , and a host circuit 14.
Is connected. The host circuit 14 sends a read (read) control signal to [1] and [2] and a shift (write) control signal to [3] based on the setting example. At the same time, based on the setting example, the image numbers of [1] and [2] are designated as # 1 and # 2, and the image number of [3] is designated as # 3.

Each pixel address is generated as shown in FIG. 3 and is input to each of the address input registers 10 ₁ , 10 ₂ and 10 ₃ . Compared to the addresses [1] and [2],
The address of [3] is set late, because the operation delay in the operation circuit 13 is reflected.

As shown in FIG. 4, the timing controller 7 sets a time t ₀ longer than the access time of the memory element 1.
Generates a cycle selection signal. For example, if the access time of the memory element 1 is 100 ns, t ₀ is 1
00 ns or more. This cycle selection signal is sent to the address multiplexer 11 of the address controller 9, and a signal for sequentially switching the address of each image data is sent to the memory element 1. Read / write
At the same time, the controller 8 sends a read control signal to the memory element 1 during the cycles [1] and [2], and sends a write control signal during the cycle [3]. FIG.
FIG. 3 is a time chart showing how the read and write operations of the memory element 1 are performed based on the cycle selection signal as described above.

In FIG. 5, when a cycle selection signal is generated, the address controller 9 is controlled based on the signal to switch the address. The memory element 1 first reads image data in the cycles [1] and [2], and then writes image data in the cycle [3]. That is, the pixel address (shown in FIG. 3) and the image number of each of [1] to [3] selected by the cycle selection signal are
By sequentially switching and supplying the memory element 1, the memory element 1 performs an operation of reading or writing image data after a certain access time.

When the memory element 1 performs a read operation, the read image data is transferred to the data transceiver 5 in the configuration of FIG.
To the shift register 4. At this time, transceivers other than the port selected by the cycle selection signal
The control is performed so that the memory element 1 does not collide with the image data, and the image data is fetched by a clock generated based on the cycle selection signal. The shift register 4 is controlled so as to take in image data with a clock and to perform a shift operation for the number of shift stages at the same time.

For example, in FIG. 5, when reading image data from the ports [1] and [2], the shift register 5
Immediately before ([1] Transceiver 5 ₁ data output and [2] transceiver 5 ₂ of the data output of) the t ₀ only image data of phase between [1] and [2]. This occurs because the read operation of the memory element 1 is temporally shifted by t ₀ between [1] and [2].
₀ of the shift stages of "1" stage in the shift register 4 ₁ corresponding to [1] in order to correct the deviation, providing a number of shift stages of the shift register 4 to ₂ "0" stage corresponding to [2] Control. As a result, the phases of the image data output from the ports [1] and [2] can be aligned as shown at the bottom of FIG.

Next, in the write operation, the image data sent from the external arithmetic circuit 13 by the capture clock of the transceiver 5 and inputted through the data register 3 and the shift register 4 is taken into the memory element 1. However, in this case, the data register 3 and the shift register 4 are [1],
Although image data flows in the direction opposite to [2], the shift register 4 does not perform another shift operation as in the case of reading.

Memory element 1 captured by transceiver 5
As shown in FIG. 5, the image data to be written to the memory device 1 is first taken into the register in the transceiver 5, and then the image data is stored in the memory element 1 only when [3] is selected based on the cycle selection signal. The data is transmitted so that the image data does not collide with another transceiver.

As described above, according to this embodiment, the address, read and write control signals for the memory element are sequentially supplied to the data input / output port selected based on the cycle select signal to read and write image data. The first image is read from the first port since the operation is performed and the number of shift stages of each shift register is controlled so that the phase of the image data between the input / output ports is aligned particularly at the time of reading. At the same time, the second image can be read from the second port, and at the same time, the image data after the operation can be written to the third port, and can be realized without complicated processing. can do.

In this embodiment, an example in which three data input / output ports are set has been described. However, these are only examples, and four or more data input / output ports may be set. In addition, although the input of the image number, the input of the pixel address, and the input of the read and write commands and the like are shown from the outside, the present invention is not limited to these.

Further, it is possible to operate the memory element in a multi-interleave operation, and it is possible to input / output image data to / from the same or earlier than the cycle selection signal with the same configuration as in this embodiment. Further, according to the present invention, it is possible to reduce the size of the hardware and improve the ease of controlling the image number of the memory element.

[0028]

As described above, according to the present invention, a plurality of data input / output ports are provided to control image data to be input / output to / from each port in response to a cycle selection signal to perform a write / read operation to / from a memory element. Since this operation is performed, simultaneous operation of writing and reading of image data can be performed without requiring complicated processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image storage device of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration for performing writing and reading operations of image data using the apparatus according to the embodiment.

FIG. 3 is a timing chart illustrating an example of generation of an image address in the apparatus according to the embodiment.

FIG. 4 is an explanatory diagram of an example of generation of a cycle selection signal in the device of the present embodiment.

FIG. 5 is a timing chart for explaining the operation of the present embodiment.

[Explanation of symbols]

Reference Signs List 1 memory element 2 (2 _{1 to} 2 _M ) data input / output port 4 (4 _{1 to} 4 _M ) shift register 7 timing controller 8 read / write controller 9 address controller 11 address multiplexer 13 arithmetic circuit 14 host circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 17/16 G06T 1/60 G11C 11 / 34,11 / 401

Claims (2)

(57) [Claims] 1. An image storage device which enables simultaneous writing and reading of image data to and from a storage element.
A plurality of data input / output ports for inputting / outputting image data to / from the storage element, and a plurality of shift registers provided at each data input / output port and each of which can control the number of shift stages so as to align the phase of each data, A timing controller for generating a cycle selection signal for controlling a write or read cycle of the storage element, a read / write controller for sending a signal for switching the write or read timing to the storage element, and a plurality of input / output ports for a plurality of data input / output ports And an address controller for sending a signal for switching the address of the image data based on the cycle selection signal to the storage element. 2. The address controller arbitrarily designates an image number for each data input / output port, and combines the designated image number and a pixel address of image data corresponding to the image number as an address. 2. The image storage device according to claim 1, wherein each of these addresses is switched.