JP2761559B2 - Data generator for semiconductor memory test - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test data generator that generates write data for testing a semiconductor memory and expected value data at the time of reading by calculation.

[Prior Art] As shown in FIG. 4, in a conventional semiconductor memory test data generator, a count value of a program counter 11 for controlling a program execution sequence according to a program description is given to an operation instruction storage unit 12 as an address. The operation instruction is read out, and the data generator 13 is read in accordance with the operation instruction.
Are the data in the buffer register 14 as +1 and −
An operation such as 1 is performed to output data. This data is supplied to the semiconductor memory under test as write data at the time of writing or as expected value data at the time of reading.

[Problems to be Solved by the Invention] In recent years, with the diversification of semiconductor memories, ASM (Application Specific Memory) ICs having various operation modes have appeared. This ASM IC has, for example, a built-in RAM and a SAM. When data is input to the RAM, a mode in which data is transferred from the RAM to the SAM, and a mode in which output data and input data are calculated and the calculation result is stored are designated. There are various operation modes, such as a mode for writing only the set bits, and an operation mode is set according to the operation mode data input from the outside, and the operation is performed in the operation mode.

The operation mode data for setting the operation mode is data unique to the operation mode, and the operation mode data is randomly input to the ASM IC. Such an ASM IC
In the test, it is necessary to generate not only the address, the write data, and the expected value data but also generate the operation mode data and supply it to the ASM IC. However, in the conventional data generator shown in FIG. 4, since data is generated by a regular operation such as +1 or -1, operation mode data cannot be easily generated.

According to the present invention, operation mode data for setting an operation mode of a memory under test is stored in an operation mode data storage file, and an operation mode is stored in an operation instruction storage unit for each instruction. An operation mode data selection signal storage unit storing a selection signal for selectively outputting operation mode data in the data storage file, and a selector control data storage unit storing selector control data for each instruction are provided. Therefore, one operation instruction is read out from the operation instruction storage unit, the operation mode data selection signal and the selector control data are read out, and the read selector control data is used to generate data according to the read out operation instruction. Either the data calculated by the device or the operation mode data selected from the operation mode data storage file by the read operation mode data selection signal is selected by the data selector and output to the memory under test.

[Operation] With this configuration, based on the operation instruction read from the operation instruction storage unit by the program counter, the data generator sequentially generates write data or expected value data by the operation and receives the data. The operation mode data selection signal is read in the middle of the sequentially generated data while being supplied to the test memory, whereby the operation mode data is selected from the operation mode data storage file and supplied to the memory under test. Therefore, while the memory is tested by outputting the write data or the expected value data generated by the operation, the operation mode of the memory can be changed in the middle of the test to continuously perform the test.

"Embodiment" FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. In the present invention, each operation mode data for setting each operation mode of the memory under test is stored in the operation mode data storage file 21. An operation mode data selection signal storage unit 22 in which a selection signal for selecting and outputting operation mode data in an operation mode data storage file 21 for each instruction is stored in the operation instruction storage unit 12; And a selector control data storage unit 23 for storing selector control data. For example, the operation mode data storage file 21 is a semiconductor memory, in which one operation mode data is stored for one address, and the operation mode data selection signal indicates one address of the memory as the file 21. An operation instruction storage unit 12 and an operation mode data selection signal storage unit 22 for each count value of the address counter 11
And the selector control data storage unit 23 are read.

The read operation instruction is supplied to the data generator 13, the read selection signal is supplied as an address to the operation mode data storage file 21, the file 21 is read, and the read selector control data is read. It is supplied to the select signal generator 24. The data generator 13 operates in the buffer register in accordance with the input
Perform calculations such as +1 and -1 with the 14 data as initial values,
The calculation result is supplied to the data selector 25 as one input. The operation mode data read from the operation mode data storage file 21 is supplied to the data selector 25 as the other input. The select signal generator 24 generates a select signal according to the input selector control data and supplies the select signal to the data selector 25 as a control signal. The data selector 25 outputs the output data of the data generator 13 when the input select signal is “0”, and outputs the output operation mode data of the operation mode data storage file 21 when the select signal is “1”. .

When the program counter 11 advances by one, the operation instruction storage unit 12, the operation mode data selection signal storage unit 22, and the selector control data storage unit 23 are read out using the count value as an address, and the read operation instruction is read out. The data is generated from the data generator 13 in accordance with the operation mode data selection signal read from the operation mode data storage file.
The operation mode data is read out from the selector 21, and the selector control data read out causes the select signal generator 24 to output, for example, "1" at the beginning of one test cycle as shown in FIG. Is output.
While this select signal is “1”, the data selector 25
The output operation mode data of the operation mode data storage file 21 is output. At this time, the operation mode data is set in the memory under test at the falling of the control signal ▲ ▼, and while the select signal is “0”, The output data of the data generator 13 is output from the data selector 25. At this time, the data generator
Thirteen output data are written.

Note that the data selector is used in units of one test cycle.
25 selection controls may be performed. In this case, the selector control data is one bit, and may be directly supplied to the data selector 25 as a select signal. In this case, the operation instruction is not stored at the address where the selector control data is “1”, and only the operation mode data selection signal is stored. At the address where the selector control data is “0”, only the operation instruction is stored. And the operation mode data selection signal is not stored. Operation mode data storage file 21
May be used as a register. For example it is stored respectively operating mode data in the register 21 ₁ through 21 _n, as shown in FIG. 3, these operating mode data may be selectively output in accordance with the operation mode data selection signal by the multiplexer 26 . The output operation result data of the data generator 13 is stored in the operation mode data storage file 21, and the operation mode data storage file
The operation result data in 21 can also be read and output.

[Effect of the Invention] As described above, according to the present invention, the operation instruction storage unit 12
Provided with an operation mode data selection signal storage unit 22 and a selector control data storage unit 23, read by the address counter 11, and select operation mode data from the operation mode data storage file 21 by the read operation mode data selection signal; To output either the output data of the data generator 13 or the selected operation mode data based on the read selector control data, test the ASM IC in real time while changing the operation mode setting Test data, that is, write data and expected value data can be sequentially generated, and operation mode data can be inserted and generated in the middle thereof.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an operation example thereof, FIG. 3 is a block diagram showing another example of the operation mode data storage file 21, and FIG.
FIG. 1 is a block diagram showing a conventional semiconductor memory test data generator.

Claims (1)

(57) [Claims] An operation instruction is read from an operation instruction storage unit by addressing by a program counter, an operation corresponding to the read operation instruction is performed by a data generator, and data of the operation result is received. In a semiconductor memory test data generator for supplying write data or expected value data to a test memory, an operation mode data storage file storing operation mode data for setting an operation mode of the memory under test is stored in the operation instruction storage unit. An operation mode data selection signal storage section provided for each of the instructions and storing a selection signal for selectively outputting operation mode data in the operation mode data storage file; and a selector control provided for each of the instructions. A selector control data storage unit for storing data; and a selector control data storage for the operation instruction storage unit. Data to select and output to the memory under test any one of the operation data output from the data generator and the operation mode data selected from the operation mode data storage file according to the selector control data read from the section A data generator for testing a semiconductor memory, comprising: a selector;