JP3001545B1 - Vector data processing device - Google Patents

Abstract

In a vector data control device, when a vector data transfer instruction between vector registers is executed,
Generation of mask information of vector data after transfer and storage in a mask register are performed at high speed. SOLUTION: When a data transfer instruction between a vector register 10 and a vector register 20 is issued from an instruction control unit 70, the data is sequentially read from a VCR 61 in a mask register unit 60 in accordance with data transfer, and is transferred to a vector register of a transfer destination. In parallel with the data transfer processing, a mask bit used to control the writing of data to the mask register 20 is used as mask information of the vector data after transfer.
Writing to the VCR 61 or VMR 62 within 0 is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing apparatus, and more particularly, to a vector data transfer instruction between vector registers, which can generate mask information of vector data after transfer at high speed and store the mask information in a mask register. The present invention relates to a vector data processing device.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional example of a vector data processing device. For simplicity of explanation, one vector processing unit R and two vector registers for storing vector data are used. The calculation unit is omitted here.

The vector register 10 is assigned a different vector register number as a vector register number 0 (V0), and the vector register 20 is assigned a different vector register number as a vector register number 1 (V1).
(N is a natural number) elements can be stored. The read / write addresses are set in the read address registers 11 and 21 and the write address registers 12 and 22 by the vector register control unit 40, and each has a count + 1 function.

When the address indicates the maximum address by counting up, the process returns to address 0 and continues counting up. When receiving the mask generation instruction from the instruction control unit 70, the mask generation unit 80
The mask information corresponding to each element of the vector data stored in 20 is generated. These pieces of mask information are stored in an area assigned to each vector data in the mask register section 60 by a mask write command.

When performing vector processing, the mask register section 60 stores a mask register (VCR) for storing mask information of vector data to be processed, and a plurality of save areas used for saving the mask register. (V
MR). When vector processing is performed, the mask information of the vector data to be processed is once V
Used after being set to CR.

Here, a vector data transfer instruction from the vector register V0 to the vector register V1 (V0 → V
When 1) is issued, the instruction code, the transfer source vector register number, the transfer destination vector register number, the transfer start address, and the instruction code are transmitted from the instruction control unit 70 to the mask register control unit 30 and the vector register control unit 40 as instruction control information.
Information such as vector length is passed.

When the mask information of the vector data to be transferred of the transfer source vector register is set in the VCR in the mask register unit 60, the mask register control unit 30 sequentially shifts one bit from the mask bit corresponding to the element indicated by the transfer start address. It is read out in units and sent to the vector register control unit 40.

The vector register control unit 40 sets the transfer start address in the read address register 11 of the transfer source vector register V0 and sets the write start address in the write address register 22 of the transfer destination vector register V1. In the transfer instruction, 0 is usually designated as the write start address.

The address register has a count + 1 function, and counts up from the set transfer start address. Along with this, the vector data for the element specified by the vector length is sequentially read from the vector register V0, and sent to the transfer destination vector register V1 via the vector data selection unit 90.

Here, the writing of vector data to the vector register V1 is performed sequentially from the address set in the write address register 22 in accordance with the count-up, but from the VCR in the mask register section 60 to the vector register control section 40. With reference to the read mask information, only the vector data of the element whose mask bit is "1" is written, and the vector data of the element whose mask bit is "0" is not written. By performing this processing for the elements specified by the vector length, the data transfer processing is completed.

When the transfer of the vector data is completed, a mask generation instruction is issued to rewrite the mask information of the vector data after the transfer. When the mask generation instruction is issued, the mask generation unit 80 of the scalar processing unit Q generates the mask information of the vector data after the transfer, and the subsequent mask information write instruction issues a predetermined VCR or VMR in the mask register unit 60. Writing of mask information is performed in the area.

[0012]

In the above-described conventional vector data processing apparatus, when a vector data transfer instruction between vector registers is executed, after the vector data transfer processing is completed, the mask information of the transferred vector data is obtained. In order to generate the mask, a mask generation instruction and a mask write instruction are issued, and the mask generation is performed by the scalar processing unit Q.
It took a long time before it was written to the mask register.

In addition, when the subsequent instruction is an instruction that uses the result of the above processing, the issue of the instruction is waited, and the performance of vector processing is reduced.

The object of the present invention has been made under such a background. In a vector data transfer instruction between vector registers, generation of mask information of vector data after transfer and writing to the mask register are performed by vector control. It is an object of the present invention to provide a vector data processing device that performs high-speed processing in parallel with data transfer processing.

[0015]

According to the first aspect of the present invention,
In the vector data processing device, a plurality of vector registers for holding vector data, a plurality of mask registers for storing mask information indicating validity / invalidity of each element of the vector data held in the vector register, and A plurality of operation units for processing the read vector data , wherein the vector register
When performing a vector data transfer instruction between
For each element of the vector data of the transfer source from the register
The vector data is read out and stored in the destination vector register.
Transfers mask bits used for data write control
Vector data as mask information of subsequent vector data
And writing to the mask register in parallel with the transfer processing .

[0016]

According to the present invention, there are provided a plurality of vector registers for holding vector data, a mask register for storing mask information indicating validity / invalidity of each element of the vector data held in the vector register, and a vector read from the vector register. In a vector data processing device including a plurality of arithmetic units for processing data, when a vector data transfer instruction is issued between the vector registers,
The transfer instruction valid flag indicating the validity of the transfer instruction, and read from the mask register control unit to the vector register control unit corresponding to each element of the transfer vector data, and are used for controlling the writing of data to the transfer destination vector register. A mask bit from the mask generation unit, and a mask instruction from the mask generation unit. And a selector for transmitting the mask information to the selector.

According to the present invention, in a vector data processing apparatus, when a vector data transfer instruction is issued between vector registers, a transfer instruction valid flag is set to "1". With the transfer of the vector data, the mask bits corresponding to each element of the vector data are stored in the VC of the mask register section.
The data is sequentially read from R to the vector register control unit, and is used for controlling writing of data to the destination vector register. This mask bit is returned to the mask register control unit at any time in the read order as mask information of the vector data after the transfer, and the transfer instruction valid flag is selected by the selector circuit by "1", and the mask instruction in the mask register unit The data is written to the VCR and the VMR assigned to the vector data after the transfer.

[0019]

Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a vector data processing device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the mask register control unit 30 in FIG. FIG. 3 is a diagram showing a relationship between data and mask bits in a vector transfer instruction.

For simplicity of description, in FIG. 1, one vector processing unit B and two vector registers for storing vector data are used, and the operation unit for calculating vector data is not directly related to the present invention. Omitted. The vector data processing apparatus according to this embodiment includes a scalar processing unit S for issuing an instruction and generating a mask, and a vector processing unit B for receiving an instruction from the scalar processing unit S and performing vector data processing.

The scalar processing section S is composed of an instruction control section 70 for controlling the issuance of instructions and a mask generating section 80 for generating a mask. The scalar processing section S issues instructions to the vector processing section B, sends mask information, and the like.

The vector processing unit B includes two vector registers 10 and 20, a read address register 11, an address register 21, a vector register 10, and a vector register 10 for specifying respective read addresses of the vector registers 10 and 20. 20, a write address register 12, an address register 22, a vector register 10 and a selection unit 90 for selecting data to be written to the vector register 20, and mask information of vector data stored in the vector register 10 and the vector register 20. Register section 60 for storing data, and selector circuit 5 for selecting input data to mask register section 60
0, writing of mask information to the mask register unit 60,
It comprises a mask register control unit 30 for controlling reading, a vector register 10 and a vector register control unit 40 for controlling writing and reading of vector data to and from the vector register 20.

The vector register 10 and the vector register 20 are assigned different vector register numbers. For example, the vector register 10 has a vector register number 0 (V0) and the vector register 20 has a vector register number 1 (V1), and stores a total of n vector data from element numbers 0 to n-1 of the vector data. Can be.

When a mask generation instruction is issued from the instruction control unit 70, the mask generation unit 80 generates mask information of the vector data stored in the vector registers 10 and 20, and sends it to the mask register control unit 30. The mask information is selected by the selector 50 and written into the mask register unit 60.

FIG. 2 is a detailed block diagram of the mask register control unit. In FIG. 2, the mask register control unit includes:
A mask register unit for storing mask information of vector data stored in a vector register, a transfer instruction valid flag 31 indicating that a transfer instruction is valid when a vector processing instruction is issued, and mask information input to the mask register unit And a selector circuit 50 for selecting mask information from the vector register control unit when the transfer instruction valid flag is "1" and selecting mask information sent from the mask generation unit 80 when the transfer instruction valid flag is "0". Is done.

The mask register section includes a vector register (VCR) 61 for storing mask information of vector data to be processed, and a plurality of registers (VMR0 to VMRm-1, where m is a natural number) used as a save area for the VCR 61. )). Transfer between the VCR 61 and the VMR 62 can be performed as needed. Vector register V0 generated by mask generation instruction
And the mask information of the vector data of V1 is VCR6
VMR 62 assigned to each one or vector data
Is stored in When the vector processing is executed, the mask information of the processing target vector data is once read out to the VCR 61 and used.

When the instruction control unit 70 issues a vector data transfer instruction between vector registers, for example, a vector data transfer instruction (V0 → V1) from the vector register 0 to the vector register 1, the instruction control unit 7
From 0, the instruction code, transfer source vector register number (V0), transfer destination vector register number (V1), transfer start element address, and transfer vector length are passed to the mask register control unit 30 and the vector register control unit 40 as command control information. It is. Here, the transfer start address is “1”, and the vector length is n (n is a natural number).

Referring to FIG. 3, a vector processing apparatus according to one embodiment will be described. FIG. 3 is a conceptual diagram illustrating the state of the vector data transfer process. Mask register control unit 4
When the mask information of the vector data of the vector register V0 as the transfer target data is set in the VCR (FIG. 3A), the data a1 of the first element which is the transfer start address
Are transmitted to the vector register control unit continuously in units of 1 bit from the mask bits corresponding to. (Fig. 3 (b))

The vector register controller 40 sets the transfer start address (here, "1") in the read address register 11 of the transfer source vector register V0, and at the same time, writes the write start address in the write address register 22 of the transfer destination vector register V1. Set "0". The read address register 11 starts counting up from the set address “1”.

Accordingly, n pieces of data indicated by the vector length are sequentially read from the vector data a1 of the element number 1 and transferred to the transfer destination vector register V1 via the selector 90.
Sent to (FIG. 3 (c)) Writing of vector data to the vector register V1 refers to mask bits (FIG. 3 (b)) sequentially read from the mask register unit 60 to the vector register control unit 40 corresponding to the transfer element. , Only the element whose mask bit is “1” is written, and writing of the element whose mask bit is “0” is suppressed.

The above operation is repeated for the vector length, and the transfer processing of the vector data in which the last element is written to the vector register V1 is completed. (FIG. 3 (e)) The mask bit read from the VCR 61 of the mask register unit 60 and used for the write control of the vector data (
FIG. 3B) is returned to the mask register control unit 30 at any time in the read order. Since the transfer instruction valid flag is “1”, the data is selected by the selector circuit 50 and written into the VCR 61 of the mask register unit 60 and the VMR 62 assigned to the vector data after transfer. Since this process is performed in parallel with the transfer process of the vector data, the storage of the mask information ends when the writing of the last element of the vector data is completed. (Fig. 3 (d))

As described above, when a vector data transfer instruction is issued between the vector registers 10 and 20, when the vector data is transferred, the VCR in the mask register unit 60 sequentially corresponds to each element as the vector data is transferred. Focusing on the fact that the mask bits read by the vector register control unit 40 and used for controlling the writing of data to the vector register 10 or the vector register 20 of the transfer destination can be used as is as the mask information after the transfer, the read is performed. By returning the mask bit to the mask register unit 60 and writing the mask bit to the VCR 61 and the VMR 62, generation and writing of the mask information of the data after the transfer can be performed.
It can be completed in parallel with the data transfer process.
Therefore, it is not necessary to generate a mask after the transfer processing of the transfer data as in the prior art, so that the speed of the vector processing can be increased.

[0033]

As described above, according to the present invention,
When a vector data transfer instruction is issued between vector registers, the data is sequentially read from the mask register corresponding to each element in accordance with the transfer of the vector data, and is used to control writing of data to the vector register of the transfer destination. Focusing on the fact that the mask bits can be used as is as the mask information after the transfer, and by writing the read mask bits back to the mask register, generation and writing of the mask information of the data after the transfer can be performed by the data transfer processing and the data transfer processing. Can be completed in parallel. Therefore, it is not necessary to generate a mask after the transfer processing of the transfer data as in the prior art, so that the speed of the vector processing can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a vector processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a mask register control unit 30 in FIG.

FIG. 3 is a conceptual diagram showing an operation of a vector data transfer process in the vector processing device of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a vector processing device according to a conventional example.

[Explanation of symbols]

 10, 20 ... vector register 11, 21 ... read address register 12, 22 ... write address register 30 ... mask register control unit 31 ... transfer instruction valid flag 40 ... ..Vector register control unit 50... Selector circuit 60... Mask register unit 61... VCR (vector register) 62... VMR (evacuation area of VCR) 70. ··· Instruction control unit 80 ···· Mask generation unit 90 ···· Vector data selection unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/16

Claims (1)

(57) [Claims] A plurality of vector registers for holding vector data; a plurality of mask registers for storing mask information indicating valid / invalid of each element of the vector data held in the vector registers; and and a plurality of arithmetic units for processing the vector data, a row vector data transfer instructions between said vector registers
In this case, the vector data of the transfer source is
Is read out for each element of the
Used to control writing vector data to the register
Mask bit, mask information of vector data after transfer
Mask register in parallel with vector data transfer processing
A vector data processing device characterized by writing data to a star .