JPH03141444A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the instruction processing time by detecting whether a space register having the same number as a designated one is available or not and saving temporarily an STO (reference point address) to be written into an STO register when a base changing case is detected. CONSTITUTION:When an instruction is carried out for change of the contents of a space register 3, a base change detecting circuit 5 detects that the register 3 designated in an instruction base field is equal to the register 3 whose contents are changed. A saving means 16 saves temporarily the STO to be written into an STO register 4 corresponding to the register 3 designated by the base field based on the output of the circuit 5. Then the register 4 corresponding to the register 3 having the same number as the base field writes the data to the end of an STO register group corresponding to the continuous registers 3 to be changed at change of the base of an LAM (load access multiple) instruction. Thus the instruction processing time is shortened in a base changing case.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to LAM (Load Access Mult
iple) instruction, the number of the space register specified in the base field and one of the space register group to be changed.
The present invention relates to a data processing device that shortens the processing time when instructions are the same number.

[Prior art]

Data processing using a multiple virtual space address method in which the contents of a space register (AR) specified by the base field of an instruction are converted by a space address conversion mechanism into a base address (segment table origin: 5TO) for performing real address conversion. The method is known (e.g.
Patent application No. 63-244398).

[Problem to be solved by the invention]

In the data processing method described above, when a LAM instruction that changes a plurality of consecutive ARs is executed, the base address register (STO register) that holds the changed AR and the corresponding STO are also rewritten.

At that time, for example, if one of the AR numbers to be changed and the AR number specified by the base field are the same number, the following problem occurs.

That is, when reading operand data for rewriting, the segment table to be used is specified by the STO in the STO register that corresponds to the AR space specified by the base field, and the address is converted to a real address using the table. However, since this instruction rewrites the AR or STO register, there is a problem in that the contents of the STO register having the same number as the base field are rewritten during the instruction.

Hereinafter, such a case will be referred to as a base change case.

Therefore, in order to prevent the ST○ register from being rewritten in the middle of an instruction in such a base change case, for the STO register with the same number as the base field,
The last write in the series of STO registers to be changed must be made.

To do this, data is read from the main memory in order to rewrite the AR, and finally, in order to rewrite the STO register with the same number as the base field, the data to be written in the AR with the same number is read out from the main memory and the STO register has the same number as the base field. The present invention has been made to solve the above problem. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that reduces instruction processing time for LAM instructions in base change cases.

Means for Solving Problem C] In order to achieve the above object, when an instruction that changes the contents of a space register is executed, the contents of the space register specified by the base field of the instruction are changed. A means for detecting whether the space register is the same as a space register, and a saving means for temporarily saving a base address to be written to a base address register corresponding to the space register specified by the base field based on the output of the detecting means. Ta.

[For production]

According to the above-mentioned means, when changing the base of a LAM instruction,
S corresponding to the space register with the same number as the base field
The TO register is written at the end of the ST○ register group corresponding to consecutive space registers to be changed.

For this purpose, it is detected whether or not there is a space register with the same number as the number specified in the base field in a continuous space register group, and if a case of base change is detected, the ST○ register is Temporarily save the STO to be written.

At the end of a series of STO register groups to be changed, the saved STO is read and written to the STO register.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a system configuration diagram that is an embodiment of the present invention, in which 1 is an instruction register and 2 is a general purpose register group (GPR).
, 3 is a space register group (AR), 4 is a base point address register group (STO register) holding a base point address (segment table origin: 5TO), 5 is a base change detection circuit, 6 is an ALB reference address generation circuit, 7 is a space register index buffer (A RTranslat
ion LookasideBuffer: A L
B), 8 is an address calculator, 9, io is a control register (CR), 11 is a real address translation mechanism, 12 is a spatial address translation mechanism, 13 is an ALB hit detection circuit, 16
is the STO save register.

When executing a LAM instruction, the numbers of R□, R2 and B fields specified in the LAM instruction are written in lines 19 to 21.
The base change detection circuit 5 detects whether or not there is an AR with the same number as the number in the B field among the AR group to be changed specified in the R2 field.

On the other hand, the real address translation mechanism 11 generates an operand address for accessing the main memory 18 in which the contents of the AR group to be changed are stored.

That is, the contents of the general-purpose register 2 specified by the B field of the instruction and the D field are input to the address calculator 8 to calculate an address and generate a virtual address.

Then, in order to convert the virtual address to a real address, the base address (STO) is usually read from the STO register 4 having the same number as the B field and inputted to the real address conversion mechanism 11 via line 29. The virtual address is converted to a real address, but the S
When the V bit of the TO register 4 is '1', the STO register 4 is valid, and the STO register 4 is
is read out, converted into a real address as described above, and the operand data is read out from the main memory device 18. The read operand data is written into corresponding AR3 starting with the number in the R□ field of the instruction and ending with the number in the R2 field.

On the other hand, the V of ST○ register 4 that was attempted to be read.
If the bit is O' and invalid, AR3 with the same number as the B field registered before the execution of the LAM instruction
is read out via line 34 and input to the ALB reference address generation circuit 6 together with the control register 9 or 10, thereby generating an ALB reference address. and,
ALB 7 is referenced by the address, and if data including STO is registered in the ALB output to the ALB hit detection circuit 13, S is read from the ALB read register 14.
TO is read and input via line 28 to the real address translator II.

Furthermore, when ALB 7 is referenced, if the ALB hit detection circuit 13 detects that no STO is registered in the ALB, the AR with the same number as the B field is read out via line 33 and the AR is read out via line 35. The spatial address translation mechanism 12 together with the control register 9 or 10
The STO is input to the real address translation mechanism 11 via line 30.

As described above, the AR is rewritten, but as described above, the LAM instruction must also rewrite the STo register corresponding to the AR.

A method of registering the STO register using the LAMb instruction will be described below.

Assume that the B field specifies number m, and the R and R2 fields specify numbers n and 15, respectively. As mentioned above, when the LAM instruction rewrites AR group 3 from ARn to AR, ALB reference is made using the ALB reference address generation circuit 6 using the rewritten data and control register 9 or lO of each AR. Generate an address. ALB7 is referred to using the generated ALB reference address, and the ALB hit detection circuit 13 sets ST to ALB7.
It is detected whether data including O is registered. A
If registered in LB7, ALB read register 1
4. Read STO to STO write register 15,
The read STO is sent to the selector circuit 17, line 38
are written to the STO registers number n to 15 through the STO register.

However, when a base change is detected by the base change detection circuit 5, the STO read from ARm with the same number as the B field is saved to the STO save register 16,
At the same time, the selector circuit 17 inhibits writing to the m-th STO register.

Then, other specified S except for the m-th STO register
When the registration of the STO in the TO register is completed, the selector circuit 17 is controlled by the base change detection circuit 5 via the line 36, the STO saved in the STO save register 16 is read out, and the STO is saved in the m-th STO register. By being registered, the LAM instruction completes processing.

Note that when ALB 7 is referenced, STO is added to ALB 7.
If the data including the STO register is not registered, the ALB hit detection circuit 13 writes O' to the v bit of the corresponding STO register in the ST○ register group via line 37, thereby invalidating the corresponding STO register. Invalid ST○
The register performs spatial address translation and reregistration when used in the base field of a subsequent instruction.

In addition, in the case of base change, without directly changing the V bit in the STO register group, the V bit added to the register 16 after saving the STO is set as jOl, and when using the STO save register 16, the V bit is Cause bit 10' to be written to the STO register.

〔Effect of the invention〕

As described above, according to the present invention, even if the number specified in the base field of the LAM instruction and one of the space register groups to be changed are the same number, an error in the space address is prevented when calculating the operand address. No, LA again
The processing time of M instructions can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram that is an embodiment of the present invention. In the figure, 1... instruction register, 2... general purpose register group, 3... space register group, 4... base address register group, 5... base change detection circuit, 6... ALB
Reference address generation circuit, 7... Space register index buffer. 8...Address calculator, 9.10...Control register, 11...Real address translation mechanism,! 2... Spatial address conversion mechanism, 13... ALB hit detection circuit,
16...STO save register

Claims (1)

[Claims] 1. A space address translation mechanism that converts the contents of a space register specified by the base field of an instruction into a base address for performing real address translation, and holds the base address provided corresponding to the space register. In a multi-virtual space addressing system data processing device having a base point address register, when an instruction to change the contents of a space register is executed, the contents of the space register specified by the base field of the instruction are changed. A means for detecting whether the space register is the same as a space register, and a saving means for temporarily saving a base address to be written to a base address register corresponding to the space register specified by the base field based on the output of the detecting means. A data processing device characterized by: