JPH01177145A - Information processor - Google Patents

Abstract

PURPOSE:To improve the executing efficiency of an instruction by providing a 2nd address conversion buffer that can be retrieved by the values of the base register number and the index register number which are designated by the instruction. CONSTITUTION:The 2nd address conversion buffer 8 defines the coupled value of a base address 104 and the index value 105 which are designated by the instructions respectively as an address and can freely store a physical address corresponding to said address as well as a valid bit showing whether the stored physical address is valid or not. Then the operand data 111 can be taken out in a 2nd cycle for execution of instructions which is faster than the conventional cycle by one cycle as long as a physical page address 205 of the data 111 is stored in the buffer 8 when the address 104 and the value 105 are supplied by each instruction. Thus the executing efficiency of an instruction is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device using a virtual storage method that determines the logical address of an operand based on a base address, index value, and displacement.

BACKGROUND OF THE INVENTION The process of fetching operands in a conventional information processing apparatus will be explained with reference to the block diagram of FIG. As shown in FIG. 2, in the first cycle of instruction execution, base register number 101 and index register number 102 specified by the instruction are given to base register 2 and index register 3, respectively, and base address 104 and index value 10 are given to base register 2 and index register 3, respectively.
Get 5 each.

The three-manpower adder 1 inputs a base address 104, an index value 105, and a displacement 103 designated by a command, and outputs an effective address 106 to the logical address register 4.

Subsequently, in the second cycle, the upper bits 107 of the logical address register 4 are given to the address conversion buffer 5 to output the page address 109, which is then delivered to the physical address register 6 together with the lower bits 108 of the logical address register 4.

In the third cycle, the output 11 of the physical address register 6
0 to the buffer memory circuit 7. If the operand data exists in the buffer memory, immediately, if it does not exist, it is retrieved from the main memory and then #! 1. Operand data 111 is taken out as the output of the negative storage circuit 7.

In this way, in the conventional information processing device, RI! Even when an operand exists in the memory, three cycles are required to retrieve the operand, so there is a drawback that the effective efficiency of the instruction is low.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can improve instruction execution efficiency.

Structure of the Invention According to the present invention, there is provided a means for generating a physical address by adding a base address and an index value respectively specified by an instruction, and a first address conversion device storing a logical address corresponding to the physical address. an information processing device that includes a buffer and accesses a Kuragaiji/failure circuit using a logical address output from the address translation buffer, the address being a combined value of the base address and the index value; A second address translation buffer is provided that can store a physical address corresponding to this address and also store a valid bit indicating whether or not this stored physical address is valid, and the base register and index value are input by a command. When the valid bit obtained by accessing the second address translation buffer with the combined value of the base address and index value indicates invalid, the valid bit corresponding to the first address translation is set to be valid. An information processing device is obtained, characterized in that when the valid bit indicates valid, the buffer storage circuit is accessed using the access output of the second address translation buffer.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, parts equivalent to those in FIG. 2 are indicated by the same reference numerals. In the operand fetching process according to this embodiment, first, in the first cycle of instruction execution, the base register number 101 and index register number 102 specified by the instruction are given to the base register 2 and index register 3, respectively.
A bit base address 104 and a 32-bit index value 105 are obtained. The 3-manual adder 1 uses a base address 104, an index value 105, and 1 specified by the instruction.
It inputs the 2-bit displacement 103 and outputs the 32-bit effective address 106 to the logical address register 4.

At the same time, a second address translation buffer 8 consisting of two fields is set to the address that is the combination of the base register number 101 and the inch register number 102.
access. Here, even if the same base address and index value are used, the value of the upper 20 bits of the effective address will differ depending on the magnitude of the displacement. Therefore, it is assumed that the corresponding physical page addresses are stored in each field of the second address translation buffer 8.

Third choice? 8 is the first field output 201 of the second address translation buffer 8 if there is no carry 203 from the lower 12 bits of the three-manual adder 1, and the second field output 201 of the second address translation buffer 8 if there is. Select each field output 202.

Subsequently, in the second cycle, the upper 20 bits 107 of the logical address register 4 are given to the first address translation buffer 5 to output the first physical page address 109.

The first selection circuit 10 selects the second physical page address 205 that is the output of the selection circuit 9 when the valid bit 204 that is the output of the third selection circuit 9 is valid, and the first address when the valid bit 204 is the output of the third selection circuit 9. The first physical page address 109 which is the output of the conversion buffer 5 is selected respectively. Second selection circuit 1
1 selects the lower 12 bits 106 of the effective address when the valid bit 204 is valid, and selects the lower 12 bits 108 of the logical address register 4 when it is invalid. Then, the output 206 of the first selection circuit 10 and the second selection circuit 1
The value obtained by combining the output 207 of 1 is given as an input to the physical address register 6.

If the valid bit 204 is valid, the address conversion control circuit 12 provides an input enable signal 208 to the physical address register 6 in the first cycle of instruction execution, and outputs the output 206 of the first selection circuit 10 and the second selection circuit 11. Output 207 of
, i.e., the second physical page address 205
and the lower 12 bits 106 of the effective address are combined into the physical address register 6. Then, in the next second cycle, a data read request 209 is given to the v1 storage circuit 7. Therefore, operand data 111 is taken out as the output of the buffer storage circuit 7 immediately if the operand data exists in the M memory, or after being taken out from the main memory (not shown) if it does not exist.

If the valid bit 204 is invalid, the input enable signal 208 is given to the physical address register 6 in the second cycle of instruction execution, and the output 206 of the first selection circuit 10 and the output 207 of the second selection circuit 11 are A value that is a combination of the first physical page address 109 and the lower 12 bits 108 of the logical address register 4 is loaded into the physical address register 6. At the same time, if there is no carry 203 in the second address translation buffer 8, the base register number 101 of the first field is combined, and if there is, the base register number 101 and index register number 102 of the second field are combined. A second address translation buffer update instruction 212 is given to the second address translation buffer 8 in order to store the first physical page address 109 and a value indicating the valid state at the address determined by the value. As a result, the second address translation buffer 8 always stores the most recently read page address among the physical page addresses stored in the first address translation buffer 5. Then, in the third cycle, a data read request 209 is given to the storage circuit 7.

Therefore, if the operand data exists in the M street memory, it is immediately retrieved, and if it does not exist, it is retrieved from the main memory.
Operand data 111 is taken out as the output of buffer storage circuit 7.

The invalidation control circuit 13 receives the microinstruction decode signal 210
When it is learned that base register 2 or index register 3 has been rewritten, the second address translation bar y
A valid bit invalidation instruction 211 is issued to the address corresponding to the number of the base register or index register that has been @ changed in the file 8 to prevent erroneous address conversion from being performed.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by providing a second address translation buffer that can be searched based on the values of the base register number and index register number specified by an instruction, If the physical page address of the operand data is stored, the operand data can be retrieved in the second cycle of instruction execution, which is one cycle earlier than the conventional method, so that the efficiency of instruction execution becomes higher than the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional information processing apparatus. Explanation of symbols of main parts 1...Adder 2...Base register 3...Index register 4...Logical address register 5.8... ...Address translation buffer 6...
・Physical address register 7...Buffer memory 9.10.11...Selection circuit 12...Address conversion control circuit 13...
・Disable control circuit

Claims (1)

[Claims] (1) means for generating a physical address by adding a base address and an index value respectively specified by an instruction;
An information processing device including a first address translation buffer storing a logical address corresponding to the physical address, and a buffer storage circuit is accessed by the logical address output from the address translation buffer,
A second address that has a combined value of the base address and the index value as an address and can store a physical address corresponding to this address and can also store a valid bit indicating whether or not this stored physical address is valid. A translation buffer is provided, and when the base register and index value are input by an instruction, the valid bit obtained by accessing the second address translation buffer with a combined value of the base address and index value indicates invalidity. When the physical address output from the first address translation buffer is stored in the corresponding address of the second address translation buffer, the corresponding valid bit is made valid, and when the valid bit indicates valid, the second address is An information processing device characterized in that the buffer storage circuit is accessed using an access output of a conversion buffer.