JPH04277846A - High-speed address converting system - Google Patents

Abstract

PURPOSE:To convert a physical address from a logical address at high speed concerning the address converting system at an information processor adopting a virtual memory system. CONSTITUTION:At the information processor adopting the virtual memory system, having a first address converting mechanism 3 composed of a dynamic address converting mechanism DAT and an address converting buffer TLB, generating a logical address 4 by using plural resource registers, etc., designated by the field of instruction and calculating the required physical address by applying the logical address 4 to the first with the resource information designated by the field of the instruction, the logical address 4 is generated parallelly with the conversion to the physical address 7 at the second address converting mechanism 6, the address converted by the TLB cache is used in the case of hit at the second address converting mechanism 6, and the address converted by the first address converting mechanism 3 is used in the case of miss hit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention employs a virtual storage method,
It has a first address translation mechanism consisting of a dynamic address translation mechanism (DAT) and an address translation buffer (TLB), and has multiple resources specified in the instruction field, such as a base register (B) and a displacement ( D), or information processing in which a logical address is generated using a base register (B) and an index register (X), etc., and the logical address is given to the first address translation mechanism to obtain the necessary physical address. The present invention relates to a high-speed address translation mechanism in a device.

[0002] With the recent diversification of functions and increase in processing capacity of information processing devices, there is a demand for increased capacity of main storage devices and faster information processing. As one measure to increase the capacity of the main storage device, an information processing device that uses a virtual storage method is used.

[0003] In an information processing device that uses this virtual storage method, programs and data are usually stored in a file storage device (DAS) that has a huge address space.
D), and if necessary, the programs and data stored on the file storage device (DASD) are paged in and expanded on the main storage device in units of pages, for example. By performing data processing at high speed between a central processing unit (CPU) and the main storage device, the apparent address space of the storage device is increased.

[0004] In this case, on the central processing unit (CPU), a logical address where data exists is generated, and the real address where the data of the generated logical address exists on the main storage device is determined. Although the main memory is accessed, there is a problem in that the address translation takes time, and an efficient address translation method is required.

[0005]

[Prior Art] FIGS. 5 and 6 are diagrams explaining conventional address translation methods, where FIG. 5(a) shows a dynamic address translation (DAT) method, and FIG. 6(b) shows an address translation buffer. (TLB) Indicates the method.

[0006] Conventionally, in an information processing apparatus employing a virtual memory method, there is a means for performing dynamic address translation (DAT) for obtaining a real address on a main storage device from a logical address.
0 is instruction register 1, as shown in Figure 6(a).
Instruction resources (1) to 10 set to , for example,
Base register (B) and index register (
X), or calculate the address using the base register (B) and the displacement (D) to generate a logical address, and then select the segment shown in the figure based on the segment number of the generated logical address. The segment table 301 indicated by the control register 300 in which the table entry is set is indexed, the page table 302 is indexed based on the page table entry indicated by the segment table 301, and the generated logical address (page address ) into the corresponding physical address (actual page address).

[0007]

[Problem to be Solved by the Invention] In the above dynamic address translation method, it is necessary to index the segment table 301 and page table 302 in order every time an address is translated, so it takes time to generate a physical address. There is a problem.

In order to improve this problem, a method using an address translation buffer (TLB) 31 shown in FIG. 6(b) is often used. In this method of using the address translation buffer (TLB) 31, the physical address translated by the dynamic address translation (DAT) mechanism 30 is combined with the address translation buffer (TLB) using a part of the logical address as a tag address. ) 31, it is held in the cache memory of the dynamic address translation (DAT) mechanism 30, and from the second and subsequent logical address translations, it is stored in the address translation buffer (TLB) 3.
By indexing 1, physical addresses can be indexed quickly.

However, this address translation buffer (TLB
) 31, as is clear from FIG. 6(b), the instruction resources (1) to 10 set in instruction register 1, for example, the base register (B) and the index register (X ) etc., the address translation buffer (TLB) 31 cannot be indexed until the generation of the logical address in the logical address register 4 is completed, so there is a problem that the speed cannot be increased any further.

In view of the above-mentioned conventional drawbacks, the present invention adopts a virtual memory system and uses a dynamic address translation mechanism (DAT).
It has an address translation mechanism consisting of an address translation buffer (TLB), and has multiple resources (
In an information processing device that generates a logical address using a register (such as a register, etc.) and provides the logical address to the address translation mechanism to obtain the necessary physical address, the generation of the logical address and parallel processing process the instructions in the instruction. using resources,
The object of this invention is to provide a means for indexing a physical address from a logical address at an earlier stage than indexing the address translation buffer (TLB).

[0011]

[Means for Solving the Problems] FIGS. 1 and 2 are diagrams showing the principle configuration of the present invention, FIG. 1(a) shows an example of the configuration, and FIG.
(b) shows an operation time chart. The above problem can be solved by a high speed address translation method configured as follows.

(1) A first address translation mechanism employs a virtual memory system and consists of a dynamic address translation mechanism (DAT) 30 and an address translation buffer (TLB) 31.
3, generates a logical address using a plurality of resources specified in a field 10 of an instruction, and provides the logical address to the first address translation mechanism 3 to obtain a necessary physical address. , the second search using the resource information specified in field 10 of the instruction.
A second address translation mechanism 6 is provided to generate a logical address using a plurality of resources specified in field 10 of the above instruction, and to search using resource information specified in field 10 of the above instruction. When there is a hit in the second address translation mechanism 6, the translated address by the second address translation mechanism 6 is used, and when there is a miss, the above conversion process is performed in parallel. The first address translation mechanism 3 is configured to use translated addresses.

(2) Second address translation mechanism 6
It is configured by copying a part of the address translation buffer (TLB) 31.

[0014]

[Operation] In order to solve the above-mentioned problems, in the present invention,
The resource in the instruction code set to instruction register 1 (1
) 10 directly to index the physical address from the logical address in parallel with the logical address generation process performed using the resource (1) 10.

Specifically, as shown in FIG. 1(a),
Conventional address translation mechanism (first address translation mechanism)
3 Separately, a means for storing a logical address tag using a page portion of a logical address and a corresponding physical address, that is, a second address translation mechanism 6, and an instruction resource (1) 10, e.g. , the information in the base register (B) specification field 10 can be indexed as a line address.

With this second address translation mechanism 6,
In the case of a hit, as is clear from the operation time chart shown in FIG. This has the effect of being able to obtain a physical address and perform high-speed address translation.

Of course, the second address translation mechanism of the present invention
6 is, for example, an instruction resource (1). Since 10 is a line address, it cannot be used as a conventional address translation buffer (TLB).
) {As shown in Figure 6 (b), part of the page specification part of the logical address generated using instruction resources (1), (2) 10, etc. is used as the line address. }Compared to 31, the capacity is small.

Therefore, if the generated logical address is in the same range as the original page, the second address translation mechanism 6 of the present invention will definitely hit, but the generated logical address will be in the same range as the original page. If the number exceeds a page, even if there is a hit in the address translation buffer (TLB) 31, it will be a miss in the second address translation mechanism 6. In this case, the physical address translated by the conventional first address translation mechanism 3 is used.

Considering that there is usually locality in the address distribution of programs and data, the probability of the above-mentioned miss is small and does not hinder the present invention.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. 1 and 2 described above are diagrams explaining the principle of the present invention, and FIGS. 3 and 4 are diagrams showing an embodiment of the present invention.

[0021] In the present invention, a virtual storage method is adopted,
It has a first address translation mechanism 3 consisting of a dynamic address translation mechanism (DAT) 30 and an address translation buffer (TLB) 31, and generates a logical address using a plurality of resources specified in a field 10 of an instruction. In an information processing device that provides the logical address to the first address translation mechanism 3 to obtain a necessary physical address,
A second address translation mechanism 6 that searches using resource information specified in field 10 of the instruction is provided to generate a logical address using a plurality of resources specified in field 10 of the instruction;
The process of converting a logical address to a physical address by the second address translation mechanism 6 searched by the resource information specified by is performed in parallel, and when a hit is found in the second address translation mechanism 6, the second address conversion A means for using the translated address by the first address translation mechanism 6 and, in the case of a miss, using the translated address by the first address translation mechanism 3, is a necessary means for implementing the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, while referring to FIGS. 1 and 2, FIGS.
The high-speed address conversion method of the present invention will be explained using FIG. 4. First, in FIGS. 3 and 4, 1 indicates an instruction register, and in the instruction code set in instruction register 1, B, D, and R are the base register number, displacement, and result storage register number, respectively. This is field 10 representing . 2 is a register file of general-purpose registers, and the corresponding register is accessed using the value of B as a line address. This data is used as the base address for address calculations. 25 is an adder that generates a logical address by adding the output of the register file 2 of the general-purpose register and the displacement (D) 10 of the instruction register 1. 4 is a logical address register for holding the address generated by the adder 25. 31 is a conventional address translation buffer (TLB) {see Figure 6(b)}
It is. 6 is a second address translation mechanism (TLB cache) for realizing the means of the present invention, and is a high-speed RAM whose number of lines for holding logical address tags and physical page addresses is the same as that of general-purpose register file 2. It is configured. 7 is the second address translation mechanism (T
This is a multiplexer (MPX) that switches between the output from the LB cache (LB cache) 6 and the output from the first address translation mechanism 3.

The specific operation will be explained below. Even if the present invention is implemented, the operation of the first address translation mechanism 3 will not change in particular, so it will be omitted, and here, the second address translation mechanism 3 of the present invention will be omitted.
The operation of the address translation mechanism 6 will be mainly explained.

The second address translation mechanism (T
LB cache) 6 is indexed. At this time, the adder
The address corresponding to the tag, for example, the page address part of the logical address as a result of the address calculation calculated in step 25, is transferred to the second address translation mechanism (T
It is compared with the logical address tag of LB cache) 6 and a hit is determined.

If there is a hit, the physical address indexed by the second address translation mechanism (TLB cache) 6 is used as the memory access address. If there is a miss, the result of the conventional address translation buffer (TLB) 31 is used. In this case, the conventional address translation mechanism may have any configuration.

In this embodiment, the number of the base register (B) is the line address of the second address translation mechanism (TLB cache) 6, but there is no need to limit it to this, and it depends on the amount of hardware. You can decide by doing so.

Storage of the logical address tag and the corresponding physical address in the second address translation mechanism (TLB cache) 6 is performed using the above-mentioned dynamic address translation (DAT).
When registering the physical address obtained by address translation in the mechanism 30 in the address translation buffer (TLB) 31, it is sufficient to register it together with the page address part (logical address tag) of the corresponding logical address register 4. .

Next, another embodiment of the present invention will be described with reference to FIG.
This will be explained using FIG. 4. In this example, the program's
For example, when branching from the main program to a subroutine and returning to the original main program, when branching from the main program to the subroutine, the return information is stored in a specific general-purpose register {base register (B)} of register file 2. By setting the address (however, a logical address), the processing of the subroutine can be completed and the base register (B
When specifying the physical address of the return address (logical address) set in the general-purpose register 2, the second address translation mechanism 6 of the present invention and the address translation buffer (TLB) for the operand are used. By using 31, the real address of the return address can be found at high speed.

As described above, the present invention employs a virtual memory system, has a first address translation mechanism 3 consisting of a dynamic address translation mechanism (DAT) 30, and an address translation buffer (TLB) 31, and 10 Generate a logical address using multiple resources specified in
In the information processing apparatus that gives the logical address to the first address translation mechanism 3 to obtain the necessary physical address, a second address translation mechanism 6 is provided that searches using resource information specified in the field 10 of the instruction. , generation of a logical address using multiple resources specified in field 10 of the above instruction, and conversion from a logical address to a physical address by a second address conversion mechanism 6 that searches using resource information specified in field 10 of the above instruction. The second address translation mechanism performs the conversion process in parallel.
6, the second address translation mechanism
6 is used, and in the event of a miss, the address translated by the first address translation mechanism 3 is used.

[0030]

[Effects of the Invention] As explained above in detail, the high-speed address translation method of the present invention uses a virtual memory method, and has a first address translation system consisting of a dynamic address translation mechanism (DAT) and an address translation buffer (TLB). It has an address translation mechanism, generates a logical address using multiple resources (registers, etc.) specified in the instruction field, and gives the logical address to the first address translation mechanism to obtain the required physical address. In the information processing device, a second address translation mechanism (TLB cache) is provided to search using resource information specified in the field of the instruction, and the logical address is generated and converted to a physical address by the second address translation mechanism. are performed in parallel, and when there is a hit in the second address translation mechanism, the address translated by the TLB cache is used, and in the case of a miss, the address translated by the first address translation mechanism is used. Therefore, it is possible to extract a necessary physical address while calculating a logical address, which has the effect of providing a high-speed address translation mechanism.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention (Part 1)

[Figure 2] Diagram explaining the principle of the present invention (Part 2)

[Fig. 3] Diagram showing one embodiment of the present invention (Part 1)

[Fig. 4] Diagram showing one embodiment of the present invention (Part 2)

[Figure 5] Diagram explaining the conventional address conversion method (Part 1)

[Figure 6] Diagram explaining the conventional address conversion method (Part 2)
)

[Explanation of symbols]

1 Instruction register
10 Field {Resource (1), ~} 2 General-purpose register file 2
5 Adder 3 First address translation mechanism 30 Dynamic address translation mechanism (DAT) 3
1 Address translation buffer (TLB) 300 Control register
301 Segment table 302 Page table 4 Logical address register 6 Second address translation mechanism

Claims (2)

[Claims] Claim 1: Adopts a virtual memory system and includes a dynamic address translation mechanism (DAT) (30) and an address translation buffer (T
LB) (31) The first address translation mechanism (3
), generates a logical address using a plurality of resources specified in the field (10) of the instruction, and gives the logical address to the first address translation mechanism (3),
In an information processing device that searches for a necessary physical address, a second address translation mechanism (6) is provided to search using resource information specified in field (10) of the instruction, and a plurality of addresses specified in field (10) of the instruction are provided. The generation of a logical address using the resources of the above instruction and the field (1
The process of converting a logical address to a physical address by the second address translation mechanism (6), which searches using the resource information specified in 0), is performed in parallel, and the second address translation mechanism (6)
6) When there is a hit, the address translated by the second address translation mechanism (6) is used, and when there is a miss, the address translated by the first address translation mechanism (3) is used. High-speed address translation method. 2. The high-speed address translation according to claim 1, wherein the second address translation mechanism (6) is configured by copying a part of the address translation buffer (TLB) (31). method.