KR0136511B1 - Processor of fitness-failure of tlb - Google Patents

Abstract

The present invention includes a first buffer 12 for storing a virtual address representing a page of the last immediately preceding step; A second buffer 13 for storing a process number when supporting multiple processors; A third buffer 14 in which the actual address of the lowest page table is stored; And a control means (11) for controlling the first to third buffers (12, 13, 14) according to the input virtual address, and having a multi-page structure mounted in the virtual address memory management apparatus. The present invention relates to a hit failure processing apparatus of a virtual address translation apparatus having a multi-page structure which has an effect of improving the performance of a system by shortening the address translation failure processing delay time of the address translation apparatus.

Description

Hit failure processing device and method for virtual address translator with multi-page structure

1 is an explanatory diagram showing a hit failure processing method of a conventional virtual address translation apparatus having a multi-page structure.

2 conceptually illustrates a virtual address storage memory.

3 is a structural diagram of a hit failure processing apparatus of a virtual address translation apparatus having a multi-page structure according to the present invention.

* Explanation of symbols for main parts of the drawings

11 controller 12 to 13 buffer

The present invention relates to an apparatus for processing a failure of a virtual address translator having a multi-page structure and a method thereof, which improves the efficiency reduction caused by the failure of the virtual address translator having a multi-page structure.

In general, a high performance computer system includes a multi-page structured virtual address translator in a microprocessor using a virtual address for efficient use of memory. In computer systems, memory management techniques, such as virtual addresses and page concepts, are used to load large executable programs into limited main memory. There is also a page-partitioning technique for embedding an executable program in main memory, which includes a variable-size page splitting method and a fixed-size page splitting method. There are two or more multi-page splitting techniques in the flexible and flexible page splitting technique, which is the most efficient splitting technique and is used as a virtual address memory management technique in many computer systems.

When the multi-page split memory management device uses a virtual address, a device that translates a virtual address into a physical address inside the memory management device, that is, a virtual address translation device (collectively referred to as TLB; Translation Lookaside Buffer; hereinafter referred to as TLB) Has

When the virtual address translator in the multi-page structure fails to perform address translation, an operation for address translation failure processing is performed. The prior art of this operation is shown in FIG. Take a look.

FIG. 1 is an explanatory diagram showing a hit failure processing method of a conventional virtual address translation apparatus having a multi-page structure.

First, the virtual address generated in the microprocessor is stored in the memory 1, and the process number is stored in the memory 2 to form a virtual address of N levels (meaning N-level page hierarchy).

When the virtual address translator fails, the N-1 level page table pointer address in the N level page table existing in main memory is read as the N level address of the memory (2). The N-1 level address of the memory 1 is combined to read the N-2 level page table designation address in the N-1 level page table. This process is performed until the last page table address in the first page table is read, and the conversion failure process is completed by registering the last page table address in the TLB.

At this time, the delay time required for the address translation failure processing is expressed by the following equation (1).

Here, dT is the delay time of one address translation failure processing, N is the number of page hierarchies in the multi-page structure, dM is the time to read the built-in page table in main memory once, and Tup is the time to register a new page address in the TLB. Respectively.

Therefore, a single address translation failure causes the microprocessor to stop operating for as long as dT, thereby degrading the overall performance of the microprocessor and the computer system using the same.

The performance degradation rate at this time is dT / (one instruction processing time) x address translation failure processing rate. This degradation has been a major cause of data degradation in high speed devices such as high performance microprocessors in the form of reduced instruction set computers (RISCs).

Therefore, the present invention devised to solve the above problem, by using the locality of the page, the address translation failure processing delay time of the virtual address translator having a multi-page structure mounted in the virtual address memory management device is shortened It is an object of the present invention to provide an apparatus and method for processing a hit failure of a virtual address translator having a multi-page structure.

In order to achieve the above object, the present invention provides a virtual address translation having an N page structure for shortening the entire address translation failure processing time when the first and second address translation failures for the first virtual address and the second virtual address are consecutive. 11. A miss handling apparatus of an apparatus comprising: first storage means for storing a process number when supporting multiple processes; Second storage means for storing a virtual address of steps N-1 to 2 of the first virtual address; Third storage means for storing a first-stage page table pointer address generated during a process of failing the first address translation; And controlling the first to third storage means according to the input virtual address, and comparing the input virtual address with contents stored in the second storage means, when the process is replaced, the first and second storage means. A function of invalidating a valid bit of the second storage means; controlling to store up to page 2 of the first virtual address in the second storage means; and storing the first level page table pointer address in the third storage means. And a failure failure processing apparatus of the virtual address translation apparatus having a multi-page structure including a control means configured to have a function of controlling a function and a function of controlling a process number to be stored in the first storage means when the process is replaced.

In addition, in the hit failure processing method of the virtual address translation apparatus having an N page structure for shortening the entire address translation failure processing time in the case of successive first and second address translation failures for the first virtual address and the second virtual address. A first step of completing a conversion failure process by generating a first translation address after performing a page table read operation of steps N to 1 when the first address translation fails; A second step of storing a virtual address of steps N-1 to 2 of the first virtual address and a first valid bit indicating validity; A third step of storing a first page table pointer address generated during the first step; A fourth step of comparing the virtual address stored in the second step with the virtual address of steps N-1 to 2 of the second virtual address when the second address translation fails; And when the comparison result of the fourth step is the same, without performing page table read operation from page N to step 1, the first step page table pointer address and the first step page table pointer address of the second virtual address are immediately read. And a fifth step of generating a second translation address to complete the second translation failure process.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3 of the accompanying drawings.

2 conceptually illustrates a virtual address storage memory.

According to the method of reducing the delay time of the present invention, a storage memory for storing the address of a page table of a lower page in a multi-page structure using a page locality is designed. That is, in the case of N-level multi-page structure, the page size exists in N, N-1, .... 2, 1-level, and the 1st page because the lowest page, the 1st page size is considerably smaller than the 2nd page size. Even if it fails in address translation, if it finds the second level page that refers to the first level page that was just used, there is a high possibility that the first level page currently required exists. This is the locality of the page, and if it succeeds in performing one-step page conversion (TLB hit), it stores the second-level page address in the buffer. The stored address is used when the first stage page conversion fails. At this time, the processing delay time is expressed as the following equation (2).

Therefore, it can be seen that Equation (2) improves the address translation failure processing delay time by (N-1) dM compared to Equation (1).

FIG. 3 is a structural diagram of a hit failure processing apparatus of a virtual address translation apparatus having a multi-page structure according to the present invention, wherein a buffer 12 storing a virtual address representing a page of the lowest immediately preceding step and a multiprocessor are supported. A buffer 13 for storing the process number, a buffer 14 for storing the lowest page table pointer address, and a controller 11 for controlling the buffers 12, 13, and 14 according to the input virtual address.

Here, the buffers 12 and 13 have one bit valid bit in the least significant bit indicating the validity of the contents of each buffer. In addition, the controller 11 includes the following functions.

First, the function of comparing the input virtual address and the contents stored in the buffer (12).

Second, the valid bits of the buffers 12 and 13 are set to '0' when the process is replaced.

Third, a function of storing the buffer 12 up to two levels of the virtual address.

Fourth, the function stores the pointer address of the first-level page table in the buffer 14.

Fifth, the function of storing the process number in the buffer 13 when the process is replaced.

The failure failure processing method of the virtual address translation apparatus applied to the apparatus of the present invention configured as described above will be described in detail.

First, the process number currently being processed is stored in the buffer 13, and if a conversion failure of the address translator occurs, the failure process is performed in the same manner as in the conventional method (i.e., performing a page table read operation from step N to step 1). To generate a translation address). At this time, if the failure process is normally completed, the virtual address up to step 2 is stored in the buffer 12, and the page table pointer address of the step 1 is stored in the buffer 14. Subsequently, if a conversion failure occurs again, only two levels of the virtual addresses input from the microprocessor and stored in the virtual address memory are compared with the contents stored in the buffer 12. Here, when the comparison result shows that the address is the same and the valid bit of the buffer 12 is '1', the pointer address is read from the page table of the first stage stored immediately without going through the page table reading operation from the N stage to the second stage. come. On the other hand, if the comparison result does not match and the valid bit of the buffer 13 is '1', the page table read operation starts from step N-1. If the valid bit is '0', the process number is newly stored in the buffer 13. And the N page table read operation starts.

On the other hand, when the process number changes, all valid bits of the buffers 12 and 13 are set to '0'.

Therefore, when the present invention made as described above is used in a computer system using a virtual address translation apparatus having a multi-page structure in the virtual address memory management apparatus, the following system performance is improved.

Where A is the processing time from N to 1 step, B is the buffer 12 failure rate x buffer 13 hit rate x N-1, and one step processing time, C is the buffer 12 hit rate x 1 step processing time, D is Conversion success rate x conversion time, E represents conversion failure rate x failure processing time, respectively.

That is, the present invention has the effect of improving the performance of the system by reducing the address translation failure processing delay time of the virtual address translator having a multi-page structure mounted in the virtual address memory management device.

Claims (7)

In the hit failure processing apparatus of the virtual address translator having an N page structure for shortening the entire address translation failure processing time when the first and second address translation failures consecutive to the first virtual address and the second virtual address fail. First storage means for storing a process number when supporting a process; Second storage means for storing a virtual address of steps N-1 to 2 of the first virtual address; Third storage means for storing a first-stage page table pointer address generated during a process of failing the first address translation; And controlling the first to third storage means according to the input virtual address, and comparing the input virtual address with contents stored in the second storage means, when the process is replaced, the first and second storage means. A function of invalidating a valid bit of the second storage means; controlling to store up to page 2 of the first virtual address in the second storage means; and storing the first level page table pointer address in the third storage means. And a control means configured to have a function of controlling a function to store a process number in the first storage means when a process is replaced. The apparatus of claim 1, wherein the first and second storage means each store a valid bit indicating validity of stored contents. 3. The apparatus of claim 2, wherein the valid bit is stored in the least significant bit of the storage means. In the method of processing a hit failure of a virtual address translation apparatus having an N page structure for shortening the total address translation failure processing time when consecutive first and second address translation failures for the first virtual address and the second virtual address fail. A first step of completing a conversion failure process by performing a page table read operation from page N to step 1 when the first address translation fails, generating a first translation address, and registering it with the virtual address translation apparatus; A second step of storing a virtual address of steps N-1 to 2 of the first virtual address and a first valid bit indicating validity; A third step of storing a first page table pointer address generated during the first step; A fourth step of comparing the virtual address stored in the second step with the virtual address of steps N-1 to 2 of the second virtual address when the second address translation fails; And when the comparison result of the fourth step is the same, directly combining the first page page pointer address with the stored first step page table pointer address of the second virtual address without performing a page table read operation of steps N through 1 of the page. And a fifth step of completing the second conversion failure process by reading the last page table address in the first-level page table and registering it as the second translation address in the virtual address translation apparatus. How to handle hit failure of inverter. 5. The method of claim 4, further comprising storing a process number and a second valid bit indicating validity before the first step when supporting multiple processes. Way. 6. The method of claim 5, wherein if the comparison result of the fourth step does not match, the second valid bit is checked, and if the second valid bit is valid, the page table read operation is performed from the step N-1. If the second valid bit is not valid, the method further includes storing the process number and the second valid bit, and then performing a page table read operation from page N. A method for handling hit failure of a virtual address translator having a structure. 6. The method of claim 5, wherein if the process number is changed, both the first valid bit and the second valid bit are invalid.