JPH0553915A - Address converting device - Google Patents

Abstract

PURPOSE:To speedily extract an operand by accelerating address conversion in the case of converting an address to a physical address at the time of extracting the operand from a buffer memory circuit. CONSTITUTION:A logical address 106 is generated from various parameters 101-103 imparted by an instruction, the address is converted into a physical address 109 by a first address conversion buffer 15, and a buffer memory circuit 17 is made access. On the other hand, among the parameters applied by the instruction, a second address conversion buffer 21 is provided to be indexed by a base register number 101, an address comparator circuit 28 compares coincidence between a physical address 212 being the index output of this buffer 21 and the physical address 109 being the index output of the first address conversion buffer 15 and when those addresses are coincident, the buffer memory circuit 17 is immediately made access by using the physical address 212.

Description

Detailed Description of the Invention

[0000]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device, and more particularly to an information processing device using a virtual memory system in which a logical address of an operand is determined by a base address, an index value and a displacement, and this logical address is converted into a physical address. Address translation device in.

[0001]

2. Description of the Related Art In a conventional information processing apparatus, when a necessary operand is fetched from a buffer memory circuit, a logical address of the operand is determined by a base address, an index value and a displacement given by an instruction, and this logical address is converted by an address conversion buffer. Convert it to a physical address,
The buffer memory circuit is indexed by this physical address.

FIG. 2 is a block diagram showing an operand fetching method by such address conversion. Referring to FIG. 2, first, in the first cycle of instruction execution, the base register number 101 and the index register number 102 specified by the instruction
To the base register 12 and the index register 13, respectively, to obtain a base address 104 and an index value 105.

The 3-input adder 11 receives a base address 104, an index value 105 and a displacement 103 designated by an instruction, and inputs an output effective address 106 to a logical address register 14.

Then, in the second cycle, the upper bit 107 of the logical address register 14 is set to the address translation buffer 1
5, the physical page address 109 is output and input to the physical address register 16 together with the lower bit 108 of the logical address register 14.

In the third cycle, the output 110 of the physical address register 16 is given to the buffer memory circuit 17. If the operand data is present in the buffer memory, it is taken out immediately from the main memory device (not shown) if it is not present, and then the operand data 111 is taken out as the output of the buffer memory circuit 17, and the arithmetic processing unit (not shown). To be sent).

In such a conventional address translator, even if an operand exists in the buffer memory circuit,
Since at least 3 cycles are required before fetching, there is a drawback that the instruction execution efficiency is low.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an address translation device which enables instruction fetching by one cycle faster than the conventional operand fetching.

[0008]

According to the present invention, the base register is obtained by designating the base register by the base register number designated by the instruction, and the index register is designated by the index register number designated by the instruction. An addition unit that adds the index value and the displacement, a logical address register that stores the addition result,
A first part using the upper part of the logical address register as an input
First address translation buffer for outputting the physical page address of the
Of the physical address register for storing the physical page address of the logical address register and the lower part of the logical address register, and the buffer storage means is indexed by the output of the physical address register. , A second address translation buffer consisting of a physical address field and indexed by the base register number, and an index register number which is an index output of the second address translation buffer and an index register number designated by the instruction And a means for controlling the storage of the physical address, which is the index output of the second address translation buffer, and the lower output of the adding means when the comparison result shows a match in the physical address register. An address translation device characterized by .

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as in FIG. 2 are designated by the same reference numerals.

The second address translation buffer 21 has two compartments, each compartment including an index register number field, a physical address field and a valid bit indicating the validity of these fields. The buffer 21 is indexed with the base register number 101 designated by the instruction as an address.

The comparators 22 and 23 are provided for the respective compartments, and the hits of the corresponding compartments,
This is to judge a mishit. That is, the output of the index register number field for each compartment
203 and 206 are compared with the index register number 102 by comparators 22 and 23, respectively, and hit detection is performed.

The compartment determination circuit 24 compares the compartments for which a match is detected among the hit compartments, ie, the comparators 22 and 23, with the comparison results 207 and 20.
The hit selection is notified to the compartment selection circuit 25 (209).

The compartment selection circuit 25 notifies this
Upon receiving 209, one of the physical address fields 201 and 205, which is the index output of the compartment, whichever hits is selected to be the output 212.

The physical address selection circuit 26 uses the selected physical address 212 and the first address translation buffer 15
One of the physical addresses 109, which is the index output of, is selected (213) and stored in the upper bits of the physical address register 16.

The in-page address selection circuit 27 selects one of the lower bit 108 of the logical address register 14 and the lower bit of the addition output 106 of the adder 11 and stores it in the lower bit of the physical address register 16 (214).

The address comparison circuit 28 compares the storage address 110 of the physical address register 16 with the index output address 109 of the first address conversion buffer 15 and compares the result.
215 is sent to the address selection circuits 26 and 27 and the address conversion control circuit 30.

The address conversion control circuit 30 determines the result of this comparison.
The second address conversion buffer 21 and the buffer storage circuit 17 are controlled according to the reference numeral 215.

The operand fetching process according to this embodiment is as follows:
First, in the first cycle of instruction execution, the base register number 101 and the index register number 102 designated by the instruction are given to the base register 12 and the index register 13, respectively, to obtain a 32-bit base address 104 and a 32-bit index value 105. ..

The 3-input adder 11 has a base address 104, an index value 105, and a 12-bit displacement specified by an instruction.
103 is input, and the output 32-bit effective address 106 is input to the logical address register 14.

At the same time, using the base register number 101 as an address, the second address conversion buffer 21 consisting of two compartments is accessed. Output 203 of the index register number field of each compartment,
206 is the index register number 102 and the comparator 22,
The comparison results 207 and 208 are sent to the compartment determining circuit 24.

The compartment determination circuit 24 determines the comparison result.
207, 208 and valid bits 202, 2 in each compartment
From 05 and so on, the compartment selection instruction is sent to the compartment selection circuit 25 so that the compartment where the valid bit indicates “valid” and the comparison result matches.
Send 209.

Compartment selection circuit 25 follows compartment # 0, compartment # 0, according to compartment selection instruction 209.
One of the physical address fields 201 and 204 of 1 is selected and sent to the physical address selection circuit 26 as the second physical page address 212.

In response to the signal 211 indicating the first cycle of instruction execution, the physical address selection circuit 26 and the in-page address selection circuit 27 cause the second physical page address 212, respectively.
The lower 12 bits of the output 106 of the 3-input adder 11 are selected and given to the physical address register 16.

Subsequently, in the second cycle, the upper 20 bits 107 of the logical address register 14 are supplied to the first address translation buffer 15 to make the first physical page address 10
Output 9

The address comparison circuit 28 compares the second physical page address, which is the output 110 of the physical address register 16, with the above-mentioned first physical page address 109, and outputs the comparison result 215 to the physical address selection circuit 26, page. It is given to the internal address selection circuit 27 and the address conversion control circuit 30. If the comparison result 215 indicates a match, the physical address selection circuit 26 and the in-page address selection circuit 27
Second physical page address 212 and 3-input adder 11 respectively
The lower 12 bits of the output 106 are still selected, and the address conversion control circuit 30 gives a data read request 216 to the buffer memory circuit 17.

Therefore, if the operand data is present in the buffer memory, immediately, if it is not present, it is taken out from the main memory device (not shown) and then the operand data 111 is taken out as the output of the buffer memory circuit 17. ..

If the comparison result 215 indicates a mismatch, the physical address selection circuit 26 and the in-page address selection circuit 27 select the first physical page address 109 and the lower 12 bits 108 of the logical address register 14, respectively. Then, it is stored in the physical address register 16.

In the second address translation buffer 21,
The index register number field, the physical address field, and the valid bit of the compartment specified by the compartment determination circuit at the address determined by the base register number 101 are set to the index register number 102, respectively.
, The first physical page address 109 and the valid state are stored, the address translation control circuit 30 instructs the second address translation buffer 21 to update the second address translation buffer 21.
Give seven

Then, in the third cycle, the buffer memory circuit 17
A data read request 216 is given to. Therefore, if the operand data exists in the buffer memory, immediately, if it does not exist, it is taken out from the main memory device and then the buffer memory circuit 17
The operand data 111 is taken out as the output of.

[0031]

As described above, according to the present invention, by providing the second address translation buffer that can be searched by the value of the base register number designated by the instruction, the physical page of the operand data is stored in the second address translation buffer. If the address is stored, the operand data can be fetched in the second cycle of instruction execution, which is one cycle earlier than the conventional one, so that there is an effect that the instruction execution efficiency is higher than the conventional one on average.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional address translation device.

[Explanation of symbols]

 11 adder 12 base register 13 index register 14 logical address register 15 first address conversion buffer 16 physical address register 17 buffer memory circuit 21 second address conversion circuit 22, 23 comparison circuit 24 compartment determination circuit 25 compartment selection circuit 26 address Comparison circuit 30 Address conversion control circuit

Claims (1)

[Claims] 1. A base address obtained by designating a base register by a base register number designated by an instruction, an index value obtained by designating an index register by an index register number designated by the instruction, and a displacement. Of the address conversion buffer, a logical address register for storing the result of the addition, a first address translation buffer for outputting a first physical page address with the upper part of the logical address register as an input, and an address translation buffer for the address translation buffer. An address translation device including a physical address register for storing a first physical page address which is an output and a lower part of the logical address register, wherein the buffer storage means is indexed by the output of the physical address register. , Index register number field, physical address A second address translation buffer consisting of a field and indexed by the base register number, and comparing the index register number, which is the index output of the second address translation buffer, with the index register number specified by the instruction. Means for controlling storage of the physical address, which is the index output of the second address translation buffer, and the lower output of the adding means when the comparison result shows a match in the physical address register. Address translation device.