JPH0481928A - Information processor - Google Patents

Abstract

PURPOSE:To improve the execution efficiency of an instruction by storing in advance an operand address of an instruction executed in the past in an operand address matrix, so that an operand address calculation stage, a cache access stage, an address conversion stage and an arithmetic stage can be executed simultaneously. CONSTITUTION:The processor has stages of an instruction fetch and a cache access, and adopts a virtual storage system. In such a state, at every execution of an instruction, in an instruction address matrix 30 and an operand address matrix 31, its instruction address and operand address are registered, and subsequently, at the time of executing its instruction, the address stored in these matrixes 30, 31 are used. Accordingly, an operand address calculation stage, a cache access stage, and also, an address conversion stage and an arithmetic stage can be executed simultaneously, respectively. In such a way, the execution efficiency of an instruction is improved.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to an information processing device, and particularly relates to an information processing device that employs a virtual memory method and has each stage of instruction fetching, operand address calculation, address translation, cache access, and operation. be.

BACKGROUND OF THE INVENTION A command processing process in a conventional information processing device will be described with reference to the drawings. As shown in FIG. 2, in the instruction fetching stage, the instruction fetching circuit 11 uses the instruction address register 10
The instruction word 102 is taken out by the output 1 (11) and stored in the instruction register 14. At the same time, the instruction word length generation circuit 12 generates the instruction word length 103 from the instruction word 102, and the instruction address update circuit 13 generates the instruction word length 103 from the instruction word 102. An update address 104 is generated from the length 103 and the output lot of the instruction address register 10, and is stored in the instruction address register 10.

In the operand address calculation stage, instruction register 1
output 106 of general-purpose register 15 designated as address calculation input by output 105 of instruction register 1
0 output 105 and the operand address calculation circuit 16
and the result 108 is given to logical address register 1
7 is stored. At the same time, the output 10 of the instruction register 14
5, the output 107 of the general-purpose register 15 specified as the first operand is assigned to the first address translation stage.
It is stored in the operand register 19.

In the address translation stage, the logical address register 17
The output 109 of is converted into a physical address 110 by the address conversion circuit 18 and stored in the physical address register 20. At the same time, the output 111 of the first operand register 19 of the address translation stage is stored in the first operand register 52 of the cache access stage.

In the cache access stage, the output 112 of the physical address register 20 is given to the cache circuit 21 and stored as second operand data 113 in the second operand register 23 . At the same time, the output 114 of the first operand register 52 of the cache access stage
is stored in the first operand register 54.

In the calculation stage, the calculation circuit 25 performs calculations on the output 11B of the first operand register 54 and the output 115 of the second operand register 23, and the result 117 is
is stored in the general-purpose register 15.

This type of information processing device requires five stages to process one instruction: instruction fetch, operand address calculation, address conversion, cache access, and operation, and because the instructions are executed sequentially, the instruction execution efficiency is low. There is.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can improve instruction execution efficiency.

According to the present invention, there is provided an information processing apparatus that has an instruction fetching stage and a cache access stage and employs a virtual memory method, and in the instruction fetching stage, an instruction address matrix storage means indexed by an instruction address; , operand address matrix storage means indexed by the instruction address, and comparison means for comparing the instruction address and the instruction address from the instruction address matrix storage means;
If it is determined that the next instruction address to be executed is registered in the instruction address matrix storage means as a result of the comparison by the comparison means, the physical page address information from the operand address matrix storage means is used for address generation. operand address generation means for generating an operand address of an instruction to be executed next from register information and displacement information indicated by the instruction word of the instruction fetching stage;
There is obtained an information processing device characterized in that it includes means for starting the operation of the cache access stage with the address generated by the operand address generation means.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an instruction address register 10 for storing an instruction address, an instruction fetch circuit 11 for fetching an instruction according to an address 101 of this register 10, and an instruction fetching circuit 11 for fetching an instruction according to an address 101 of this register 10. Based on the instruction word 102 from the circuit 11, the instruction word length is 10.
3, an instruction address update circuit 13 that generates an update address 104 based on the instruction word length 103 from this circuit 12 and the address from the register 10 and sends it to the instruction address register 10, and an instruction address register. Instruction address matrix memory 30 for reading two compartments in parallel with ten lower outputs 202
, two comparison circuits 32 and 33 which compare the outputs 203 and 204 from this memory 30 with the upper output 201 of the register 10, and which compartment of the memory 30 is selected based on the comparison results 205 and 20B of these circuits 32 and 33. It determines whether an instruction to be executed next is registered or not, and outputs a controller selection signal 207 to select the compartment of the operand address matrix memory 31 corresponding to the registered compartment. 2 from the position specified by the hit determination circuit 34 and the lower output of the instruction address register 10.
an operand address matrix memory 31 outputting two compartments, and an output 208 from this memory 31;
and 209, the first selection circuit 35 selects one of them using a selection signal 207.

One of the features of one embodiment of the present invention is that the operand address calculation stage and the cache access stage are executed in parallel.

These stages include general purpose registers 15 which output an output 215 by the general purpose register field 21Q in the output of the first selection circuit 35, and outputs 21 of these registers 15.
5 and an intra-page address calculation circuit 60 that generates an intra-page address 21B from the displacement field in the instruction word 102 output by the circuit 11, and an address 2 from this circuit 60.
1G, the output 214 of the first selection circuit 35, and the output 110 of the address conversion circuit 18, based on the output 213 of the physical address comparison circuit 38.
6. A physical address register 20 that stores the output 211 of this second selection circuit 36. Cache circuit 2 accessed by physical address 112 from this register 20
1. An instruction register 14 that stores the instruction word 102 from the instruction fetch circuit 11; an operand address that generates an operand address from the output 106 given from the general-purpose register 15 and the output 105 of the register 14 according to the output from the instruction register 14; A calculation circuit 16, a logical address register 17 that stores the operand address 108 generated by this circuit 16, a cache access stage instruction register 62 that stores the output 21g of the address translation stage instruction register 61, and an instruction address register 10.
an operand address calculation stage instruction address register 63 that stores the upper output 201 of
, and a cache access stage instruction address register 65 that stores the output 221 of this register 64 .

Another feature of an embodiment of the present invention is that operations are performed in parallel in the address translation stage and the calculation stage.

These stages include an address translation stage physical address register 37 that stores the physical address 112 from register 12, and a logical address 109 from register 17.
address conversion circuit 18 that converts the address into a physical address 110
, a physical address conversion circuit 38 that compares the physical address 110 from this circuit 18 and a physical address 212 from the register 37, a p flip-flop (F/F) 39 that stores the comparison result 218 of this circuit 38, and a An address translation stage first operand register 19 that stores the first operand 107 outputted from the general-purpose register 15 by the output 105, a second operand register 23 that stores the second operand 11B from the cache circuit 21, and from these registers 19 and 23; 1st of
and an arithmetic circuit 25 that performs an operation based on second operands 11 and 115, and an address translation stage instruction register 61 that stores the output 105 of the instruction register 14.

Next, the operation of one embodiment of the present invention will be described in detail with reference to FIG.

Referring to FIG. 1, in the instruction fetching stage of the instruction processing process according to an embodiment of the present invention, the instruction fetching circuit 11 uses the output lO1 of the instruction address register 10 to
2 and stores it in the instruction register 14. At the same time, from the instruction word 102, the instruction word length generation circuit 12 generates an instruction word length of 1
03 is generated, and the instruction word address update circuit 13 generates an update address 104 from the instruction word length 103 and the output 101 of the instruction address register 10, and stores it in the instruction address register 10.

The upper output 201 of the instruction address register 10 is stored in the instruction address register 63 of the operand address calculation stage.

Further, the lower output 202 of the instruction address register 10 is provided to the instruction address matrix memory 30 and the operand address matrix memory 31. The comparator circuits 32 and 33 compare the outputs 203, 20 of the two compartments of the instruction address matrix memory 30, indicated by a given address.
4 are compared with the upper output 201 of the instruction address register 10, and comparison results 205 and 206 are provided to the hit determination circuit 34.

This hit determination circuit 34 is connected to the instruction address matrix memory 3.
The compartment selection signal 207 is first set to determine in which compartment of 0 the instruction to be executed next is registered, and to select the compartment of the operand address matrix that corresponds to the registered compartment. is sent to the selection circuit 35. This first selection circuit 35 selects two compartment outputs 208 and 209 of the operand address matrix memory 31 according to the compartment selection signal 207.

The intra-page address calculation circuit 60 is connected to the first selection circuit 35
An intra-page address 216 is obtained from the general-purpose register output 215 specified by the general-purpose register field 210 being outputted by the general-purpose register output 215 and the displacement field in the instruction word 102 output by the instruction fetch circuit 11.

The intra-page address 21B is combined with the physical page address field 214 being output from the first selection circuit 35,
The signal is sent to the second selection circuit 36. Then, the second selection circuit 36 selects this combined address and stores it in the physical address register 20.

In the operand address calculation stage, instruction register 1
4, the output 106 of the general-purpose register 15 specified as the address calculation input and the output 105 of the instruction register 14 are output to the operand address calculation circuit 1.
6, and the result 108 is stored in the logical address register 17.

At the same time, the output 105 of the instruction register 14 causes the first
Output 1 of general-purpose register 15 specified as operand
07 is stored in the first operand register 19 of the address translation stage.

Further, the output 220 of the instruction address register 63 of the operand address calculation stage is stored in the instruction address register 64 of the address translation stage.

Furthermore, the output 112 of the physical address register 20 is given to the cache circuit 21, and the second operand data 1
1B and is stored in the second operand register 23. The output 112 of the physical address register 20 is also stored in the physical address register 37 of the address translation stage.

Also, the instruction address register 6 of the address translation stage
The output 221 of 4 is stored in the instruction address register 65 of the cache access stage.

In the address translation stage, the logical address register 17
The output 109 of is converted into a physical address 110 by the address conversion circuit 18. Physical address conversion circuit 38
compares the physical address 110 with the output 212 of the physical address register 37 of the address translation stage, and outputs a comparison result 213. If the comparison result 218 indicates a match, the general-purpose register 15 stores the operation result 117 of the output 111 of the first operand register 19 of the address translation stage and the output 115 of the second operand register 23, and processes one instruction. ends.

If a mismatch is indicated, the update operations of the instruction address register 10, instruction register 14, general-purpose register 15, and logical address register 17 are all inhibited, and
The second selection circuit 36 selects the physical address 110 as its output 211 and stores it in the physical address register 20. Further, the comparison result 213 is stored in the D type flip-flop 39.

Then, in the next cycle, the output 112 of the physical address register 20 is given to the cache circuit 21 and stored in the second operand register 23 as the second operand data 113.
The output 112 of is stored in the physical address register 37 of the address translation stage. In addition, the output of the D type flip-flop 39 causes the operand address matrix 31
The physical page address in the output 112 of the physical 1 address register 20 and the address calculation register number and displacement in the output 219 of the cache access stage instruction register 52 are stored. At the same time, the output 222 of the instruction address register 65 of the capture access stage is stored in the instruction address matrix 30.

Furthermore, in the next cycle, the address conversion stage is performed again, and this time, the output 213 of the physical address comparison circuit 38 indicates a match, so the instruction processing is completed.

By doing this, each time an instruction is executed, the instruction address and operand address will be registered in the instruction address matrix 30 and operand address matrix 31, so the next time the instruction is executed, these will be stored in the matrix. You can use the address you have. In that case,
It becomes possible to simultaneously execute the operand address calculation stage and the cache access stage, as well as the address translation stage and the calculation stage.

Note that the physical address comparison circuit 38 compares the physical address 112 of the physical address register 20 and the physical address 110 of the address conversion circuit 18 to find a match, because the contents of the general-purpose register 15 are rewritten, etc. Second
The combined address (21
4 and 216) is invalid.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention stores the operand addresses of instructions that have been executed in the past in an operand address matrix, so that the operand address calculation stage, the cache access stage, the address translation stage, and the calculation stage This has the effect of making the execution efficiency of instructions higher on average than before.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional information processing apparatus. Explanation of symbols of main parts 10...Instruction address register 11...
- Instruction fetch circuit 12...Instruction word length generation circuit 13...Instruction address update circuit 14...
・Instruction register 15...General-purpose register 16...Operand address calculation circuit 17...
...Logical address register 18...Address translation circuit 19...First operand register 20 of address translation stage...Physical address register 21...
- Cache circuit 23... Second operand register 25...
...Arithmetic circuit 30...Instruction address matrix 31...Operand address matrix 32, 33...
... Comparison circuit 34 ... Hit judgment circuit 35 ... First selection circuit 36 ... Second selection circuit 37 ... Address conversion stage Physical address register 38...Physical address comparison circuit 60...
- In-page address calculation circuit 61...Address translation stage instruction register 62...Cache access stage instruction register

Claims (1)

[Claims] (1) An information processing device that employs a virtual memory system and has an instruction fetching and cache access stage, wherein the instruction fetching stage includes an instruction address matrix storage means indexed by an instruction address; operand address matrix storage means,
Comparing means for comparing the instruction address and the instruction address from the instruction address matrix storage means, and determining that the instruction address to be executed next is registered in the instruction address matrix storage means based on the comparison result of the comparison means. an operand that generates the operand address of the next instruction to be executed from the physical page address information from the operand address matrix storage means, the register information used for address generation, and the displacement information indicated by the instruction word of the instruction fetching stage. An information processing device comprising: address generation means; and means for starting the operation of the cache access stage with the address generated by the operand address generation means.