JP2560520B2 - Advance control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a virtual memory space and having a pipeline configuration for prefetching instructions, and in particular, to instructions at a branch destination of a relative branch instruction at high speed. The present invention relates to a preceding control device that can be preempted.

[Conventional technology]

Conventionally, when the preceding control device of this type fetches an instruction of a branch destination of a relative branch instruction, after adding the branch displacement of the above instruction to the logical address of the relative branch instruction to obtain the logical address of the branch destination, Absolute address translation is performed, and the branch destination instruction is fetched based on the absolute address obtained by absolute address translation. In addition to this, the absolute address of the branch destination obtained when the relative branch instruction was executed last time is stored in a storage means such as a table, and when the instruction is executed again, it is stored in the storage means. A device has also been proposed in which the absolute address of the branch destination instruction is used as the absolute address.

[Problems to be Solved by the Invention]

Among the above-mentioned conventional techniques, the former requires absolute address translation after determining the logical address of the branch destination, so it takes several cycles to obtain the absolute address, and it takes time to fetch the next instruction. There was a problem.
Also, the latter can obtain the absolute address of the branch destination in the next cycle, so the processing speed can be increased as compared with the former, but a table or the like for storing the absolute address of the branch destination can be used. There is a problem in that the amount of hardware is scarce because a storage means is required.

An object of the present invention is to enable a branch destination instruction of a relative branch instruction to be fetched at high speed with a small amount of hardware.

[Means for solving the problem]

In order to achieve the above object, the present invention has a virtual memory space, and in a preceding control device used in an information processing device of a pipeline structure for prefetching an instruction, is the prefetched instruction a relative branch instruction? First determining means for determining whether or not the prefetched instruction is a relative branch instruction by the first determining means, so that the in-page element of the absolute address of the prefetched relative branch instruction itself And an addition means for adding the branch displacement of the prefetched relative branch instruction, and a branch destination instruction of the prefetched relative branch instruction based on the addition result of the addition means in the same page as the prefetched relative branch instruction. Second determining means for determining whether or not the prefetched relative branch instruction itself is determined by the second determining means. Absolute based address page head address of the addition result and the address of concatenating said adding means is provided with a an instruction fetch means for fetching of the next instruction.

[Work]

Whether or not the prefetched instruction is a relative branch instruction is determined by the first determining means. When the instruction prefetched by the first determining means is determined to be a relative branch instruction, the in-page element of the absolute address of the relative branch instruction itself prefetched by the adding means and the branch displacement of the relative branch instruction are added. To be done. The second determination means determines whether or not the branch destination of the relative branch instruction is on the same page as the relative branch instruction based on the addition result of the addition means, and the second determination means determines whether the branch destination and the relative branch instruction are present. When it is determined that the instruction exists in the same page, the instruction fetching unit fetches the next instruction based on the address obtained by concatenating the page start address of the absolute address of the relative branch instruction itself and the addition result of the adding unit.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. For convenience of explanation, the information processing apparatus to which the preceding control apparatus of this embodiment is applied has an absolute address of 32 bits for fetching an instruction, a page size of 4 Kbytes, and an instruction word length of 1 byte.
It is 32 bits (4 bytes), and the instructions are 4 in main memory.
It is assumed to be aligned in bytes. Further, when a branch instruction is fetched, the next instruction is fetched uniformly, and if the branch instruction is executed and the branch is unsuccessful, the preceding control is canceled and the instruction is fetched again. Is adopted.

Now, as shown in FIG. 1, the advance control apparatus of the present embodiment has an instruction cache (IC) 1 in which a copy of a main memory (not shown) in which instructions are stored and an instruction fetch And an instruction address register (IAR) 2 in which the absolute address is set. Here, in the simplest configuration, the instruction cache 1 has a one-compartment configuration and is indexed by the address stored in the instruction address register 2. An instruction register (IR) 3 in which an instruction is set, an instruction fetch address 5 from an external unit (not shown), an address in the instruction address register 2 plus "4" corresponding to the instruction word length 6, a selector 4 for selecting one of the addresses 7 connecting the upper 20 bits of the instruction address register 2 and the addition result of the adder 9, and whether the instruction set in the instruction register 3 is a branch instruction If it is a branch instruction, it is further judged whether it is a relative branch instruction and an adder 9
A select signal generating circuit 10 for generating a select signal for controlling the selector 4 based on the judgment result of the decoder 8, the sign bit 14 and the carry signal 11 of the adder 9, and the lower 12 bits of the instruction address register 2 are set. In-page address register (PAR) 12 is provided.

 Next, the operation of this embodiment will be described.

At the time of initialization, the instruction start address is set in the instruction address register 2 as the instruction fetch address 5 from the outside through the selector 4. After that, the instruction is fetched by indexing the instruction cache 1 with the address set in the instruction address register 2, and the read instruction is set in the instruction register 3. Instruction register 3
When the instruction is set to, the decoder 8 determines whether or not the set instruction is a branch instruction, and when it is determined to be a branch instruction, it is further determined whether or not it is a relative branch instruction. The result is added to the select signal generation circuit 10.

When the decoder 8 determines that the instruction is not a branch instruction, the select signal generation circuit 10 adds a select signal for selecting the address 6 to the selector 4. As a result, "4" is added to the address currently set in the instruction address register 2.
Is added to set the address, and the next instruction is fetched. After that, the above operation is repeated until the fetched instruction is determined to be a branch instruction by the decoder 8.

When the decoder 8 determines that the instruction is a branch instruction but not a relative branch instruction, the select signal generation circuit 10 adds a select signal for selecting the instruction fetch address 5 to the selector 4. As a result, the absolute address of the branch destination generated by the external unit (not shown) is set in the instruction address register 2, and the instruction of the branch destination is fetched from the instruction cache 1.

Next, the instruction set in the instruction register 3 is transferred to the decoder 8
The operation when it is determined to be a relative branch instruction will be described.

The logical address of the branch destination of the relative branch instruction is the displacement part in the instruction for the logical address in which the relative branch instruction was stored (lower 12 bits in this embodiment)
Relative to. Here, as is well known, the lower 12 bits of a logical address, that is, an address within a 4 Kbyte page is equal to that of an absolute address. Therefore, if the branch destination address is on the same page as the page from which the relative branch instruction is fetched, the 20 bits above the absolute address of the branch destination, that is, the top address of the page is the page from which the relative branch instruction was fetched. The lower 12 bits, that is, the in-page address can be obtained by adding the in-page address from which the relative branch instruction is taken out and the displacement part in the instruction.
The present invention focuses on this point.

When a relative branch instruction is set in the instruction register 3, the decoder 8 adds a determination result indicating that the set instruction is a relative branch instruction to the select signal generation circuit 10.

Further, by setting the relative branch instruction in the instruction register 3, the adder 9 obtains the in-page address of the branch destination. The adder 9 is an in-page address register 12
And the contents of the lower 12 bits 13 of the instruction register 3 and the sign bit 14 are input, and if the sign bit 14 is "0", that is, the branch displacement is positive, the contents of the in-page address register 12 and the instruction Lower 12 bits of register 3
When the carry signal 11 is set to "1" by adding the contents of 13 and carrying occurs, and the sign bit 14 is "1", that is, when the branch displacement is negative, the contents of the in-page address register 12 Lower 12 bits of instruction register 3
The carry signal 11 is set to "0" by subtracting the contents of 13 and borrowing. Here, when a relative branch instruction is set in the instruction register 3, the contents of the in-page address register 12 are the in-page address from which the relative branch instruction is fetched, and the lower 12 bits 13 of the instruction register 3 are the branch displacement, Since the sign bit 14 indicates whether the branch displacement is positive or negative, the addition result of the adder 9 indicates the in-page address of the branch destination.

When the decoder 8 determines that the instruction set in the instruction register 3 is a relative branch instruction, the select signal generation circuit 10 performs the following processing based on the carry signal 11 and the sign bit 14 of the adder 9.

Here, there are the following four combinations of the carry signal 11 and the sign bit 14 (a) to (d).

(A) Sign bit 14 and carry signal 11 are both "0" (b) Sign bit 14 is "0" and carry signal 11 is "1" (c) Sign bit 14 and carry signal 11 are both "1" ( d) Sign bit 14 is "1" and carry signal 11 is "0". Among the above four combinations, (a) and (d) are relative branch instructions and branch destinations in the same page.
Sign bits 14 when (b) and (c) are not on the same page
And carry signal 11.

Therefore, when the combination of the sign bit 14 and the carry signal 11 is (b) or (c), that is, when the relative branch instruction and the branch destination are not on the same page, the absolute address conversion result by the external unit is used as the instruction address. Since it is necessary to set it in the register 2, the select signal generation circuit 10 adds a select signal for selecting the instruction fetch address 5 to the selector 4. As a result, the absolute address translation result by the external unit is set in the instruction address register 2,
The next command is fetched.

When the combination of the sign bit 14 and the carry signal 11 is (a) or (d), that is, when the relative branch instruction and the branch destination are on the same page, the start address of the branch destination is the relative branch instruction. Since the top address of the fetched page, that is, the upper 20 bits of the instruction register, and the in-page address are the addition result of the adder 9, the selector 4 is supplied with a select signal for selecting the relative branch destination address 7 connecting them. Add. As a result, the relative branch destination address 7 connecting the top address of the page and the in-page address is set in the instruction address register 2, and the next instruction is fetched.

〔The invention's effect〕

As described above, according to the present invention, when a relative branch instruction and its branch destination exist on the same page, the displacement result of the relative branch instruction and the addition result of the relative branch instruction itself and the in-page element of the absolute address of the relative branch instruction, The next instruction is fetched based on the address obtained by concatenating the absolute start address of the relative branch instruction and the page start address, and the probability that the relative branch instruction and the branch destination will be different pages is Since it is rare, the relative branch instruction can be prefetched at a higher speed than in the conventional apparatus that always waits for the absolute address conversion result. Also, since the branch destination address of the relative branch instruction is dynamically calculated and calculated, the amount of hardware for storage is reduced compared to the conventional device that stores the absolute address of the branch destination when the previous relative branch instruction was executed. There is also an effect that it can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 1 ... Instruction cache, 2 ... Instruction address register, 3 ... Instruction register, 4 ... Selector, 8
...... Decoder, 9 ... Adder, 10 ... Select signal generation circuit, 12 ... In-page address register.

Claims (3)

(57) [Claims] 1. A preceding control device used in an information processing device having a pipeline structure having a virtual memory space for prefetching an instruction, determines whether or not the prefetched instruction is a relative branch instruction. First determining means, and by the first determining means determining that the prefetched instruction is a relative branch instruction, the prefetched relative branch instruction itself has an absolute address within a page element and the prefetched relative instruction. Addition means for adding the branch displacement of the branch instruction, and whether the branch destination instruction of the prefetched relative branch instruction is on the same page as the prefetched relative branch instruction based on the addition result of the addition means. And a page of the absolute address of the prefetched relative branch instruction itself when it is judged by the second judgment means that it is in the same page. A preceding control device comprising: an instruction fetching means for fetching a next instruction based on an address obtained by concatenating the start address and the addition result of the adding means. 2. The second judgment means, when the branch displacement has a positive value, a carry occurs in the addition result of the addition means, whereby the prefetched relative branch instruction and the branch of the relative branch instruction. The preceding control device according to claim 1, wherein it is determined that the previous instruction is not within the same page. 3. The second judgment means, when the branch displacement has a negative value, a borrow occurs in the addition result of the addition means, whereby the prefetched relative branch instruction and the branch of the relative branch instruction. The preceding control device according to claim 1, wherein it is determined that the previous instruction is not within the same page.