JPH05143330A - Stack cache and control system thereof - Google Patents

Abstract

PURPOSE:To shorten time necessary for a PUSH/POP instruction and to prevent a cache from storing invalid data for popped software. CONSTITUTION:In order to hold the combinations of addresses and data at the time of pushing a microcomputer 3, automatically push unpushed held data to a main memory 4 during the idle time of a bus cycle, output the data concerned to the microcomputer 3 at the time of popping the microcomputer 3, and substitute valid data for unnecessary data by automatic popping from the main memory 4 during the idle time of the bus cycle, a stack cache 20 is provided with a cache 10 having a means indicating whether respective data have been written in the main memory 4 or not, an active controller having a vertex pointer for an intra-cache stack, a bottom pointer for the intra-cache stack and a vertex pointer for cache outside stack and a bus control part 11 for arbitrating the external accesses of the microcomputer 3 and the active controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system for processing data, and more particularly to a stack in a microcomputer system that supports a stack structure in which the last input data is first output as a data structure on the main memory. It's about cache.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional microcomputer system (hereinafter referred to as a microcomputer system) having no cache, in which 1 is a stack pointer (hereinafter abbreviated as SP) and 2 is 8 bits. Incrementer / decrementer (hereinafter abbreviated as ID8B), 3 is SP
1 and a microcomputer including the ID8B2 (hereinafter abbreviated as a microcomputer), 4 is a main memory. FIG. 4 is a memory map showing the operation of the conventional microcomputer system having no cache. FIG. 5 is a block diagram showing a configuration of a conventional microcomputer system having a cache. In FIG. 5, 1-4 are the same as those in FIG. 3, 5 is a selector, 6 is a data section, 7 is a tag section, and 8 is data. V is valid
Bit 9 is a comparator. Also, 10 is the selector 5,
A cache composed of a data unit 6, a tag unit 7, a V bit 8, and a comparator 9, and 11 is a bus control unit. Figure 6
Is a memory map showing the operation of the conventional microcomputer system having a cache. The contents of each component in FIGS. 3 and 5 will be described in the following operation description.

The operation of the conventional microcomputer system of FIG. 3 having no cache will be described with reference to FIG. As a data structure on the main memory 4, the microcomputer 3 supports a stack structure in which the last input data is output first, and the data input to the stack is PUSH (push),
Data output from the stack as POP (pop)
Differentiate from other data writing / reading. In FIG. 4A, the microcomputer 3 pushes to the stack area of the main memory 4. In FIG. 4B, the microcomputer 3 pops from the stack area of the main memory 4. Here, the data on the main memory 4 POPed to the microcomputer 3 remains as a value, but the value is not read out again and used in terms of software. On the other hand, the PUSHed data in the stack is used by the microcomputer 3 as a read / write target other than the "stack POP operation" before being POPped.

Referring to FIG. 3, data is PUS
At the time of H, the microcomputer 3 decrements (-1) the value of SP1 indicating the top of the current stack with ID8B2, and writes it to the main memory 4 using that value as an address. As a result, the data is written to the new top of the stack on main memory 4. When popping the data, the microcomputer 3 reads from the main memory 4 using the value of SP1 indicating the top of the current stack as an address and sets SP1 as an ID.
Increment (+1) at 8B2. As a result, the data is taken from the top of the stack in main memory 4 and SP1
Indicates the address of the new one lower stack vertex.

Next, the operation of the conventional microcomputer system of FIG. 5 having a cache will be described with reference to FIG. Figure 6 (a)
Then, the microcomputer 3 pushes the data to the stack area of the main memory 4. At this time, a set of data and a corresponding address is also registered in the cache 10 at the same time. In FIG. 6B, the microcomputer 3 pops the data from the stack in the cache 10. Since the relevant data is registered in the cache 10, the data is read from the cache 10. As mentioned above, (cache 1
The data (in 0) remains as a value, but the value is not read and used again in terms of software. However, cache 1 in this conventional example
Within 0, the data is treated as valid data. Figure 6
In (c), if a large amount of other data is registered in the cache 10 after the PUSHed data is registered in the cache 10, the PUSHed data in the cache 10 is overwritten with the other data. At this time, since the corresponding data is not registered in the cache 10, the POP data is read from the main memory 4. The data read from the main memory 4 is simultaneously registered in the cache 10. As mentioned above, (cache 10
The data (which has been newly re-registered in) remains as a value, but the value is not read again and used by software. However, in the cache 10, the data is treated as valid data.

Referring to FIG. 5, data is PUS
At the time of H, the microcomputer 3 decrements (-1) the value of SP1 indicating the top of the current stack with ID8B2, and writes the value as an address. Actually, at this time, the bus control unit 11 writes the data to the cache 10 and the new vertex of the stack on the main memory 4. For example, the operation in the cache 10 when the address is an 8-bit binary number "01010101" and the data is an 8-bit binary number "11101110" will be described. When the cache 10 has a structure of 8 entries as shown in FIG. 5, the lower 3 bits “101” of the address are given to the selector 5, and the selector 5 has the tag portion 7, V bit 8 and “101” of the data portion 6.
Select the part corresponding to. The “101” corresponding part of the tag part 7 records the upper 5 bits “01010” of the address, the “101” corresponding part of the V bit 8 records “1”, and the “101” corresponding part of the data part 6 records the data. "111
"01110" is recorded.

When POP data, the microcomputer 3 reads the value of SP1 indicating the top of the current stack as an address, and increments (+1) SP1 by ID8B2. Here, the case where the corresponding data is registered in the cache 10 as shown in FIG. 6B will be described first. 8-bit 2 as a read address from the microcomputer 3
When the decimal number "01010101" is output, the bus control unit 11 first notifies the cache 10 of the address. The lower 3 bits "101" of the address are given to the selector 5 inside the cache 10, and the selector 5 selects the portion corresponding to "101" in the tag portion 7, the V bit 8 and the data portion 6. The portion corresponding to "101" of the tag portion 7 outputs the upper 5 bits "01010" of the recorded address to the comparator 9, and the comparator 9 outputs the upper 5 bits "01010" of the input address and the recorded address. Top 5 of
The bit “01010” is compared to notify that they match. The portion corresponding to "101" of the V bit 8 outputs "1", indicating that the corresponding data in the cache 10 is valid. Since the coincidence of the address and the validity of the corresponding data are shown, the portion corresponding to "101" of the data portion 6 is the data "11".
"101110" is output to the microcomputer 3.

Next, the case where the previously PUSHed data is overwritten by another data as shown in FIG. 6C will be described. 8-bit 2 as a read address from the microcomputer 3
When the decimal number "01010101" is output, the lower 3 bits "101" of the address are given to the selector 5 inside the cache 10, and the selector 5 corresponds to "101" of the tag section 7, V bit 8 and data section 6. Select a part. The portion corresponding to “101” of the tag unit 7 outputs the upper 5 bits “XXXXXXX” of the address of the other overwritten data to the comparator 9, and the comparator 9 outputs the upper 5 bits “01” of the input address.
010 ”is compared with the upper 5 bits“ XXXXXXX ”of the recorded address to notify that they do not match. The portion corresponding to "101" of the V bit 8 outputs "1", indicating that the corresponding data in the cache 10 is valid. Since the address mismatch is indicated, the data corresponding to "101" in the data portion 6 does not output the data. When the cache controller 10 indicates that the addresses do not match, the bus controller 11 reads out the data at the corresponding address from the main memory 4 and supplies it to the microcomputer 3 and the cache 10. The microcomputer 3 completes the reading, and the cache 10 performs the same registering operation of the address and data as described above.

When the data in the main memory 4 is rewritten by means (not shown) other than the microcomputer 3,
Since the data in the main memory 4 and the data in the cache 10 cannot be matched with each other, the V bit 8 of the rewritten corresponding address, or all the V bits 8 are set to "0" by means not shown. Immediately after starting the microcomputer system, all V bits 8 are "0". If the V bit 8 is "0", the same operation as when the addresses do not match at the time of reading is performed.

[0010]

P for manipulating a stack
The USH and POP instructions are used for saving data when the flow of processing such as a subroutine or interrupt processing routine is changed, and the data on the stack is also used for passing data between old and new routines. However, in the conventional microcomputer system having no cache, the microcomputer itself needs to access the main memory every time a PUSH or POP instruction is given to the microcomputer, and the next instruction execution is delayed until the access is completed. .. Further, in the conventional microcomputer system having a cache, it is not necessary to access the main memory if the corresponding data is held in the cache when the POP instruction is executed. However, when the PUSH instruction is executed and when the corresponding data is not held in the cache at the time of the POP instruction, there is a problem that the main memory needs to be accessed and execution of the next instruction is waited until the access is completed. Further, in the conventional microcomputer system having the cache, since the data invalidated by the software is held as the valid data even after the POP instruction is executed, there is a problem that the efficiency of the cache is substantially ineffective.

The present invention has been made to solve the above problems, and PUSH for operating a stack is provided.
It is an object of the present invention to provide a stack cache control method and a stack cache that can efficiently hold stack data in the cache by reducing the time required for a POP instruction.

[0012]

[Means for Solving the Problems] Claim 1 according to the present invention
The control method of the stack cache of
When SH is performed, a set of the corresponding address and data is held in place of the main memory 4, and the held data that is not PUSHed to the main memory 4 is PUSHed to the main memory 4 when the microcomputer 3 is not accessing outside, and the microcomputer 3 If the corresponding data is held when the POP is performed, the corresponding data is output to the microcomputer 3 instead of the main memory 4, and the data unnecessary at the POP of the microcomputer 3 may be POPed later at the bottom of the stack. In order to replace with, the POP is made from the main memory 4 when the microcomputer 3 is not accessing the outside.

In order to realize the above method, the stack cache according to claim 2 of the present invention stores a set of address and data at the time of writing, outputs data corresponding to the input address at the time of reading, and It has a validity determining means (V bit 8) for indicating whether the set of address and data is valid and a write determining means (W bit 12) for indicating whether or not each data is written in the corresponding address of the main memory 4. The cache 10 that is written or read according to each means, a pointer (ITSP13) indicating the top of the stack inside the cache 10, a pointer (IBSP14) indicating the bottom of the stack inside the cache 10, and the top of the stack outside the cache 10. Pointer (ET
SP15), an active controller 19 for controlling the cache 10 and the like in accordance with the above pointers, and a bus controller 11 for arbitrating external access between the microcomputer 3 and the active controller 19.
It is equipped with and.

[0014]

In the stack cache control system according to the first aspect, the stack cache 20 is the microcomputer 3 which is the PUS.
When H, the set of the corresponding address and data is held in place of the main memory 4, and the held data that is not PUSHed to the main memory 4 is automatically PUSHed to the main memory 4 when the microcomputer 3 is not accessing the outside. , The microcomputer 3 is a POP
When the corresponding data is held, the corresponding data is output to the microcomputer 3 instead of the main memory 4, and the P
In order to replace unnecessary data in OP with the data at the bottom of the stack that may be POP later, the POP is automatically performed from the main memory 4 when the microcomputer 3 is not accessing the outside. The time required for the PUSH and POP instructions for operating the is reduced, the bus use is averaged, and the stack data is efficiently held in the cache 10.

Further, in the stack cache according to the present invention, the cache 10 stores the set of address and data at the time of writing, outputs the data corresponding to the input address at the time of reading, and determines whether each set of address and data is valid. There is a validity determining means (V bit 8) indicating whether or not, and a write determining means (W bit 12) indicating whether or not each data is written in the corresponding address of the main memory 4, and the write or read operation is performed according to each of the above means. To be done. The active controller 19 uses a pointer (I
The cache 10 and the like are controlled according to the TSP 13), a pointer (IBSP 14) indicating the bottom of the stack inside the cache 10, and a pointer (ETSP 15) indicating the top of the stack outside the cache 10. The bus control unit 11 arbitrates external access between the microcomputer 3 and the active controller 19.
Stack cache 20 having such components
Is realized with relatively small-scale hardware, and
Enable the operation of.

[0016]

1 is a block diagram showing the configuration of a microcomputer system having a stack cache according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 5 are designated by the same reference numerals, and their description will be omitted. In FIG. 1, 8 is a V bit (validity determination means) indicating whether each address and data pair is valid, and 12 is a W bit indicating whether each data is written to a corresponding address in the main memory (write determination). 10) is a cache composed of a selector 5, a data unit 6, a tag unit 7, a V bit 8, a W bit 12, and a comparator 9, and 13 is a pointer (hereinafter referred to as ITSP) indicating the top of the stack inside the cache 10. Abbreviated), 14 is a pointer (hereinafter abbreviated as IBSP) indicating the bottom of the stack inside the cache 10, and 15 is a cache 1
A pointer indicating the top of the stack outside 0 (hereinafter ETSP
16 is a pointer (hereinafter abbreviated as EBSP) indicating the bottom of the stack outside the cache 10, 17 is a 3-bit incrementer / decrementer (hereinafter abbreviated as ID3B), and 18 is an 8-bit incrementer (hereinafter abbreviated as I8B). , 19 are ITSP13, IBSP14, ETSP1
5, an active controller composed of EBSP16, ID3B17, and I8B18, 11 is a bus control unit in which a function of arbitrating the bus use right of the microcomputer 3 and the cache 10 is added to a conventional function, and 20 is a cache 10 and an active control unit. 19,
And a bus control unit 11 is a stack cache. FIG. 2 is a memory map showing the operation of the microcomputer system having the stack cache according to the embodiment of the present invention.

The operation of the microcomputer system having the stack cache shown in FIG. 1 will be described with reference to FIG. In FIG. 2A, the microcomputer 3 uses the cache 1 of the stack cache 20.
PUSH the data to 0. In FIG. 2B, the main memory 4
The held data that has not been PUSHed is automatically PUSHed to the corresponding address of the main memory 4 when the microcomputer 3 is not accessing the outside. In this way, the data in the stack cache 20 is appropriately written in the main memory 4, and the data PUSHed beyond the capacity of the stack cache 20 is overwritten on the data already PUSHed in the main memory 4. However, when the writing from the stack cache 20 to the main memory 4 is not in time and the data in the cache 10 is not written to the main memory 4 at all, prior to the PUSH from the microcomputer 3 to the stack cache 20, After writing to 4, the data is overwritten.

In FIG. 2C, the microcomputer 3 pops the data from the stack cache 20. Since the relevant data is registered in the stack cache 20, it is read from the stack cache 20. As mentioned earlier, POP
The data on the created stack (in the cache 10) remains as a value, but the software does not read and use the value again. Therefore, the bus control unit 11 invalidates the POP data in the cache 10. Therefore, the valid data vertex in the stack cache 20 is always the stack vertex. Figure 2
In (d), when the microcomputer 3 does not access the outside, the most recently erased data among the data erased by overwriting is used instead of the address and data set which becomes unnecessary by the reading from the microcomputer 3. The data written in the main memory 4 are read in order. In this way, even if the data that has been erased by overwriting is popped from the main memory 4 and exceeds the capacity of the stack cache 20, the stack cache 20 is always popped.
If there is data to be popped by the microcomputer 3, but there is no valid data in the cache 10 because the data from the main memory 4 cannot be read in time, the microcomputer 3 does not perform the POP from the cache 10 and the main memory 4 Directly from P
Perform only OP. This is because data that has been POP'd and has become invalid due to software is not taken into the cache 10.

Next, the operation of the microcomputer system having the stack cache of this embodiment will be described in detail with reference to FIG. The initial value of SP1 is written in advance from the microcomputer 3 into ETSP15 and EBSP16. PU data
When SH is performed, the microcomputer 3 decrements (-1) the value of SP1 indicating the top of the current stack with ID8B2,
Writing is performed using the value as an address. Actually, at this time, the bus control unit 11 writes the data in the cache 10. The address is an 8-bit binary number "0101010
1 ”, the data is an 8-bit binary number“ 11101110 ”
The operation in the cache 10 in the case of When the cache 10 has a structure of 8 entries as shown in FIG. 1, the lower 3 bits “101” of the address are the ITSP 13
And the lower 3 bits of the IBSP 14 and the selector 5, and the selector 5 includes the tag unit 7, the W bit 12, and the V bit 8
And a portion corresponding to “101” of the data portion 6 is selected.
In the portion corresponding to “101” of the tag portion 7, the upper 5 bits “XXXXXXX” of the recorded address are set to the upper 5 of the IBSP 14.
Give to a bit. The portion corresponding to "101" of the W bit 12 outputs the recorded value. When the W bit 12 is "1", the corresponding data in the cache 10 has already been written in the main memory 4, so the bus control unit 11 performs the overwrite operation, and when it is "0", the overwrite operation is performed after writing to the main memory 4 described later. As an overwrite operation,
In the portion corresponding to “101” of the tag portion 7, the upper 5 bits “01010” of the address are recorded, and the W bit 12 “101”.
The corresponding portion records “0”, the V bit 8 “101” corresponding portion records “1”, and the data portion 6 “101” corresponding portion records data “11101110”.

When POP data, the microcomputer 3 reads the value of SP1 indicating the top of the current stack as an address, and increments (+1) SP1 by ID8B2. 8 as read address from microcomputer 3
When the binary number "01010101" is output,
The bus control unit 11 first notifies the cache 10 of the address. The lower 3 bits “101” of the address are given to the selector 5 inside the cache 10, and the selector 5 has the tag section 7, the W bit 12, the V bit 8 and the data section 6.
The portion corresponding to “101” of is selected. The portion corresponding to "101" of V bit 8 outputs the recorded value. When V bit 8 is "1", the corresponding data in cache 10 is valid, so bus control unit 11 causes cache 10 to cache P
The OP operation is performed, and when it is "0", the POP is directly performed from the main memory 4. As a POP operation from the cache 10, the portion corresponding to "101" of the tag unit 7 outputs the upper 5 bits "01010" of the recorded address to the comparator 9, and the comparator 9 outputs the upper 5 bits "010" of the input address.
10 "and the upper 5 bits of the recorded address" 0 "
1010 "is compared to notify that they match.
Since it is shown that the addresses match and the corresponding data is valid, the portion corresponding to “101” in the data portion 6 is the data “1110111”.
0 ”is output to the microcomputer 3. W bit 12 “10
"1" is recorded in the portion corresponding to "1", and "10" of V bit 8 is recorded.
"0" is recorded in the portion corresponding to "1". In the active controller 19, if the contents of ETSP15 and the contents of ITSP13 are equal, the contents of both ETSP15 and ITSP13 are ID.
3B17 increments (+1), and if not equal, ITSP13 only increments (+1).

The bus control unit 11 arbitrates access to the outside of the microcomputer 3 and the cache 10, and when there is no external access of the microcomputer 3, the stack cache 20 automatically performs PUSH or POP. If the lower 3 bits of the IBSP 14 and the bits of the ITSP 13 are not equal, the stack cache 20 automatically performs the POP. That is, the active controller 19 replaces the set of addresses and data that is no longer needed by the reading from the microcomputer 3 with the main memory 4 in order from the most recently erased data that has been erased by overwriting. The written data is read into the cache 10. At this time, the active controller 19 first compares the contents of the IBSP 14 and the EBSP 16, and if they are equal, it means that the cache 10 has already read the data to the bottom of the stack in the main memory 4, and therefore does nothing. If not, the value of the IBSP 14 is output to the main memory 4 as an address to read the data. Further, the active controller 19 is the lower 3 of the IBSP 14.
The bits are given to the selector 5, and the selector 5 and the tag unit 7 and W
Corresponding parts of bit 12 and V bit 8 and data part 6 are selected. The read data is recorded in the corresponding part of the data part 6, the corresponding part of the tag part 7 records the upper 5 bits of the IBSP 14, and the corresponding part of the V bit 8 records "1",
“1” is recorded in the corresponding portion of the W bit 12, and IBSP1
4 is incremented (+1) by I8B18 to complete the automatic POP of the stack cache 20.

Lower 3 bits of IBSP14 and ITSP1
When the 3 bits are equal and the ETSP 15 and ITSP 13 bits are not equal, the stack cache 20 automatically performs PUSH. That is, the bus control unit 11 writes the data, which has not been written in the main memory 4 among the data in the cache 10, to the corresponding address in the main memory 4 from the oldest one. The active controller 19 decrements (-1) the ETSP15 with the ID3B17, and the value of the ETSP15 is selected by the selector 5
The selector 5 selects the corresponding portion of the tag portion 7, the W bit 12, the V bit 8 and the data portion 6. First, the bus control unit 11 reads the recorded value from the corresponding portion of the V bit 8, and if it is "1", the corresponding data is valid and therefore is written. If it is "0", other data is written. No writing is performed because it indicates that the device has rewritten the corresponding address. As a write operation, the bus control unit 11 reads out the upper 5 bits of the recorded address from the corresponding portion of the tag unit 7, and outputs it to the main memory 4 as an address of write data together with 3 bits of the ETSP 15. Then, the recorded data is read from the corresponding portion of the data portion 6 and written in the main memory 4. The corresponding portion of the W bit 12 records “1” and the stack cache 20 automatically sets P
USH is complete. Lower 3 bits of IBSP14 and IT
Bits of SP13 are equal and ETSP15 and ITSP1
When the 3 bits are equal, the stack cache 20 does not make an access request to the bus control unit 11.

In this embodiment, the cache 10 has a simple structure as shown in FIG. 1. However, if the address, data, V bit and W bit can be registered as a set, the cache format will be used. And capacity. The capacity of the cache and the data width (the number of bits) depend on the number of registers and the bus width (the number of bits) of the microcomputer to be combined. For example, in the case of a 32-bit microcomputer, the data width of the cache is set to 32 bits or 32 × N bits, and the cache capacity is equal to or larger than the number of registers.
Efficient use is possible if the capacity is four times or more.

[0024]

As described above, according to the invention of claim 1,
When the microcomputer pushes, it holds the corresponding address and data set in place of the main memory, and pushes the held data not pushed to the main memory to the main memory when the microcomputer does not access the outside. , If the microcomputer holds the corresponding data when popping, the corresponding data is output to the microcomputer instead of the main memory, and there is a possibility that the data no longer needed by the popping of the microcomputer will be popped later. In order to replace it with the data at the bottom of the stack, the microcomputer is controlled so that it pops from the main memory when it is not accessing the outside, so the use of the bus is averaged, and PUSH and POP instructions for operating the stack are executed. Can reduce the time needed In addition, there is no such thing as software on invalid data after POP is maintained in the cache, thus the effect is obtained that can be efficiently hold the stack data in the cache.

According to the second aspect of the invention, the set of address and data is stored at the time of writing, and the data corresponding to the input address is output at the time of reading to indicate whether each set of address and data is valid. A cache which has a validity judging means and a write judging means which indicates whether or not each data is written to the corresponding address of the main memory, and which is written or read according to the above means, and a pointer which indicates the top of the stack inside the cache. An active controller configured by a pointer indicating the bottom of the stack inside the cache and a pointer indicating the apex of the stack outside the cache for controlling the cache and the like according to each of the pointers, and the outside of the microcomputer and the active controller. Since the bus control unit for arbitrating access is provided, the operation of the invention of claim 1 The effect is obtained that can be achieved with a relatively small scale of hardware additional.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer system according to an embodiment of the present invention.

FIG. 2 is a memory map showing the operation of this embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional microcomputer system having no cache.

FIG. 4 is a memory map showing the operation of the conventional example of FIG.

FIG. 5 is a block diagram showing a configuration of a conventional microcomputer system having a cache.

FIG. 6 is a memory map showing the operation of the conventional example of FIG.

[Explanation of symbols]

3 Microcomputer 4 Main memory 8 V bit (validity determination means) 10 Cache 11 Bus control unit 12 W bit (write determination means) 13 ITSP (pointer indicating the top of the stack inside the cache) 14 IBSP (bottom of the stack inside the cache) 15 pointer ETSP (pointer indicating the top of the stack outside the cache) 19 active controller 20 stack cache

Claims (2)

[Claims] 1. A stack structure in which the last input data is output first as a data structure on the main memory is supported, the data input to the stack is pushed, the data output from the stack is pop, and another data is output. In a microcomputer system including a microcomputer that performs data processing separately from writing / reading, when the microcomputer pushes, it holds a corresponding address and data set in place of the main memory and pushes it to the main memory. If the held data is pushed to the main memory when the microcomputer is not accessing the outside and the corresponding data is held when the microcomputer pops, the corresponding data is replaced with the main memory instead of the main memory. Output to the above Characterized by popping from the main memory when the microcomputer is not accessing outside in order to replace unnecessary data by popping the microcomputer with data at the bottom of the stack that may be popped later. Stack cache control method. 2. A validity determining means for storing a set of an address and data at the time of writing, outputting data corresponding to an input address at the time of reading, and indicating validity of each set of the address and data, and each data. A cache which has a write determination means for indicating whether or not the data has been written to the corresponding address of the memory, and which is written or read in accordance with each of the above means;
A pointer to the top of the stack inside this cache,
An active controller configured by a pointer indicating the bottom of the stack inside the cache and a pointer indicating the apex of the stack outside the cache for controlling the cache and the like according to each pointer, and external access to the microcomputer and the active controller. And a bus control unit that arbitrates the stack cache.