JPS594783B2 - Kasoukiokuhoshikinojiyouhoushiyorisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that employs a virtual storage method.

In an information processing device that employs a virtual memory method, the address of the command or operand specified by the program is regarded as an address (logical address) in virtual memory, and the logical address is converted using a pre-prepared address conversion table. The real address is converted into a real address, and the main memory is accessed using the real address.

In this case, if the logical address given by the processing unit is converted to a real address each time using a conversion table, access to the main memory will be slow, so it is necessary to store pairs of logical addresses and real addresses that are often used. It is common to provide an address translation buffer (TLB). On the other hand, from a software perspective, programs tend to require larger logical addresses, and the currently commonly used 24-bit logical address is running out of space.

In other words, it is conceivable that the logical address will become variable as it becomes larger, and a processing device that can coexist with several logical address modes is required. SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that employs a virtual storage system that provides modes corresponding to the size of logical addresses and allows each mode to coexist.

Hereinafter, the content of the present invention will be explained in detail with reference to illustrated embodiments.

In FIG. 1, 1 is a register for cassetteing a main memory reference address, and sets a logical address when the processing device is in address translation mode. For convenience, in the following it is assumed that the above reference address has a bit configuration of 0 to 31 with a maximum of 32 bits (32-bit address mode), and 3
A case where the 2-bit address mode and the 24-bit address mode coexist will be described. In address conversion mode, set bits 0 to 31 in register 1,
Of these, bits 0 to 20 are used to refer to TLB2.

Note that the 21st to 31st bits are a common part of the logical address and the real address, and this corresponds to an address within a predetermined block (2 KB in this example) of the main memory. 2 is an address translation buffer (TLB).

In the illustrated example, this address translation buffer 2 is divided into 64 register blocks, each of which is specified by 15 to 20 bits set in register 1. Each block of TLB2 has TLBV
area, TLBR area, and other necessary areas. The TLB area stores 0 to 14 bits of the logical address.
The TLBR area is the corresponding real address O~20
Contains bits. Each block of TLB2 refers to a pair of a logical address and a real address corresponding to a 2KB area in the main memory. Reference numerals 3 and 4 are comparison circuits in which register 1, bits 0 to 7, and bits 8 to 14 of TLB are operated manually, respectively.

5 is a special AND circuit, which receives the comparison circuits 3 and 4 as inputs.

The AND circuit 5 is controlled by a control signal to determine whether to AND the two inputs or to output the result of the comparison circuit 4 as is. This control signal is a control signal for selecting 24-bit address mode or 32-bit address mode. 6 is a real address register for actually accessing the main memory.

Next, the operation shown in FIG. 1 will be explained in detail.

When an access request to the main memory is generated in the processing device, the memory reference address is set in register 1 before the main memory is accessed, and the corresponding block in TLB2 is accessed according to the contents of bits 15 to 20. The contents of TLB, TLBR, etc. registered in the corresponding block are read. Bits 0 to 7 of the read TLBV and bits 0 to 7 of register 1 are compared in comparison circuit 3, and bits 8 to 14 of TLB and bits 8 to 14 of register 1 are compared in comparison circuit 4. As is easily understood, if both of these comparisons match, it means that the memory reference address set in register 1 is registered in TLB 2, and a match signal (InTLB) is output from AND circuit 5. At the same time, the contents of the corresponding TLBR (real address) are set in bits 0 to 20 of the address register 6. In 32-bit address mode,
The real address can be found using the method described above, but in 24-bit mode, bits 0 to 7 set in register 1 are meaningless bits, and it is unclear whether anything is set. It is clear that correct results will not be obtained if the same address translation processing as in the mode is performed.

Therefore, in 24-bit mode, register 1 O~
Comparison circuit 3 that compares 7 bits and O to 7 bits of TLB
You can ignore the result. Looking at Figure 1, comparison circuit 3
The output of the comparator circuit 3 becomes the input power of the AND circuit 5, and when the control signal is set to 24-bit mode, the input from the comparator circuit 3 is ignored, and the result of the comparator circuit 4 is sent directly to the AND circuit 5.
The output is In the 32-bit mode, the AND circuit 5 ANDs the output of the comparator circuit 3 and the comparator circuit 4 according to the control signal.

This method allows operation in both 24-bit address mode and 32-bit address mode.

Up until now, the address translation buffer has been configured with 64 columns x
Although the explanation has been made assuming one row, this is just an example, and it can be easily inferred that the performance of the processing device can be further improved by increasing the number of rows.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Logical address/real address storage register, 2... Address conversion buffer, 3, 4...
...Comparison circuit, 5...AND circuit, 6...
...Real address register.

Claims (1)

[Claims] 1. An information processing device capable of handling multiple logical address modes in which the number of bits of a logical address differs, which has an address translation buffer in which a pair of a logical address and a real address corresponding to the logical address is set, and which performs address translation. When an address translation operation is performed by comparing the logical address given to the logical address with the logical address in the address translation buffer and obtaining the matching logical address and the paired real address, in a certain logical address mode, An information processing device characterized in that a part of the logical address that is the target of the logical address comparison is not used as the target of the logical address comparison in a logical address mode different from the logical address mode.