JPH01260552A - Virtual memory controller - Google Patents

Abstract

PURPOSE:To accelerate an address conversion processing by using a physical page address obtained by applying the address conversion processing just before in case of storing a new logic address in a logic address register. CONSTITUTION:A just before address register 27, a second comparison means 28, and a second physical address register 29 are attached. And a just before logic page address is stored in the just before address register 27, and when a new logic page address coincides with a just before logic page address, a just before physical page address is set as it is as a part of an output physical address. In such a way, reference and a comparison operation can be reduced, and the address conversion processing can be accelerated.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a virtual storage control device for an electronic computer.

(Prior Art) In electronic computers, in order to create programs without taking up the limited real memory space of the main memory, a virtual memory space is set up, and programs are written on this virtual memory space. A method of creating a program is used. This is generally referred to as a virtual memory method, and allows a computer to be used as if the real memory space had been expanded by performing a predetermined address conversion between the main memory space and the virtual memory space to create a correspondence between them. I can do it.

Now, in an electronic computer that employs such a virtual memory system, the following virtual memory control device is used for address conversion.

FIG. 2 shows a configuration diagram of a conventional virtual storage control device.

The device shown in the figure is composed of a logical address register 1, a mapping memory 2, a table memory 3, a virtual address register 4, a comparing means 5, and a physical address register 6.

This device is a circuit that operates to accept a logical address to be translated into a logical address register 1 and finally store a physical address after address translation processing into a physical address register 6.

The logical address register 1 is a register that stores a logical address composed of a logical page address 7 and an intra-page address 8. Furthermore, the logical page address 7 is
It consists of a map address 9, a primary address 10, and a table address 11.

This map address 9 is an address indicating a reference position in the mapping memory. The table address 11 is an address indicating a reference position in the table memory 3. 1
The next address 10 is the address of the logical page address 7 with map address 9 and table address 11 removed.

The mapping memory 2 is a memory that stores mapping addresses 16 for extending logical addresses onto virtual space.

The table memory 3 (translation lookaside buffer) is a memory that stores the correspondence between the virtual page address 13 and the physical page address 14. This table memory 3 is configured such that a virtual page address 13 and a corresponding physical page address 14 can be read by reading a predetermined position.

The virtual address register 4 is a register that stores a virtual address composed of a virtual page address 15 and an intra-page address 8. Furthermore, virtual page address 15
is composed of a mapping address 16 and a secondary address 17.

The secondary address 17 is composed of the primary address 10 of the logical address register 1 and the table address 11.

The comparison means 5 is a circuit that compares the virtual page address 13 of the table memory 3 and the virtual page address 15 of the virtual address register 4.

The physical address register 6 is a register that stores a physical address composed of a physical page address 14 and an intra-page address 8.

The device with the above configuration is operated by a processor (not shown), etc.
operate in a controlled manner.

Here, the specific operation of the apparatus shown in FIG. 2 will be explained using FIG. 3.

FIG. 3 is a flowchart showing the operation of the conventional virtual storage control device shown in FIG.

The mapping address 16, virtual page address 13, and physical page address 14 described above are stored in the mapping memory 2 and table memory 3 in advance.

First, a logical address to be subjected to address conversion processing is stored in the logical address register 1 of the device (step S). Next, map address 9 is extracted from logical page address 7 of this logical address register l (
Step S2). Based on the map address 9 extracted in step S2, the corresponding mapping address 16 in the mapping memory 2 is referred to (step S3). The mapping address 16 referenced in step S3 is
Transfer to the virtual address register 4 (Step S4), and transfer the secondary address 17 composed of the primary address 10 and table address 11 of the logical page address 7 to the virtual address register 4 (Step S5). Then, the virtual page address 15 of the virtual address register 4 is input to the comparing means 5 (step S6).

On the other hand, in parallel with these steps 82 to S6, the full address 11 is extracted from the logical page address 7 of the logical address register l (step S7), and based on this table address 11, the corresponding virtual page address in the table memory 3 is extracted. 13 (step S8).

Then, the virtual address 1 referenced in step S8
3 is manually input to the comparison means 5 (step S9).

As a result of steps S6 and 89, the comparison means 5 receives the virtual page address 15 input from the virtual address conversion process 4.
and the virtual page address 13 input from the table memory 3 (step 510). If this comparison results in a match, the physical address register 6
, physical page address 14 from table memory 3,
The intra-page address 8 is transferred from the virtual address register 4 to create a physical address (step 511).

On the other hand, if the result of step S1.0 is a mismatch, the processor refers to an address conversion table (not shown) and executes another process to determine the answer to Deba Physical 71 (step 512). .

According to the above flow, a logical address is converted to a physical address.

The processing from steps 81 to Sll is sequentially repeated every time a new logical address is stored in the logical address register l.

(Problem to be Solved by the Invention) By the way, as explained above with reference to FIGS. 2 and 3, in conventional devices, when an address is converted from a logical address to a physical address, the new logical address is Every time data is stored in register 1, mapping memory 2 and table memory 3 must be referenced. Furthermore, the virtual page address 15 of the virtual address register 4 and the virtual page address 13 of the table memory 3 had to be compared each time.

In this way, it takes a lot of processing time to refer to mapping memory 2 and table memory 3 and to compare virtual page address 13 and virtual page address 15 every time the contents of logical address register 1 change. , the burden on the computer also increased, which hindered speeding up of address translation processing.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a virtual storage control device that speeds up address translation processing by reducing reference and comparison operations.

(Means for Solving the Problems) A virtual memory control device of the present invention includes a logical address register that stores a logical page address and an address within the page, and a mapping address that indicates the arrangement of the logical page in a virtual space. a mapping memory to store, a table memory to store a table for collating the correspondence between virtual page addresses and physical page addresses, and a virtual page address obtained by referring to the mapping memory using the logical page address. and a virtual address register for temporarily storing the in-page address; a first comparing means for comparing the virtual page address in the virtual address register and a corresponding virtual page address in the table memory; a first physical address register that receives and stores the physical page address and the intra-page address based on a comparison result of the comparing means, and the virtual address register obtained based on the contents of the logical address register. If the virtual page address of the page matches the corresponding virtual page address in the table memory, the physical page address in the table memory and the intra-page address in the virtual address register are stored in the physical address register. In the case where the address conversion process to obtain the physical address of Deba is repeated sequentially,
A previous address register that stores the logical page address used in the previous address translation process, the physical page address used in the previous address translation process, and a valid flag that indicates the validity of these addresses; a second comparison means that compares a new logical page address when executing a new process and the immediately previous logical page address only when the validity is valid; A second physical address register is provided to store a physical page address and a new in-page address, and the logical page address used for the new processing is compared with the immediately previous logical page address stored in the immediately preceding address register. When the two match, the physical address of the blade is obtained based on the contents of the second physical address register.

(Operation) Among the logical addresses to be converted, the logical page address remains unchanged unless the page itself changes. In other words, if addresses in the same page or logical addresses are sequentially stored and an address translation request is made, if a physical page address corresponding to the logical page address is obtained through the first address translation, then that physical page address will be used. , address translation can be performed immediately by replacing only the addresses within the page.

In this case, there is no need to refer to either the mapping memory or the table memory.

For this purpose, the device of the present invention stores the previous logical page address in the previous address register, and when the new logical page address and the previous logical page address match, outputs the previous physical page address as is □ Part of the physical address It is said that

Note that if the previous process is invalid, such as when starting up the device, invalidating table addresses, or rewriting the contents of mapping memory, it cannot be used.
A valid flag is set for this determination.

(Example) FIG. 1 is a configuration diagram of a virtual storage control device of the present invention.

The device shown in FIG. Conversion processing 27, second comparison means 28, and second physical address register 29
It is made up of spikes.

The logical address register 21 has the logical page address 3.
This is a register that stores a logical address composed of 1 and an intra-page address 32. Furthermore, the logical page address 31 is composed of a map address 33, a primary address 34, and a table address 35.

The mapping memory 22 is a memory that stores mapping addresses 36.

The table memory 23 is a memory that stores the correspondence between the virtual page address 37 and the physical page address 38.

The virtual address register 24 stores the virtual page address 39
This is a register that stores a virtual address composed of the address 32 and the intra-page address 32.

Furthermore, the three virtual page addresses are composed of a mapping address 36 and a secondary address 40.

The first comparing means 25 is a circuit that compares the virtual page address 37 of the table memory 23 and the virtual page address 39 of the virtual address register 24.

The first physical address register 26 is a register that stores a physical address composed of a physical page address 38 and an intra-page address 32.

The above configuration is similar to that shown in FIG.

In the present invention, the immediately preceding address register 27 and the second
A comparing means 28 and two second physical address registers are newly added.

The immediately preceding address register 27 is a register that stores the valid flag 41, the immediately preceding logical page address 42, and the immediately preceding physical address 43.

Here, the immediately preceding logical page address 42 and the immediately preceding physical page address 43 refer to the immediately preceding logical page address 31 and physical page address 38 when the conversion from a logical address to a physical address is repeated. say. That is, each time the address conversion process from a logical address to a physical address is completed, the logical page address 31 is stored in the previous address register 27 as the previous logical page address 42, and the physical page address 38 or the previous physical address is stored as the previous logical page address 42. It is stored as a page address 43.

The valid flag 41 indicates a valid state in which address translation processing can be performed using the immediately preceding logical page address 42 and immediately preceding physical page address 43 stored in the immediately preceding address register 27, and an invalid state in which address translation processing cannot be performed. It's a flag.

The second comparison means 28 compares the logical page address 31 of the logical address register 21 and the immediately preceding logical page register 27.
This circuit compares the logical page address 42 with the immediately preceding logical page address 42.

The second physical address register 29 is a register that stores a so-called physical address consisting of the immediately preceding physical page address 43 and the in-page address 32 of the immediately preceding address register 27.

Here, the immediately preceding logical page address 42 and the immediately preceding physical page address 43 refer to the immediately preceding logical page address 31 and physical page address (for example, the previous one) when the process of converting a logical address to a physical address is repeatedly performed. It refers to 38.

The device having the above configuration operates under the control of a processor (not shown) or the like.

The operation of the apparatus shown in FIG. 1 will now be explained using FIG. 4.

FIG. 4 is a flowchart showing the operation of the virtual storage control device of the present invention.

The mapping memory 22 and table memory 23 store a mapping address 36, a virtual page address 37, and a physical page address 38 in the manner described above.

Here, first, a logical address is stored in the logical address register 21 of the device (step 521). Next, the valid flag 41 of the immediately preceding address register 27 is checked (step 522). As mentioned above, when the address conversion process is executed for the first time, the valid flag 41 indicates an invalid state. Therefore, the valid flag 41 is in the invalid state (
For example, if it indicates 0'''), the same processing as the conventional one explained in FIG. 3 is performed (steps 323 to 53).
2). Then, in step S32, a physical address is created using the 1'-th physical address register 26, and then the logical page address 31 and physical page address 38 are transferred to the immediately preceding register 27 (step 537). On the other hand, in step S22, the validity flag 41 is in the valid state (
For example, if the previous address register 27 is valid, step 333
and step S34 are executed in parallel. Step S33
Then, input the immediately preceding logical page address 42 stored in the immediately preceding address register 27 to the second comparison means 28,
The process moves to step S35. In step S34, the logical page address 31 of the logical address register 21 is input to the -2 comparison means 28, and the process moves to step S3'5.

Then, the second comparison means 28 determines that the immediately preceding ring processing pager F
The address 42 is compared with the logical page address 31 (step 535). If they do not match, that is, if the new logical page address 31 is different from the previous logical page address 42 and the previous physical page address 43 cannot be used, the process moves to the invalidity determination portion of step S22. In case of a match,
That is, if the previous physical page address 43 can be used, the process moves to step S36.

In step S36, the second physical address register 29
After transferring the immediately preceding physical page address 43 and intra-page address 32 to create a Deba physical address, the contents are transferred to the first physical address register and the process proceeds to step S.
Move on to 37. In step 837, the logical page address 31 and physical page address 38 are transferred to the immediately preceding address register 27 (step 537).

According to the above flow, a logical address is converted to a physical address.

The present invention is not limited to the above embodiments.

In the above embodiment, the Deba physical address is obtained only from the first physical address register 26, and what is stored in the second physical address register is transferred to the first physical address register once -. Alternatively, if the second physical address register 29 is valid in a selection circuit (not shown), the physical address may be obtained directly from the second physical address register 29.

Further, each of the circuit blocks described above may be replaced with a circuit block having the same function as appropriate, and the processing procedure of the flowchart may also be changed as necessary.

(Effects of the Invention) The virtual memory control device of the present invention configured as described above converts the physical page address obtained by the previous address conversion process when a new logical address is stored in the logical address register 21. Therefore, the number of times the mapping memory 22 and table memory 23 are referred to can be reduced. This simplifies the process and makes it possible to speed up the address translation process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the virtual memory control device of the present invention, FIG. 2 is a block diagram of a conventional virtual memory control device, FIG. 3 is a flowchart showing the operation of the conventional virtual memory control device, and FIG. 4 is a block diagram of the present invention. 3 is a flowchart showing the operation of the virtual storage control device of the invention. 21... Logical address register, 22... Mapping memory, 23... Table memory, 24... Virtual address register, 25... First comparing means, 26... First physical Address register, 27... Immediate address register, 28... Second comparing means, 29... Second physical address register. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] A logical address register that stores a logical page address and an address within the page; a mapping memory that stores a mapping address that indicates the arrangement of the logical page in virtual space; and a mapping memory that stores the virtual page address and the physical page. a table memory that stores a table for checking correspondence with addresses; and a virtual address register that temporarily stores a virtual page address obtained by referring to the mapping memory using the logical page address and the intra-page address. and a first comparing means for comparing the virtual page address in the virtual address register with a corresponding virtual page address in the table memory, and a first comparing means for comparing the virtual page address in the virtual address register with a corresponding virtual page address in the table memory, and determining the physical page address based on the comparison result of the first comparing means. and a first physical address register that receives and stores the in-page address and the virtual page address of the virtual address register obtained based on the contents of the logical address register and the corresponding in-page address in the table memory. If the virtual page address matches, the physical page address in the table memory and the in-page address in the virtual address register are stored in the physical address register to obtain the Deba physical address, and an address conversion process is sequentially repeated. a previous address register for storing a logical page address used in the previous address translation process, a physical page address used in the previous address translation process, and a valid flag indicating the validity of these addresses; a second comparing means for comparing a new logical page address when executing a new process with the immediately previous logical page address only when the flag is valid; and based on the comparison result of the second comparing means. A second physical address register is provided for storing the immediately previous physical page address and a new intra-page address, and the logical page address used for the new processing and the immediately previous logical page address stored in the immediately preceding address register are stored. A virtual storage control device characterized in that, when the two match, the output physical address is obtained based on the contents of the second physical address register.