JPH01142957A - Address converter - Google Patents

Abstract

PURPOSE:To execute an address conversion at a high speed by providing a comparator to compare the row address of a buffer (TLB) for converting an address corresponding to a virtual address to execute the address conversion and the counted value of a counter when an address converting request is executed during a clear execution. CONSTITUTION:When an address converting request is generated before the clearing of all rows of TLB is completed, the row address of the TLB corresponding to the virtual address to execute the address conversion and the output of a counter 23 at the present time are compared by a comparator 25. When the row address is less than the output of the counter 23, it is informed to a TLB control circuit that an 'OFF' signal (a) is outputted from the comparator 25 and the row of the TLB corresponding to the row address is already cleared. As the result, the counting-up of the counter 23 is stopped and the address conversion with the row of the TLB corresponding to the row address is executed.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to an address translation device used in a computer system that employs a virtual address method, and in particular, relates to an address translation device used in a computer system that employs a virtual address method. The present invention relates to an address translation device that performs address translation.

(Prior Art) Conventionally, in computer systems, addresses specified by programs are treated as virtual addresses, and
A virtual address system is employed in which data is accessed from the main memory by converting a virtual address into a real address via an address conversion device.

Computer systems that use such a virtual address method usually use an address translation buffer (Translation Logo) to speed up address translation.
The following address translation is performed using an OKAside Buyer (hereinafter referred to as TLB).

FIG. 2 is a diagram for explaining an address translation method in an address translation device using this TLB.

In the figure, A indicates a virtual address, and this virtual address A is composed of, for example, page addresses p and +p2 consisting of 0 to 19 bits, and an intra-page address D consisting of 20 to 31 bits. 1 is TLB
This is a buffer table created in 1, and a real page address B of the main storage device (not shown) is registered in this buffer table 1. 2 is buffer table 1
For example, 3 is a directory in which a comparison page address Pa consisting of 0 to 11 bits is registered according to the contents of the page address Pa, and 3 compares the comparison page address Pa with the 0 to 11 bit page address P1 of the virtual address A to be converted. It is a comparator that

In the specific address translation operation of this address translation device, first, the directory 2 is referred to to search for a comparison page address Pa corresponding to the page address P2 consisting of 12 to 19 bits of the virtual address A to be address translated. . After that, in the comparator 3, the comparison page address Pa and the virtual address A, which are the search results, are 0 to 1.
It is compared with the 1-bit page address P1. If both match, the real page address B corresponding to the 12-19 bit page address P2 of the virtual address A is searched by referring to the buffer table 1. Finally, the in-page address D of the virtual address A is added to the real page address B, and the address conversion is completed.

Next, the above-mentioned TLB clear circuit will be explained.

FIG. 3 is a block diagram showing the configuration of this clear circuit. In the figure, 11 is a TLB control memory;
The state of B is maintained for each row address (page), and if this is 0'', it means that the corresponding TLB row is in the initial state (no entry has been created).1
2 is a selector for selecting data to be supplied to the TLB control memory 11; update data is selected during normal operation, and "0" is selected when a TLB clear signal is input. Furthermore, 13 is a counter that counts up sequentially from 0 at a predetermined timing in response to the input of the TLB clear signal, and 14 is a selector for supplying the address of the TLB ilJ@memory 11. During normal operation, the TLB row address is When the clear signal is input, each output of the counter 13 is selected.

In the clearing operation of the clearing circuit with the above configuration,
T”LB When the B clear command is executed, first the TL
In response to the input of the B clear signal, the counter 13 sequentially counts up the number of rows of TLB1 from 0 at a predetermined timing. It memory 11
0'' is sequentially output to.

This clears the TLB 1 row corresponding to the row address held in the TLB control memory 11.

However, in the clear circuit of the conventional address translation device described above, while the TLB clear signal is being output, it is not possible to refer to the 1゛LB or to register a new entry in the TLB in order to perform address translation. I can't.

Therefore, in response to an address translation request that occurs during TLB clearing, address translation is executed after waiting for all TLB rows to be cleared, resulting in high-speed address translation. There was a problem that hindered the realization of this idea.

(Problems to be Solved by the Invention) The present invention is intended to solve these difficulties. Even if an address translation request is made while the address translation buffer is being cleared, the cleared row is used. To provide an address translation device that can perform address translation using an address translation buffer in response to an address translation request, and that can improve the usage efficiency of the address translation buffer and speed up address translation. It is an object.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides an address translation buffer used for address translation from a virtual address to a real address, and a buffer clearing method. A counter that sequentially counts up from 0 at a predetermined timing according to the input of a signal, a clearing means that sequentially clears each row of an address conversion buffer as the counter counts, and a virtual address conversion buffer that is to be converted by an address conversion request during clearing. A comparator that compares the row address of the address conversion buffer corresponding to the address with the count value of the counter, and a signal that stops inputting the buffer clear signal when the row address is less than the count value of the counter in the comparison result of this comparator. The device is equipped with an input stop means and an address conversion means that performs address conversion using an address conversion buffer in accordance with the stop of input of a buffer clear signal.

(Function) In the address translation device of the present invention, when the row address of the address translation buffer corresponding to the virtual address to be translated in the comparison result of the comparator is less than the count value of the counter, the control means issues a buffer clear signal. The input is stopped by the signal input stop means, and the address conversion means is thereby configured to perform address conversion using the row of the address conversion buffer corresponding to the row address. Even if there is an address translation request, it is possible to perform address translation using an address translation buffer in an address translation request that uses a row that has been cleared.
It is possible to improve the usage efficiency of the address translation buffer and speed up address translation.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of a clear circuit in an address translation device according to an embodiment of the present invention. In the same figure, 21 is a TLB control memory, which holds the TLB state for each row address (page), and if this is "0", the corresponding 1゛LB row is in the initial state (an entry has been created). means that it has not been done). 22 is a selector for selecting either the update data or "0" and outputting it to the TLB control memory 21; during normal operation, the update data is the TLB control memory 21; when performing clear processing, "0" is the TLB control memory 21;
It is output to the LB control memory 21. 23 is a counter that sequentially counts up from 0 at a predetermined timing in response to the input of the TLB clear signal; 24 is a selector for selecting either the TLB row address or the output of the counter 23 and writing it into the TLB control memory 21; . Also 25 is T
Compare the row address of LB and the output of the counter 23,
If the row address is greater than or equal to the output of the counter 23, an "rOn" signal a indicating that the row of the TLB corresponding to that row address has been cleared is output, and if the row address is less than the output of the counter 23, the row is cleared. A comparator that outputs r Off, a signal a indicating that the TLB row corresponding to the address has not been cleared yet, 2
6, the TLB clear signal from the outside is "On", comparator 2
When the input signal from 5 is “On”, internal 1'L
This is an AND circuit for outputting the B clear signal.

Further, the counter 23 mentioned above is configured to count up when the output signal of the AND circuit 26 is "00", and the selector 22 for data supply is configured to count up when the output signal of the AND circuit 26 is "00".
00”, “0”, r O(f.

When the update data is selected, and when the output signal of the address supply selector 24 is "On", the counter 2 is selected.
When the output of No. 3 is r0ffJ, the row address of the TLB is selected.

Next, the operation of the clear circuit in the address translation device of this embodiment will be explained.

First, when address translation is not performed, it is assumed that the TLB row address is set to '1', and at this time TLB
When the LB clear signal is input, the comparator 25 outputs “O
The signal a of “n” is output, and the AND circuit 26 outputs the “on” signal a.
” signal is output.

As a result, the data supply selector 22 outputs "0".
'' is selected by the output of the counter 23 in the row address supply selector 24. At the same time, the counter 23 starts counting and the TLB
By outputting a write strobe at a predetermined timing to the control memory 21, each row of the TLB is sequentially cleared.

If an address conversion request occurs before all rows of the TLB are cleared, the row address of the TLB corresponding to the hypothetical address to be converted is input, and the comparator 25 uses this row address and the current address. The output of the counter 23 is compared. As a result of the comparison, if the row address is less than the output of the counter 23, the comparator 25 outputs r 0ffJ signal a, AND
The circuit 26 outputs a signal r (Hf), and the TLB control circuit is notified that the TLB row corresponding to this row address has already been cleared. As a result, the selector 22 for data supply The selector 24 for address supply selects each row address of the TLB, and furthermore, the count-up of the counter 23 is stopped, and the TLB corresponding to this row address is
Address translation is performed using the row of LB.

On the other hand, in the comparator 25, the row address is
If the output is greater than 3, the comparator 25 turns “On”
The signal a and the "On" signal S are output from the AND circuit 16, and the TLB control circuit is notified that the row of 'rLB corresponding to the row address has not been cleared yet. As a result, each row in the TLB is continuously cleared, and address translation is performed without using the TLB.

Thus, according to the address translation device of this embodiment, T
Even if an address translation request is made while the LB is being cleared, address translation using the TLB can be performed in the address translation request that uses the row of the cleared TLB, which improves the efficiency of TLB usage. As a result, the speed of address translation can be increased.

[Effects of the Invention] As explained above, according to the address translation device of the present invention, even if an address translation request is made while the address translation buffer is being cleared, the address translation request using the cleared row is This makes it possible to perform address translation using an address translation buffer, thereby improving the efficiency of using the address translation buffer and speeding up address translation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration of a clear circuit in an address translation device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining an address translation method in a conventional address translation device, and FIG. 3 FIG. 1 is a block diagram for explaining the configuration of a clear circuit of a conventional address translation device. 21... TLB control memory, 22... Selector (for data supply), 23... Counter, 24... Selector (for address supply), 25... Comparator, 26...
AND circuit. Applicant Toshiba Corporation Representative Patent Attorney Sasa Suyama −

Claims (2)

[Claims] (1) An address translation buffer used to perform address translation from a virtual address to a real address, a counter that counts up sequentially from 0 at a predetermined timing by inputting a buffer clear signal, and clearing means for sequentially clearing each row of the address translation buffer, and a count value of the counter is compared with a row address of the address translation buffer corresponding to a virtual address to be translated by an address translation request during clearing; a comparator; a signal input stop means for stopping the input of the buffer clear signal when the row address is less than the count value of the counter in the comparison result of the comparator; and the address conversion buffer when the input of the buffer clear signal is stopped. 1. An address translation device comprising: address translation means for performing address translation using. (2) The control means continues to clear the address translation buffer and uses the address translation buffer when the row address of the address translation buffer is greater than or equal to the count value of the counter in the comparison result of the comparator. 2. The address translation device according to claim 1, wherein the address translation device performs an address translation that is not based on an address.