JPH04266140A - Address conversion buffer device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of performance of an address conversion buffer device due to the repetitive updating of a specific address of an address conversion storage of the small capacity. CONSTITUTION:The comparators 50, 51, 52 and 53 of a deciding means decide whether the requested virtual addresses are stored or not in a small capacity address conversion storage 20, the address conversion registers 30 and 31, and a large capacity address conversion storage 40 respectively. A transfer means transfers the address conversion pairs of virtual and real page numbers of the storages 40 and 20 and the register 30 to the storage 20 and the registers 30 and 31 respectively when the virtual address is stored in the storage 40 only.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation buffer device, and more particularly to an address translation buffer device for performing address translation from a virtual address to a real address at high speed.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional address translation buffer device.

A conventional address translation buffer device is shown in FIG.
As shown in FIG. 3, a high-speed small-capacity address translation memory 320 and a larger large-capacity address translation memory 3 store a plurality of address translation pairs including virtual page numbers and real page numbers.
40.

[0004] Using these, the virtual address including the virtual page number and the address within the page received from the address conversion request source in the register 310 is converted into the real address including the real page number and the address within the page. , and output from the register 390.

First, when the register 310 receives a virtual address for which address translation is to be performed from an address translation request source, it supplies the lower part of the virtual page number to the small capacity address translation memory 320 through the selector 384. A comparator 350 compares the virtual page number read from the register 310 with the virtual page number stored in the register 310.

If the comparison result of the comparator 350 matches, the actual page number read from the small capacity address conversion memory 320 and the address within the page in the register 310 are transferred to the registers via selectors 381 and 382, respectively. 390 and completes the address conversion.

On the other hand, if the comparison result of the comparator 350 does not match, in parallel with the above, the lower part of the virtual page number is given to the large-capacity address translation memory 340, and the virtual page read from the large-capacity address translation memory 340 is The comparator 353 compares the number with the virtual page number in the register 310, the result is set in a flip-flop (F/F) 371, and the real page number read from the large-capacity address translation memory 340 is stored in the register. It is set to 370.

The virtual address in register 310 is then transferred to register 311, so that register 310 can receive the next virtual address.

Therefore, if the flip-flop 371 indicates a match, the lower part of the virtual page number of the register 311 is given to the small capacity address conversion memory 320 through the selector 384, and the virtual page number of the register 311 and the register 370 are combined. It stores the actual page number.

[0010] In parallel, the real page number of register 370 and the in-page address of register 311 are sent to register 3 via selectors 381 and 382, respectively.
The address conversion is completed by setting the address to 90.

As explained above, in the conventional address translation buffer device, when a virtual address received from an address translation request source is not in the small-capacity address translation memory but is in the large-capacity address translation memory, the large-capacity address translation buffer device Address translation pairs in the translation memory are stored in a small-capacity address translation memory so that subsequent address translation for this virtual address can be performed at the high speed of one machine cycle.

0012

Problem to be Solved by the Invention The conventional address translation buffer device described above has a small capacity address translation memory of 16
Word, large capacity address translation memory is 512 words,
1st operand, 2nd operand, 3rd operand
In the case of allocation to a virtual page number that is a multiple of 6, etc., the reference words of the small-capacity address translation memory for the first, second, and third operands are the same, and the Each time an operand is written, the virtual page number of the virtual address received from the address translation request source is not in the small-capacity address translation memory but in the large-capacity address translation memory. This method has the disadvantage that one machine cycle is wasted, resulting in a decrease in calculation performance.

An object of the present invention is to maintain an update history for the contents of the small-capacity address translation memory in an address translation register, thereby preventing performance degradation caused by specific repeated updates to the small-capacity address translation memory. The object of the present invention is to provide a buffer device.

[0014]

[Means for Solving the Problems] The address translation buffer device of the first invention has a small capacity address translation memory and a large capacity address translation memory that store a plurality of address translation pairs including virtual page numbers and real page numbers. In an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) first to nth address translation registers that store address translation pairs including a virtual page number and a real page number; (B) a virtual page number of a virtual address received from an address translation request source; a small capacity address translation memory and said first,
- determining means for determining whether the address is stored in any of the N-th address translation registers and determining whether the address is stored in the large-capacity address translation memory; (C
) Based on the determination result of the determination means, the virtual page number of the virtual address received from the address translation request source is stored in either the small-capacity address translation memory and the first to nth address translation registers. and is stored in the large-capacity address translation memory, the large-capacity address translation memory, the small-capacity address translation memory, the first address translation register, ~ the N-1th address translation and a transfer means for transferring and storing the address translation pair read from each of the registers to each of the small capacity address translation memory, the first address translation register, to the Nth address translation register. There is.

Further, the address translation buffer device of the second invention has a small capacity address translation memory and a large capacity address translation memory for storing a plurality of address translation pairs including virtual page numbers and real page numbers. , in an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) virtual a first, which stores an address translation pair including a page number and an actual page number;
~nth address translation register, (B) when the virtual page number of the virtual address received from the address translation request source is a fixed address of the small capacity address translation memory, the small capacity address translation memory and the first address translation register; , to determine whether the address is stored in any of the N-th address translation registers, and determine whether or not it is stored in the large-capacity address translation memory, and at the fixed address of the small-capacity address translation memory. (C) determining means for determining whether the data is stored in the small-capacity address translation memory and determining whether the data is stored in the large-capacity address translation memory; Based on this, when the virtual page number of the virtual address received from the address translation request source is a fixed address in the small capacity address translation memory, the small capacity address translation memory and the first to nth address translation registers , but is stored in the large-capacity address translation memory, the large-capacity address translation memory, the small-capacity address translation memory, the first address translation register, - the Nth address translation register. - The address translation pair read from each of the first address translation registers is transferred and stored in each of the small capacity address translation memory, the first address translation register, to the Nth address translation register, and If the address is not a fixed address in the address translation memory, the address translation pair read from the large capacity address translation memory is not stored in the small capacity address translation memory but is stored in the large capacity address translation memory. and a transfer means for transferring and storing the data in the small-capacity address conversion memory.

Furthermore, the address translation buffer device of the third invention has a small capacity address translation memory and a large capacity address translation memory for storing a plurality of address translation pairs including virtual page numbers and real page numbers. , in an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) virtual The first one stores an address translation pair including a page number and a real page number.
, ~ nth address translation register, (B) a comparison address register that holds a designated address to be compared with the address that refers to the small-capacity address translation memory, (C) a virtual address received from the address translation request source. When the virtual page number is a specified address held in the comparison address register, it is determined whether the virtual page number is stored in any of the small-capacity address translation memory and the first to Nth address translation registers; and , determines whether or not the specified address is stored in the large-capacity address translation memory, and if the specified address is not held in the comparison address register, determines whether or not it is stored in the small-capacity address translation memory; Judgment means for determining whether or not the data is stored in the large-capacity address translation memory (
D) Based on the determination result of the determination means, if the virtual page number of the virtual address received from the address translation request source is the specified address to be held in the comparison address register, the small-capacity address translation storage and the 1
, ~n-th address translation register, but is stored in the large-capacity address translation memory, the large-capacity address translation memory, the small-capacity address translation memory, and the first address translation register, ~
The address translation pairs read from each of the N-1 address translation registers are stored in the small capacity address translation memory;
If the address is not a specified address to be transferred and stored in each of the first address translation register to the Nth address translation register and held in the comparison address register, it is not stored in the small capacity address translation memory. , a transfer means for transferring the address translation pair read from the large capacity address translation memory to the small capacity address translation memory and storing the address translation pair when the address translation pair is stored in the large capacity address translation memory. .

[0017]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an address translation buffer device according to the first invention.

The address translation buffer device of this embodiment is as follows:
As shown in FIG. 1, it has a high-speed small-capacity address translation memory 20 and a larger large-capacity address translation memory 40 that store a plurality of address translation pairs including virtual page numbers and real page numbers.

Using these, the virtual address containing the virtual page number and the address within the page received from the address conversion request source in the register 10 is converted into the real address containing the real page number and the address within the page. , and output from the register 90.

First, when the register 10 receives a virtual address to be translated from an address translation request source,
The lower part of the virtual page number is given to the small capacity address translation memory 20 through the selector 84, and the virtual page number read from the small capacity address translation memory 20 and the virtual page number stored in the register 10 are compared by the comparator 50. .

In parallel with this, the virtual page number taken out from the address translation registers 30 and 31 that store the address translation pair including the virtual page number and the real page number and the virtual page number in the register 10 are Comparator 51
, 52.

If any of the comparison results of the comparators 50, 51, and 52 match, the output of the OR circuit 60 causes the small-capacity address conversion memory 20 and the address conversion registers 30, 31 to be selected from the matching results. The read actual page number is passed through selectors 80 and 81, and the in-page address in register 10 is set in register 90 via selector 82, thereby completing the address conversion.

On the other hand, if any of the comparison results of the comparators 50, 51, and 52 do not match, in parallel with the above, the lower part of the virtual page number is given to the large-capacity address conversion memory 40,
A comparator 5 compares the virtual page number read from the large-capacity address translation memory 40 with the virtual page number stored in the register 10.
3, the result is a flip-flop (F/F)
71, and the real page number read from the large-capacity address conversion memory 40 is set in the register 70.

[0025]The virtual address of register 10 is
Transferred to register 11, register 10 can receive the next virtual address.

Therefore, if the flip-flop 71 indicates a match, the address translation pair of the address translation register 30 is transferred to the address translation register 31, and the address translation pair of the address translation register 30 is transferred to the address translation register 31.
The lower part of the virtual page number 1 is given to the small-capacity address translation memory 20 through the selector 84, and the read address translation pair is transferred to the address translation register 30, where the virtual page number of the register 11 and the real page number of the register 70 are combined. is stored in the small capacity address conversion memory 20.

Further, in parallel with this, the actual page number of the register 70 and the in-page address of the register 11 are set in the register 90 via the selectors 81 and 82, respectively, and the address conversion is completed.

FIG. 2 is a block diagram showing an embodiment of the address translation buffer device according to the second invention.

The address translation buffer device of this embodiment is as follows:
As shown in FIG. 2, it has a high-speed small-capacity address translation memory 120 and a larger large-capacity address translation memory 140 that store a plurality of address translation pairs including virtual page numbers and real page numbers.

Using these, the virtual address including the virtual page number and the address within the page received from the address conversion request source in the register 110 is converted into the real address including the real page number and the address within the page. , and output from the register 190.

First, when the register 110 receives a virtual address for which address translation is to be performed from an address translation request source, it supplies the lower part of the virtual page number to the small capacity address translation memory 120 through the selector 184. A comparator 150 compares the virtual page number read from the register 110 with the virtual page number stored in the register 110.

Additionally, in parallel with this, the virtual page number taken out from the address translation registers 130 and 131 that store the address translation pair including the virtual page number and the real page number, and the virtual page number in the register 110 are Comparators 151 and 152 compare.

AND circuits 161 and 162 use a comparator 155 to perform a comparison when the lower value of the virtual page number given to the small capacity address translation memory 120 is a predetermined fixed address of the small capacity address translation memory 120. Since the OR circuit 160 generates an output when the comparison results of the comparators 151 and 152 match, the OR circuit 160 generates an output when any of the comparison results of the comparators 150, 151, and 152 match. .

Then, the output of the OR circuit 160 causes the small capacity address conversion memory 120 and the address conversion register 1 to be
The actual page number read from the matched page number 30 and 131 is passed through selectors 180 and 181, and the in-page address in register 110 is set in register 190 via selector 182 to complete the address conversion. There is.

On the other hand, if any of the comparison results of the comparators 150, 151, and 152 do not match, in parallel with the above, the lower part of the virtual page number is given to the large-capacity address conversion memory 140, and large-capacity address conversion is performed. A comparator 153 compares the virtual page number read from the memory 140 and the virtual page number in the register 110, and the result is set in a flip-flop (F/F) 171 and read out from the large-capacity address translation memory 140. The actual page number is in register 1.
It is set to 70.

The virtual address in register 110 is then transferred to register 111, so that register 110 can receive the next virtual address.

Therefore, if the flip-flop 171 indicates a match, the address translation pair in the address translation register 130 is transferred to the address translation register 131, and the lower virtual page number of the register 111 is transferred to the small capacity address through the selector 184. The address translation pair is transferred to the translation memory 120 and read out to the address translation register 130, and the virtual page number of the register 111 and the register 17 are transferred.
The real page number 0 is stored in the small capacity address conversion memory 120.

In parallel, the real page number of register 170 and the in-page address of register 111 are sent to register 1 via selectors 181 and 182, respectively.
The address conversion is completed by setting the address to 90.

On the other hand, AND circuits 161 and 162 each use a comparator 155 when the lower part of the virtual page number given to small capacity address translation memory 120 is not a predetermined fixed address of small capacity address translation memory 120. Since it does not generate an output, OR circuit 160 generates an output when comparator 150 matches.

Then, by the output of the OR circuit 160, the actual page number read from the small capacity address conversion memory 120 is passed through selectors 180 and 181, and the address within the page in the register 110 is passed through the selector 182, and the address is sent to the register. The address conversion is completed by setting the address to 190.

On the other hand, if the comparison result of the comparator 150 does not match, the lower virtual page number is given to the large-capacity address translation memory 140 in parallel to the above, and the virtual page read from the large-capacity address translation memory 140 is The comparator 153 compares the number with the virtual page number in the register 110, the result is set in the flip-flop (F/F) 171, and the real page number read from the large-capacity address conversion memory 140 is stored in the register. It is set to 170.

The virtual address in register 110 is then transferred to register 111, so that register 110 can receive the next virtual address.

Therefore, if the flip-flop 171 indicates a match, the lower part of the virtual page number of the register 111 is given to the small capacity address conversion memory 120 through the selector 184, and the virtual page number of the register 111 and the register 170 are combined. The actual page number is stored in the small capacity address conversion memory 120.

In parallel, the real page number of register 170 and the in-page address of register 111 are sent to register 1 via selectors 181 and 182, respectively.
The address conversion is completed by setting the address to 90.

FIG. 3 is a block diagram showing an embodiment of an address translation buffer device according to the third invention.

The address translation buffer device of this embodiment is as follows:
As shown in FIG. 3, it has a high-speed small-capacity address translation memory 220 and a larger large-capacity address translation memory 240 that store a plurality of address translation pairs including virtual page numbers and real page numbers.

Using these, the virtual address including the virtual page number and the address within the page received in the register 210 from the address conversion request source is converted into the real address including the real page number and the address within the page. It is converted into and output from the register 290.

First, when the register 210 receives a virtual address for which address translation is to be performed from an address translation request source, it supplies the lower part of the virtual page number to the small capacity address translation memory 220 through the selector 284. A comparator 250 compares the virtual page number read from the register 210 with the virtual page number stored in the register 210.

In parallel, the virtual page number retrieved from the address translation registers 230 and 231 that store the address translation pair including the virtual page number and the real page number and the virtual page number in the register 210 are Comparators 251 and 252 compare.

The AND circuits 261 and 262 use the comparator 255 to select the lower value of the virtual page number given to the small-capacity address translation memory 220 from the small-capacity address translation memory 220 specified in advance and held in the comparison address register 235. , the comparator 251,
Since the OR circuit 260 generates an output when the comparison results of the comparators 250 and 252 match, the OR circuit 260
An output is generated when any of the 1,252 comparison results match.

Then, the output of the OR circuit 260 causes the small capacity address conversion memory 220 and the address conversion register 2
The real page number read from the matched one of 30 and 231 is passed through selectors 280 and 281, and the in-page address in register 210 is set in register 290 via selector 282 to complete the address conversion. There is.

On the other hand, if any of the comparison results of the comparators 250, 251, and 252 do not match, in parallel with the above, the lower part of the virtual page number is given to the large-capacity address conversion memory 240, and large-capacity address conversion is performed. A comparator 253 compares the virtual page number read from the memory 240 and the virtual page number in the register 210, and the result is set in a flip-flop (F/F) 271 and read out from the large-capacity address conversion memory 240. The actual page number is in register 2.
It is set to 70.

The virtual address in register 210 is then transferred to register 211, so that register 210 can receive the next virtual address.

If the flip-flop 271 indicates a match, the address translation pair in the address translation register 230 is transferred to the address translation register 231, and the lower virtual page number of the register 211 is transferred to the small capacity address through the selector 284. The address translation pair read out is transferred to the translation memory 220 and transferred to the address translation register 230, and the virtual page number of the register 211 and the register 27 are transferred.
The real page number 0 is stored in the small capacity address conversion memory 220.

In parallel, the real page number of register 270 and the in-page address of register 211 are sent to register 2 via selectors 281 and 282, respectively.
The address conversion is completed by setting the address to 90.

On the other hand, the AND circuits 261 and 262 use the comparator 255 to select the lower value of the virtual page number given to the small capacity address translation memory 220 from the small capacity address translation memory 2 specified in advance and held in the comparison address register 235.
Since the OR circuit 260 does not generate an output when the address is not the designated address of 20, the OR circuit 260 generates an output when the comparator 250 matches.

Then, by the output of the OR circuit 260, the actual page number read from the small capacity address conversion memory 220 is passed through the selectors 280 and 281, and the address within the page in the register 210 is passed through the selector 282, and the address is sent to the register. 290 and completes the address conversion.

On the other hand, if the comparison result of the comparator 250 does not match, in parallel with the above, the lower part of the virtual page number is given to the large-capacity address translation memory 240, and the virtual page read from the large-capacity address translation memory 240 is The comparator 253 compares the number with the virtual page number in the register 210, the result is set in the flip-flop (F/F) 271, and the real page number read from the large-capacity address translation memory 240 is stored in the register. It is set to 270.

The virtual address in register 210 is then transferred to register 211, so that register 210 can receive the next virtual address.

Therefore, if the flip-flop 271 indicates a match, the lower part of the virtual page number of the register 211 is given to the small capacity address conversion memory 220 through the selector 284, and the virtual page number of the register 211 and the register 270 are combined. The actual page number is stored in the small capacity address conversion memory 220.

In parallel, the real page number of register 270 and the in-page address of register 211 are sent to register 2 via selectors 281 and 282, respectively.
The address conversion is completed by setting the address to 90.

[0062]

As explained above, the address translation buffer device of the first invention can perform small-capacity address translation by holding the update history for the entire contents of the small-capacity address translation memory in N address translation registers. This has the effect of preventing performance degradation due to repeated updating of a specific address for the entire stored content.

Further, the address translation buffer device of the second invention maintains the update history for the contents of the fixed address in the small capacity address translation memory in the N address translation registers, so that the fixed address in the small capacity address translation memory can be updated. This has the effect of being able to prevent performance degradation due to repeated updates of a specific address for the contents of the file.

Furthermore, the address translation buffer device of the third invention sets a designated address in the comparison address register, and holds the update history for the contents of the designated address in the small capacity address translation memory in the N address translation registers. This has the effect that it is possible to prevent performance degradation due to repeated updates of a specific address to the contents of a specified address in the small capacity address translation storage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an address translation buffer device according to a first invention.

FIG. 2 is a block diagram showing an embodiment of an address translation buffer device according to a second invention.

FIG. 3 is a block diagram showing an embodiment of an address translation buffer device according to a third invention.

FIG. 4 is a block diagram showing an example of a conventional address translation buffer device.

[Explanation of symbols]

10, 11, 70, 90, 110, 111, 170, 1
90, 210, 211, 270, 290, 310, 31
1,370,390 Register 20, 120, 220, 320 Small capacity address translation memory 30, 31, 130, 131, 230, 231, 330
, 331 Address translation register 40, 140,
240, 340 Large capacity address translation memory 50, 51, 52, 53, 150, 151, 152, 1
53,155,250,251,252,253,25
5,350,351,352,353 Comparator 6
0,160,260,360 OR circuit 71,1
71,271,371 Flip-flop (F/
F) 80, 81, 82, 83, 180, 181, 182, 1
83,280,281,282,283,380,38
1,382,383 Selector 161,162,261,262 AND circuit 2
35 Comparison address register

Claims (3)

[Claims] 1. By having a small-capacity address translation memory and a large-capacity address translation memory for storing a plurality of address translation pairs including virtual page numbers and real page numbers,
In an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) a virtual page (B) a virtual page number of a virtual address received from an address translation request source is stored in the small-capacity address translation memory; and said first, ~
(C) determining means for determining whether the address is stored in any of the N-th address translation registers and determining whether the address is stored in the large-capacity address translation memory;
Based on the determination result of the determination means, the virtual page number of the virtual address received from the address translation request source is stored in any of the small capacity address translation memory and the first to nth address translation registers. not stored in the large-capacity address translation memory, the large-capacity address translation memory, the small-capacity address translation memory,
The address translation pairs read from each of the first address translation register and the N-1th address translation register are stored in the small capacity address translation storage, the first address translation register and the N-th address translation register. An address translation buffer device comprising a transfer means for transferring and storing data in each of the addresses. 2. By having a small-capacity address translation memory and a large-capacity address translation memory for storing a plurality of address translation pairs including virtual page numbers and real page numbers,
In an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) a virtual page (B) a virtual page number of a virtual address received from an address translation request source is stored in the small-capacity address translation memory; If the address is a fixed address, it is determined whether or not it is stored in either the small-capacity address translation memory and the first to Nth address translation registers, and whether or not it is stored in the large-capacity address translation memory. If the address is not a fixed address in the small-capacity address translation memory, it is determined whether the address is stored in the small-capacity address translation memory and whether or not it is stored in the large-capacity address translation memory. (C) based on the determination result of the determination means, when the virtual page number of the virtual address received from the address translation request source is a fixed address of the small capacity address translation storage; If the data is not stored in the small-capacity address translation memory and the first to n-th address translation registers, but is stored in the large-capacity address translation memory, the large-capacity address translation memory and the small Address translation pairs read from each of the capacity address translation memory, the first address translation register, and the N-1th address translation register are stored in the small capacity address translation memory, the first address translation register, and the N-1th address translation register. If the address is not a fixed address in the small-capacity address translation memory, the address is not stored in the small-capacity address translation memory, but is stored in the large-capacity address translation memory. 2. An address translation buffer device comprising: a transfer means for transferring and storing an address translation pair read from said large capacity address translation memory into said small capacity address translation memory when the address translation pair is read from said large capacity address translation memory. 3. By having a small-capacity address translation memory and a large-capacity address translation memory for storing a plurality of address translation pairs including virtual page numbers and real page numbers,
In an address translation buffer device that converts a virtual address including a virtual page number and an address within the page received from an address translation request source into a real address including a real page number and an address within the page, (A) a virtual page (B) a comparison address that holds a specified address to be compared with an address that refers to the small-capacity address translation memory; register, (C
) When the virtual page number of the virtual address received from the address translation request source is the specified address to be held in the comparison address register, either the small capacity address translation memory or the first to Nth address translation registers It is determined whether the address is stored in the large-capacity address translation memory, and if it is not the specified address to be held in the comparison address register, the address is stored in the small-capacity address translation memory. (D) determining whether or not the address translation is stored in the large-capacity address translation memory; When the virtual page number of the virtual address obtained is the designated address held in the comparison address register, it is not stored in either the small capacity address translation memory or the first to nth address translation registers; When stored in the large-capacity address translation memory, reading from each of the large-capacity address translation memory, the small-capacity address translation memory, the first address translation register, and the N-1th address translation register. The address translation pair is transferred to and stored in each of the small-capacity address translation memory, the first address translation register, to the Nth address translation register, and when the address is not a specified address to be held in the comparison address register, If the address translation pair is not stored in the small-capacity address translation memory but is stored in the large-capacity address translation memory, the address translation pair read from the large-capacity address translation memory is transferred to the small-capacity address translation memory. An address translation buffer device comprising: a storage transfer means.