JP2864548B2 - Instruction cache device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction cache device, and more particularly to an instruction cache device used for an information processing device.

2. Description of the Related Art A conventional instruction cache device will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of an instruction cache device having two compartments. The hit determination circuit 10 determines whether or not the target data is stored in the cache. The data matrices 15 and 16 are two-compartment address arrays that store copies of data stored in a main storage device (not shown) in block units. The address matrices 11 and 12 are two-compartment address arrays for storing address information of data stored in data matrices 15 and 16 provided correspondingly.

The comparison circuits 13 and 14 are provided corresponding to the compartments in order to compare the address information read from the address matrix with a part of the address of the memory access. The output data selection circuit 17 is a selector that determines which output of the data matrices 15 and 16 is to be selected according to the determination result of the hit determination circuit 10.

The instruction address register 18 is a register for storing an instruction address by a memory access, and an output matrix is searched for an address matrix and a data matrix. The output of the instruction address register 18 is added by the instruction word length in the adder 19 and stored in the address register 18 again via the input selection circuit 20.

First, when the instruction address is rewritten due to execution of a branch instruction or the like, the instruction address 121 sent from the arithmetic unit (not shown), which is a higher-level device, is written to the instruction address register 18 via the instruction address register input selection circuit 20. It is.

Thereafter, the compartments 11 and 12 of the address matrix are read at the middle part 103 of the output 101 of the instruction address register 18. At the same time, each compartment 15, 16 of the data matrix is read with a value 102 obtained by combining the middle part and the lower part of the output 101 of the instruction address register 18. The outputs 105 and 106 of the address matrix compartments 11 and 12 are compared with the upper part 104 of the output 101 of the instruction address register 18 by comparing circuits 13 and 14, respectively.

The hit judgment circuit 10 compares the comparison results 107 and 108 of the comparison circuits 13 and 14.
If the output of the address matrix compartment 11 matches, the data matrix compartment 15
On the other hand, if the outputs of the address matrix compartment 12 match, a data selection signal 111 is sent to the output data selection circuit 17 so as to select the data matrix compartment 15. Then, the output 115 of the output data selection circuit 17 is sent to the arithmetic unit.

The output 101 of the instruction address register 18 is added by the adder 19 to the instruction word length 113 sent from the arithmetic unit, and the addition result 114 is stored in the instruction address register 18 for fetching the next instruction.

If none of the address matrix compartments 11 and 12 match, the hit determination circuit 10 sends a data read request 112 to a main storage device (not shown). When the read data 116 is sent from the main storage device, a predetermined replacement compartment determination method (for example, LRU method)
A data matrix update instruction 117 (118) is sent to the compartment determined by the above, for example, the data matrix compartment 15 (16), and the read data 116 is stored.
At the same time, the corresponding address matrix compartment 11
An address matrix update instruction 119 (120) is sent to (12) to instruct to store the upper part 104 of the output 101 of the instruction address register 18.

In the above-described conventional instruction cache device, since the delay time of the path from the search of the address matrix by the output of the instruction address register to the selection of the data matrix output based on the result is large, the processing speed of the entire information processing device is reduced. It has the disadvantage of hindering.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve such disadvantages of the related art, and the purpose thereof is to
An object of the present invention is to provide an instruction cache device capable of shortening a delay time of a path from a search of a data matrix to an output of an instruction address register to an output of the data matrix, thereby speeding up the entire processing.

An instruction cache device according to the present invention includes a data matrix having data stored in a main storage device as a copy in a block unit, an address matrix storing address information of the copy in a block unit, and a memory access from a host device. , The read address of the address matrix is sequentially incremented by "1" by using the instruction address sent from the higher-level device as an initial value, and the address matrix is accessed with a lower part of the read address after the increment. Address matrix reading means, comparing means for comparing the upper part of the read address after the step with the address read from the address matrix by the address matrix reading means, and storing the result of comparison by the comparing means. Comparison result storage means, sent from the higher-level device in response to a memory access from the higher-level device. Data matrix reading means for incrementing the read address of the data matrix by the instruction word length with the instruction address as an initial value; and when the data matrix is read, target data is present in the data matrix from the output of the comparison result storage means. Hit determination means for determining whether or not to perform.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 2 are denoted by the same reference numerals. The comparison result register 24 is a first-in first-out buffer (FIFO) that stores the comparison results 107 and 108 of the comparison circuits 13 and 14, respectively. This FIFO buffer 24
Are output to the hit determination circuit 10. The FIFO control circuit 25 controls writing and reading of the FIFO buffer 24.

The address matrix read register 22 stores the instruction address 121 from the arithmetic unit as an initial value and the “1” added output of the adder 21 via the input selection circuit 23. Therefore, read addresses 201 and 202 sequentially incremented by "1" are derived from the output 213 of the address matrix read register 22, and the address matrices 11 and 12 are sequentially accessed by the lower part 201 of the read address. .

First, when the instruction address is rewritten by executing a branch instruction or the like, the instruction address 121 sent from the arithmetic unit is written into the instruction address register 18 via the instruction address register input selection circuit 20. At the same time, the instruction addresses 121 corresponding to the key part and the block number in the instruction cache, respectively.
The upper part and the middle part are written to the address matrix read address register 22 via the address matrix read address register input selection circuit 23.

In the next cycle, the compartments 11 and 12 of the address matrix are read from the lower part 201 of the output 213 of the address matrix read address register 22. Outputs 105 and 106 of the address matrix compartments 11 and 12 are comparison circuits 13 and 14, respectively.
Is compared with the upper part 202 of the output 213 of the address matrix read address register 22, and the comparison results 107, 108
Are stored in the FIFO buffer 24.

At the same time, the output 213 of the address matrix read address register 22 and the fixed value "1" are added by the adder 21, and as a result 211 is stored in the address matrix read address register 22, and the next block of the address matrix compartments 11, 12 is stored. The number becomes searchable.

In the following cycle, the block number in the instruction cache,
Each of the compartments 15 and 16 of the data matrix is read with a value 102 obtained by combining the middle part and the lower part of the output 101 of the instruction address register 18 corresponding to the relative address in the block.

At the same time, the hit decision circuit 10
Enter 3,204, if address matrix compartment 11
Indicates that it matches the upper part 202 of the output 213 of the address matrix read address register 22, if the data matrix compartment 15 is selected,
Conversely, if the output of the address matrix compartment 12 indicates that it matches the upper part 202 of the output 213 of the address matrix read address register 22, an output data selection circuit is selected to select the data matrix compartment 16. The data selection signal 111 is sent to 17. Then, the output 115 of the output data selection circuit 17 is sent to the arithmetic unit.

The output 101 of the instruction address register 18 is added to the instruction word length 113 sent from the arithmetic unit by the adder 19, and the addition result 114 is stored in the instruction address register 18 for fetching the next instruction.

On the other hand, in parallel with the reading of the data matrix, the search for the address matrix compartments 11 and 12 and the updating of the address matrix read address register 22 are performed in the same manner as the above operation by the output 213 of the updated address matrix read address register 22. Done.

The FIFO control circuit 25 informs the adder 19 that the middle portion of the instruction address register 18, that is, the block number has been updated.
Is detected by the carry signal 205 output from the
An output data update instruction 208 is sent to the buffer 24. Each time the address matrix compartments 11 and 12 are searched, the data storage instruction 209 is sent to the FIFO buffer 24.
Send. In addition, the buffer full signal from the FIFO buffer 24
When 207 is received, the address matrix read address register 2
2 for the update suppression signal 206 and the FIFO buffer
The transmission of the data storage instruction 209 to 24 is suppressed.

If the output of the FIFO buffer 24 indicates that none of the address matrix compartments 11 and 12 match the output 213 of the address matrix read address register 22, the hit determination circuit 10 reads the data to the main memory. Send request 112. When the read data 116 is sent from the main storage device, a data matrix update instruction 117 is sent to a compartment determined by a predetermined replacement compartment determination method (for example, the LRU method), for example, the data matrix compartment 15, and the read is performed. The data 116 is stored.

At the same time, the corresponding address matrix compartment 11
Sends an address matrix update instruction 119 to store the upper part 104 of the output 101 of the instruction address register 18. Further, the address matrix read address register 22 stores a value 214 obtained by combining the upper part and the middle part of the output 101 of the instruction address register 18 selected by the address matrix read address register input selection circuit 23. Then, in the next cycle, an initialization instruction 215 is sent to the FIFO buffer 24 to erase the contents stored so far and newly store the search results of the address matrix compartments 11 and 12, and thereafter, Continue normal operation as you did.

As described above, by storing the cache hit / miss hit determination results in the FIFO buffer 24 in advance, the third
As shown in the figure, the delay time of the path from the output of the instruction address register 18 to the search and output of the data matrices 15 and 16 is dominated by the time of the address register 18, the data matrices 15 and 16 and the selection circuit 17. Become.

On the other hand, in the prior art, as shown in FIG. 4, an address register 18, address matrices 11 and 12, comparison circuits 13 and 14, a selection circuit
It is clear that the delay time of the 17 paths becomes dominant, and thus the delay time according to the present invention is small.

As described above, according to the present invention, the search of the address matrix of the instruction cache is performed in advance, and the result is stored in the FIFO buffer, so that the delay of the path having a large delay time is reduced. There is an effect that the time can be reduced and the processing speed of the entire information processing apparatus can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional instruction cache device, FIG. 3 is a schematic diagram showing a delay time path of the embodiment of the present invention, and FIG. FIG. 3 is a schematic diagram illustrating a delay time path of the device. Description of Signs of Main Parts 10 Hit Search Circuit 11,12 Address Matrix 13,14 Comparison Circuit 15,16 Data Matrix 18 Address Register 19,21 Adder 22 Address Matrix Read address register 24 …… FIFO buffer

Claims (1)

(57) [Claims] 1. A data matrix having data stored in a main storage device as a copy in a block unit, an address matrix storing address information of the copy in a block unit, and a memory device in response to a memory access from a host device. Address matrix reading means for sequentially incrementing the read address of the address matrix by "1" by using the instruction address sent from the host device as an initial value, and accessing the address matrix with a lower part of the read address after the increment; Comparison means for comparing the upper part of the read address after the step with the address read from the address matrix by the address matrix reading means, comparison result storage means for storing a comparison result by the comparison means, In response to a memory access from the higher-level device, the instruction address sent from the higher-level device is used as an initial value for the command address. Data matrix reading means for incrementing the read address of the data matrix by the instruction word length, and determining whether or not target data exists in the data matrix from the output of the comparison result storage means when reading the data matrix. An instruction cache device comprising: