JPH06103477B2 - Parallel cache memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel cache memory used in a data processing system having a plurality of processors.

[0002]

2. Description of the Related Art Conventionally, as a means for realizing high-speed data processing, a plurality of processors P are used as shown in FIG. 8, and the plurality of processors P are connected to a memory bus B to share a memory M. Some have adopted a combined multiprocessor system.

However, if each processor P is simply coupled to the memory bus B in this way, memory access requests such as read / write to the shared memory M from each processor P may concentrate on the memory bus B. It is known that when the number of processors P is about 4 to 16, the performance improvement of the entire system cannot be expected any more.

As a means for solving this, as shown in FIG. 9, the cache memory CM1 for each processor P,
Some have CM2, ... Connected. The following are known as reference documents relating to cache memories.

Paul Sweazey and Alan Jay Smith: A Cl
ass of a Compatible Cache Consistency Protocol and
their Support by the IEEE Futurebus, Proceedingso
f the 13th Annual International Symposium on Compu
ter Architecture, June, 1986. James Archibald and Jean-loup Baer: Cache Coherenc
e Protocols: Evaluation Using a Multiprocessor Sim
ulation Model, ACM Transacions on Computer, Vol.4,
No. 4, Novemder, 1986. Here, in FIG. 9, the cache memories CM1, CM2, ... Connected to the respective processors P are shared memories M recently referenced by the corresponding processors P.
Stores a copy of the contents of one of the cache lines. Each cache line here stores the following information. (1) Data of several words (generally 4 to 16 words) (this is called cache line data). (2) Shared memory device M in which data originally existed
Address above. (3) Cache line state, for example, as tag information: -whether valid data is stored in the cache line-whether the cache line data exists in other cache memory, shared memory Whether it is the same as the above data, etc.

In the cache memories CM1, CM2, ..., Which have been described above, when a read / write request from each processor P to the shared memory M is issued by a certain processor P, a processor P is issued. If the cache memory CM1 connected to is holding the requested cache line data, FIG.
As shown in the operation sequence of
1 returns the requested partial data from the cache line data to the processor P and ends the processing.

If the cache memory CM1 connected to the processor P does not hold the corresponding cache line data, as shown in the operation sequence of FIG. The cache memory CM2 and the shared memory M are requested to transfer the cache line data corresponding to the address. Then, the cache memory CM2 that has received the data transfer request determines whether or not the requested cache line data is held in that cache line, and whether or not it should be transferred to the cache memory CM1. Then, the cache memory CM2 that determines that the data transfer should be performed transfers the cache line data to the cache memory CM1. If no cache memory is transferred, the shared memory M transfers the corresponding cache line data. Then, the cache memory CM1 which has received the transferred contents of the cache line stores it in an appropriate cache line, returns the requested partial data from the cache line data to the processor P, and ends the processing. To do.

On the other hand, when there is a write request from the processor P, the cache memory C connected to the processor P
If M1 holds the corresponding cache line data and the cache line data does not exist in another cache memory CM2 (this is checked by referring to the tag information), the operation scene of FIG. As shown
The cache memory CM1 rewrites the data of the portion for which a write request has been issued among the corresponding cache line data, and updates the tag information as necessary (for example, stores that the content is different from the shared memory M). .

If the cache memory CM1 connected to the processor P holds the corresponding cache line data and the cache line data exists in another cache memory CM2, FIG.
Cache memory CM1
Requests the other cache memory CM2 to invalidate the corresponding cache line data. Then, when it becomes certain that the request for invalidation is achieved, the data of the portion of the corresponding cache line data for which the write request is made is rewritten, and the tag information is updated as necessary (for example, , That the content is different from the shared memory and that the cache line data is not in another cache memory). Further, the cache memory CM2 which has received the invalidation request checks whether or not there is the corresponding cache line data in the cache line, and if there is, the information indicating that the data held in the tag is invalid. Will be stored.

If the cache memory CM1 connected to the processor P does not hold the corresponding cache line data, as shown in the operation scene of FIG. The CM2 and the shared memory M are requested to transfer and invalidate the cache line data corresponding to the address. The cache memory CM2 that has received the data transfer and invalidation request is
It is determined whether or not the corresponding cache line data exists in the cache line therein, and whether or not the cache line data should be transferred to the requesting cache memory CM1. Then, the cache memory C that determines that the data transfer should be performed
M2 transfers the corresponding cache line data to the cache memory CM1. If no cache memory CM1 is transferred, the shared memory M transfers the corresponding cache line data. At the same time, all the cache memories CM2 having the corresponding cache line data in the cache line are invalidated (that is, the tag stores information indicating that the cache memory is invalid). Further, the cache memory CM1 that has received the transferred cache line data stores it in an appropriate cache line and rewrites the data of the write request portion of the corresponding cache line data, and if necessary, The tag information is updated (for example, it is stored that the content is different from the shared memory and that the cache line data does not exist in another cache memory).

However, if there is a high probability that the read / write request in each processor P can be processed by the operation sequences shown in FIGS. 10 (a) and 11 (a), the parallel cache is used. Therefore, the performance of the entire data processing device can be dramatically improved. However, in reality, the operation sequences shown in FIGS. 10B and 11B and 11C may occur, so that the processor P
If the number of memory cells becomes about 16 to 30, the traffic on the memory bus will increase, and even if the number of processors is increased, the performance of the entire system will not improve.

By the way, when a parallel cache memory is used, a command is issued to the memory bus B in the following three cases.
There are two cases.

In the first case, the programs and data used by a certain processor cannot be stored in the cache memory, and the cache line data is transferred between the cache memory and the shared memory. This is
This corresponds to the operation sequence of 0 (b) and FIG. 11 (c), and in order to reduce this, it is necessary to increase the capacity of the cache memory. This may be realized by the recent high integration of LSI.

The second case is a case where different processors access individual data in a cache line, resulting in access competition for the cache line data. This is shown in FIG.
This corresponds to the operation sequence of FIG. 11B and FIGS. 11B and 11C, and in order to reduce this, it is necessary to reduce the cache line size. This may also be realized by the recent high integration of LSIs.

The third case is a case where the operation sequences of FIGS. 10B and 11B and 11C occur due to competition of accesses from a plurality of processors for certain data. This is an essential phenomenon when a single job is processed in parallel by a plurality of processors and cannot be solved by high integration of LSI.

[0016]

As described above, in the conventional parallel cache memory, when accesses from a plurality of processors compete for certain data, the load on the memory bus increases. Even if the number of processors is increased beyond a certain limit, the performance of the entire system for data processing does not improve.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a parallel cache memory in which the load on the memory bus is reduced and the performance of the entire system for data processing can be improved.

[0018]

A parallel cache memory of the present invention has a cache memory that is connected to a plurality of processors and that is also connected to a shared memory via a memory bus. For the cache memory connected to the processor, it judges whether or not there is cache line data that is the target of the read request in its own cache line, and if there is no cache request data from another cache memory or the shared memory, The target cache line data is acquired, and if each cache memory has the cache line data that is the target of the read request in its own cache memory, the processor that issued the read request sends the same cache line data to the same cache line data. To predict whether or not a write request will be made Have, other cache memory that has received the transfer request for the cache line data from the cache memory coupled to the processor performing the read request,
If it is predicted that the processor will make a write request to its own cache line data, and if it is predicted that a write request will be made, that cache line data will be invalidated, and the cache memory connected to the processor that issued the read request If it is predicted that the processor will make a write request to the cache line data transferred from the cache memory or the shared memory, and if it is predicted that a write request will be made, it is stored that the cache line data is not in another cache memory. I am trying to do it.

[0019]

As a result, according to the present invention, the function of predicting a write request in each cache memory when the processor reads from one address and then writes to the same address, and With the cache line data invalidation function based on this, the write processing can be speeded up even when access from a plurality of processors competes for certain data, and the load on the memory bus can be reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic structure of the embodiment. In the figure, 1 to 3 are processors, and these processors 1 to 3 are connected to cache memories 10 to 12 via 32-bit address lines 4 to 6 and 32-bit data lines 7 to 9, respectively. Further, the cache memories 10 to 12 are connected to a shared memory 14 by a memory bus 13.

To simplify the description, the cache memory 10 will be described. The cache memory 10 includes a register 101, a comparison circuit 102, and a selector 1.
03, cache line 104, control circuit 105, 10
6, comparison circuit 107, selector 108, register 10
9, 110, an arithmetic circuit 111, and a register 112.

The register 101 corresponds to the corresponding processor 1.
When the read request is received from, the address is stored. The cache line 104 is the address storage unit 104.
1, a tag storage unit 1042, and a cache line data storage unit 1043. Also, the cache line 10
The number of entries of 4 is 1024, and the size of each cache line data is 16 bytes. Further, the cache line 104 stores information of A31 to A14 (where the most significant bit is A31 and the least significant bit is A0) among the addresses of the shared memory where the stored cache line data was originally stored. , And has V bits and X bits as tag information. Here, when the V bit is 1, it means that the cache line data is valid, and when the X bit is 1, it means that the cache line data does not exist in other cache memory.

The control circuit 105 determines whether or not the cache line data corresponding to the read request exists in the cache memory 10 by checking the cache line corresponding to the addresses A13 to A4 stored in the register 101. A of the address stored in the selected cache line and the address stored in the register 101
The comparison circuit 102 checks whether or not 31 to A14 are equal, and it is performed depending on the result and whether the value of the V bit of the tag information is 1 or not. For example, in the case of a read request for the address 0x34564 (hexadecimal number), since A13 to A4 are 0x56, the 0x56th (86th decimal) cache line is selected.

Here, when the cache line data corresponding to the read request exists in the cache memory 10, the addresses A3 to A stored in the register 101 are stored.
Select the data of the part corresponding to 2 with the selector 103,
It will be output to the data line 7.

On the other hand, when the cache line data corresponding to the read request does not exist in the cache memory 10, another cache memory 1 is accessed through the memory bus 13.
1, 12 or the shared memory 13 is requested to transfer the cache line data.

The other cache memories 11 and 12 are similar to the cache memory 10 described above.

From this state, the case where the cache memory 10 requests the transfer of the cache line data will be described. The memory bus 13 is composed of 32 bits of address lines, 64 bits of data lines, and a control line (not shown). Is the type of command (transfer of cache line data,
(Invalidation of cache line data, etc.) is included.

Then, the other cache memories 11 and 12
However, when the cache line data transfer request from the cache memory 10 is received, the address information is stored in the respective registers 112.

Then, the control circuit 106 determines whether or not there is cache line data corresponding to the cache line.
The comparison circuit 107 determines. This determination method is performed by the control circuit 10 for a read request from the corresponding processor.
5, exactly the same as the judgment by the comparison circuit 102. Here, having exactly the same circuit twice is a memory access request from a processor directly connected to the cache memory and the transfer of cache line data sent from another cache memory via a bus. This is because the requests can be processed simultaneously.

If there is cache line data corresponding to the cache line, the cache memories 11 and 12
While transmitting the cache line data, the selector 108 is used to select the data corresponding to the addresses A3 to A2 stored in the register 112, and the arithmetic circuit 111 is used to store the data and the register 109. Bitwise logical product is performed between the existing values and then compared with the value stored in the register 110. as a result,
When they match, the V bit is rewritten from 1 to 0.

Further, the cache memory 10 stores the transferred cache line data in an appropriate cache line, and uses the selector 108 to store the data corresponding to the addresses A3 to A2 stored in the register 112. Then, the arithmetic circuit 111 is used to perform a bit-wise AND operation between the data and the value stored in the register 109, and then the logical product is compared with the value stored in the register 110. As a result, when they match,
Write 1 to the X bit.

Next, according to the present invention thus constructed, as shown in FIG. 2, the cache memories CM1 and CM2 are respectively connected to a plurality of processors P, and these cache memories CM1 and CM2 are connected to the memory bus B. The description will be made by substituting the memory M for sharing.

First, a typical pattern in which access from a plurality of processors P competes for certain data is when each processor P reads at that address and writes at that data. . In this series of operations, when the processor P first issues a read request, there is no cache line corresponding to the cache memory CM1 connected to the processor P, and it is necessary to receive transfer of cache line data from another cache memory CM2. In the conventional case, as shown in the operation sequence of FIG.
The cache line data is transferred from M2 to the cache memory CM1 (the same operation sequence as in FIG. 10A described above), and at the next write request, another cache memory CM that originally held that cache line.
The cache line is invalidated for 2. On the other hand, in the cache memory CM1 of the present invention, as shown in the operation sequence of FIG. 4, when the cache line data is first transferred from the cache memory CM2 to the cache memory CM1 by a read request, the cache memory CM2 stores the cache line data. As a result of predicting the write request by the processor P2, the cache line data is also invalidated at the same time. Further, the cache memory CM1 which has received the cache line data also stores that there is no other cache memory having the cache line data as a result of predicting the write request by the processor P. Then, in the next write request, since only the cache memory CM1 holds the cache line, the same operation sequence as that in FIG. 11A described above occurs.

Therefore, the cache memory CM of the present invention
In 1 and CM2, it is possible to omit the invalidation of the cache line data, which has been performed by the write request in the conventional cache memory, and it is possible to reduce the load on the bus.

When the processor P reads a certain address, the write is not always performed to that address thereafter. According to the present invention, whether or not the write is next performed is determined by each cache memory CM1,
The greatest feature is that only the cache memory CM1 or CM2 directly connected to the processor P holds the corresponding cache line data only when it is predicted that the CM2 will cause a write.

Next, a case will be described in which it can be predicted whether the processor that has actually read the data will write to the same address.

In this case, in the parallel logic program, generally, many processes are generated and executed by a large number of processors to speed up the processing. When parallel processing is performed by a plurality of processes in this way, it is necessary to synchronize the processes, such as passing results between the processes. In parallel logic programs, this is achieved by substituting values for variables.

For example, to pass the result from the process P1 to the process P2, a predetermined word A is used as shown in FIG. The word A has an undefined value as an initial state and can store a certain value (in a parallel logic program, this is called a variable).
Then, in the process P1, when the value to be delivered to the process P2 is determined, it is substituted into the word A. Further, the process P2 performs a read operation on the word A, and if the result is not a variable, processes it as the value passed from the process P1. On the contrary, if the result is still a variable, it is necessary to make the execution of P2 wait until the value other than the variable is stored in the word A.

In the parallel logic program, the above operation is realized by the following method.

First, the process P2 on the side of receiving the result is
If word A is read and it is not a variable, word A is not accessed further. However, if it is a variable, it needs to be waited until another result is written to word A by another process, and thus a "variable with pointer" as shown in FIG. 6 is written to word A. This "variable with a pointer" is "the process P pointed to by the pointer when a process writes a value in this word.
Make 2 feasible again ".

Process P1 then returns the result in word A
When writing to, the word A is a variable, a variable with a pointer (that is, the data structure shown in FIG. 4 is formed), or a value other than the variable is already stored by another process. Since there is a possibility of different types, it is necessary to perform a read operation on word A. As a result, when the word A is a variable or a variable with a pointer, the value is written to the word A,
If word A is not a variable, word A is not accessed. .

As described above, in a parallel logic program, after reading a variable or a variable with a pointer, the word is often written, and if not, it is not written. A variable or a variable with a pointer "can be used as the prediction of a write request. This can be determined by whether or not the data has a specific pattern (for example, whether or not the bitwise logical product of the data and a certain constant matches a certain constant).

By predicting the write request by the processor in this way, the parallel cache memory of the present invention uses the memory bus B for the first read by the process P2, but at that time, another cache memory is used. Since the relevant cache line data therein is invalidated, it is not necessary to issue a command to the memory bus B in the subsequent write. Further, the load on the memory bus B is similarly reduced in the subsequent reading and writing to the word A by the process P1. As a result, the write operation to the word A by the processes P2 and P1 can be speeded up, the addition of the memory bus B is reduced, and the overall performance is improved accordingly.

Next, in the symbol processing language, a large amount of data is allocated in the memory during the execution process, and the memory allocated to the unnecessary data is recovered. Among them, a method of using a reference counter is a powerful method for finding unnecessary data. This is a counter that holds how many pointers the data points to, as shown in FIG. In FIG. 7, since the data A is pointed by three pointers, “3” is stored in the reference counter.

With this reference counter, it is necessary to increment or decrement the reference counter of the data pointed to by the pointer by 1 each time the processor newly creates or deletes the pointer.
Therefore, when the reference counter is updated by the processor,
First, reading is performed, and then the updated result is written. On the contrary, the reference count is not read but the write is not performed. Therefore, when the read data is the reference counter, it can be predicted that the next write will be performed. Whether or not the read data is the reference counter can be determined by whether or not the data has a specific pattern.

Next, in the multiprocessor operating system, a part of the memory is used as an area for synchronization processing like a semaphore. In such a synchronous processing area, a write operation is usually performed to the same address following a read operation. Therefore, whether or not the read-requested data is in the synchronous processing area can be used to predict the write operation by the processor, and it can be determined by whether or not the address of the word is within a specific range. .

The present invention is not limited to the above-mentioned embodiments, but can be carried out by appropriately modifying it within the scope of the invention.
For example, as a means for predicting a write after a read by a processor, in the above embodiment, the bit-wise logical product of the data to be read and a constant (value stored in the register 109) is calculated, and another constant is calculated. (Register 11
However, there are various possibilities as a method for determining whether the data has a specific pattern. As an example, a memory of 2 ^N entries × 1 bit is prepared, N bits of the data to be read are used as an address to access this memory, and if the value is 1, a write is performed by the processor. You may predict.

Further, in the above description, whether or not the data to be read is a specific pattern is used as the prediction of writing by the processor. Instead, however, the data to be read and its address are used. May be regarded as data (that is, 64-bit data), and by using the same prediction means as described above, more accurate prediction may be possible. This is effective, for example, in a parallel logic program when an area in which a variable exists is limited to a certain address range. In other words, by determining whether or not it is a variable by matching the case where the data pattern is a variable and "that address is included in the address range in which the variable exists", it is possible to predict the write by the processor. The accuracy can be increased.

Furthermore, when using whether or not an address is within a certain range as a write prediction by the processor, an MMU (Memory Management Unit) for converting a logical address to a physical address is used instead of the above memory, The information regarding the page including the address may include whether or not a write is predicted. Furthermore, in the above description, as a means for the cache memory 10 to predict a write by the processor 1, a bitwise logical product is calculated between the data portion for which a read request has been made and the value stored in the register 109 (operation unit 111 Used), and then compared with the value stored in the register 110. Instead, when the cache memories 11 and 12 transfer the cache line data, the prediction results performed by the cache memories 11 and 12 are also simultaneously calculated. Transfer,
The cache memory 10 may refer to it.

[0051]

According to the parallel cache memory of the present invention, the write processing can be speeded up and the load on the memory bus can be reduced, so that a high-performance data processing system can be realized without changing the number of processors. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing the schematic configuration of an embodiment of a parallel cache memory according to the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a diagram showing an operation sequence of the cache memory when reading and writing certain data in succession in the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing an operation sequence of the cache memory when reading and writing certain data continuously in the embodiment shown in FIG. 1;

5 is a conceptual diagram illustrating synchronization between processes mediated by word A in the embodiment shown in FIG.

FIG. 6 is a conceptual diagram illustrating a wait operation of a process using a variable with a pointer in the embodiment shown in FIG.

FIG. 7 is a conceptual diagram for explaining a reference counter in the embodiment shown in FIG.

FIG. 8 is a configuration diagram showing a conventional memory sharing type multiprocessor.

FIG. 9 is a configuration diagram showing a multiprocessor including a conventional parallel cache memory.

10 is a diagram showing an operation sequence of each cache memory in response to a read request from the processor in the multiprocessor shown in FIG.

11 is a diagram showing an operation sequence of each cache memory in response to a write request of the processor in the multiprocessor shown in FIG.

[Explanation of symbols]

1-3 ... Processor, 4-6 ... Address line, 7-9 ... Data line, 10-12 ... Cache memory, 101, 10
9, 110, 112 ... Registers, 102, 107 ... Comparison circuits, 103, 108 ... Selectors, 104 ... Cache lines, 105, 106 ... Control circuits, 111 ... Arithmetic circuits.

Claims (3)

[Claims] 1. A cache memory connected to a plurality of processors, each of which has a cache memory connected to a shared memory via a memory bus, the cache memory being connected to the processor in response to a read request from the processor. Judge whether or not there is cache line data that is the target of the read request in its own cache line,
If there is no cache line data that is the target of a read request from another cache memory or the shared memory, each cache memory has its own cache line data that is the target of a read request. If there is a read request, the processor that makes the write request for the same cache line data has a means for predicting whether or not there is a request to transfer the cache line data from the cache memory connected to the processor that issued the read request. The other cache memory that received the request predicts whether the processor will make a write request for its own cache line data, and if it predicts that a write request will be made, invalidates the cache line data and connects to the processor that made the read request. Cached The memory predicts whether or not the processor issues a write request to the cache line data transferred from another cache memory or the shared memory. A parallel cache memory characterized by storing nothing. 2. The prediction of whether or not a processor that has issued a read request issues a write request for the same cache line data is performed based on whether or not the target data of the read request has a certain pattern. The parallel cache memory according to claim 1. 3. The prediction of whether or not a processor that has issued a read request issues a write request to the same cache line data is performed based on whether or not the target address of the read request is within a certain range. The parallel cache memory according to claim 1.