JPH10207773A - Bus connecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the traffic of a system bus, and to improve the performance of a system by preventing data whose use frequency is high from being forced out from an input and output cache memory. SOLUTION: A bus connecting device connects a system bus 400 for connecting a processor with a main storage device with an input and output bus 700 for connecting an input and output controller. The bus connecting device is provided with an input and output cache memory 130 and a lead buffer 110. The lead buffer 110 holds data from the system bus 400 at the time of reading miss hit of the input and output cache memory 130.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus connection device, and more particularly to a bus connection device including an input / output cache memory.

[0002]

2. Description of the Related Art It is generally known that a processor repeatedly accesses the same address or an address in the vicinity of the same, so that it is possible to increase the speed by holding once accessed data in a cache memory. In a conventional bus connection device for connecting a system bus and an input / output bus, an input / output cache memory is also provided to temporarily store a copy of data on a main storage device.

A conventional input / output cache memory employs the same configuration as a cache memory for a processor. The input / output cache memory employs a so-called on-demand replacement method in which data is transferred from the main memory when data relating to a request from the input / output bus is not held.

[0004]

In the above-mentioned prior art,
When the data related to the request is not held, the contents in the main storage device are transferred to the input / output cache memory. However, most of the input / output data deals with continuous data, and the same data is repeatedly accessed less frequently than in a processor. Therefore,
When the contents of the I / O cache memory are updated with the same policy as the processor, data that is frequently used is likely to be evicted by data that is not frequently used, increasing the traffic on the system bus and hindering system performance improvement. There was a problem of doing.

It is an object of the present invention to provide a bus connection device including an input / output cache memory which makes use of the properties of input / output data and in which required data is not easily flushed.

[0006]

According to another aspect of the present invention, there is provided an input / output cache memory connected between a main storage device and an input / output device. If a mishit occurs in reading from the device, the data from the main storage device is transferred to the input / output device without updating the contents of the input / output cache memory.

Further, another input / output cache memory of the present invention further includes a read buffer for holding data from the main storage device when a miss occurs in reading from the input / output device.

Further, the bus connection device of the present invention is a bus connection device for connecting a system bus connected to a main storage device and an input / output bus connected to an input / output device, wherein the content of the main storage device is Input and output that transfers data from the main storage device to the input / output device without updating the held content when a mishit occurs in reading from the input / output device. Includes cache memory.

Further, another bus connection device of the present invention is a read buffer for holding data from the main storage device when a miss occurs in the input / output cache memory for reading from the input / output device. Further included.

In another bus connection device according to the present invention, the I / O cache memory updates the contents held therein when a mishit occurs with respect to writing from the I / O device, and then updates the contents. Write the write data from the entry output device.

In another bus connection device of the present invention, the read buffer includes at least one data register for holding data from the main storage device, and an address corresponding to the data held in the data register. At least one address register that holds the data, a determination circuit that determines whether an address related to a read request is stored in the address register, and a selector that selects the contents of the data register according to a result of the determination circuit. And

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a bus connection device according to the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a bus connection device 100 of the present invention is used in an information processing system.
Bus 400 that connects the main storage device 300 with the
And an input / output bus 700 for connecting the input / output control device 500
Connect between The processing device 200 includes a system bus 40
There is at least one on 0. Further, at least one input / output control device 500 exists for each input / output bus. The input / output control device 500 includes the input / output device 60
0 is connected.

The processing device 200 performs processing such as various calculations. The main storage device 300 stores data necessary for processing. The input / output device 600 is, for example, a magnetic disk device or a magnetic tape device, and stores a large amount of data. The input / output control device 500 serves as an adapter for the input / output device 600 and interfaces the input / output bus 700 and the input / output device 600. The input / output control device 500 requests access to the main storage device 300 from the input / output bus 700 via the bus connection device 100 and the system bus 400.

Referring to FIG. 2, the bus connection device 100
Includes an input / output cache 130, a read buffer 110 which is a feature of the present invention, and a multiplexer 120. The input / output cache memory 130 holds a part of the data in the main storage device 300. Read buffer 1
Like the input / output cache memory 130, the input / output cache memory 10 retains a part of the data in the main storage device 300, but has a smaller capacity than the input / output cache memory 130. Further, the multiplexer 120 includes an input / output cache memory 130.
As an input to, one of data from the system bus 400 and data from the read buffer 110 is selected.

Referring to FIG. 3, read buffer 110
Has at least one set of a data register 111 and an address register 112, and holds data on the main storage device 300 and addresses corresponding thereto. These data and address are input via signal lines 101 and 102, respectively.

The read buffer 110 includes a comparator 11 for comparing the address held in the address register 112 with the address accessed via the signal line 102.
3, and when there are a plurality of comparators 113, an OR circuit 114 is further provided.

The selector 115 selects one of the contents of the data register 111 based on the comparison result by the comparator 113. That is, if there is an address register 112 that holds an address that matches the address accessed by the signal line 102,
The contents of the data register 111 corresponding to the signal line 1
03 is output.

The controller 140 receives the comparison result of the signal line 104, and receives the result of the comparison.
Control of each part in.

Address line 40 from system bus 400
1 is connected to the input / output cache memory 130.
A data line 402 from the system bus 400 is connected to the read buffer 110. I / O bus 700
From the input / output cache memory 13
0 and the read buffer 110, and the data line 70
2 is connected to the input / output cache memory 130.

The multiplexer 120 is connected to the system bus 4
00 and the data line 702 of the input / output bus 700
Connect to the data port of

The input / output cache memory 130 has a configuration similar to that of a general processor cache memory, and operates by a store-in (also called write-back) method.

The data register 111 and the address register 112 receive data and addresses from the upper side, that is, from the signal lines 101 and 102, and shift downward each time there is a new input. Therefore, in order to hold the data exceeding the allowable amount, the data and the address held from the oldest are evicted. Such an arrangement is called a first in first out (FIFO) buffer. Here, for convenience of explanation, a buffer managed by the FIFO is assumed, but the present invention is not limited to this, and may be managed by another LRU method or the like.

The number of pairs of the data register 111 and the address register 112 is determined by
Although a number smaller than the number of entries of 30 is sufficient, it is preferable that the number is equal to or larger than the number of input / output control devices 500 connected to the input / output bus 700.

Next, the operation of the embodiment of the bus connection device of the present invention will be described.

From the input / output controller 500 to the input / output bus 70
When an access request to the main storage device 300 is output to 0, it is checked whether the requested data exists in the input / output cache memory 130 or the read buffer 110 in the bus connection device 100. In the read buffer 110, by using the comparator 113, it is checked whether the corresponding address exists.

Referring to FIG. 4, input / output control device 500
If the access request from is a read request, it is determined whether or not the requested data exists in the bus connection device 100 (step S701). Data is read (step S702). Here, when the processing device 200 has a cache memory, data may be read from the cache memory.

The data read from the main storage device 300 is stored in the read buffer 110 together with the address (step S703). Then, the data is returned to the input / output control device 500 that issued the request (step S7).
05). However, in this case, the data read from the main storage device 300 is not stored in the input / output cache memory 130.

If it is determined in step S701 that the requested data exists in the bus connection device 100, the data is read from the input / output cache memory 130 or the read buffer 110 in the bus connection device 100. Then, it is returned to the input / output control device 500 (step S705).

Referring to FIG. 5, input / output control device 500
If the access request is a write request, it is determined whether or not the requested data exists in the input / output cache memory 130 (step S801). A determination is made (step S810). Here, in the present embodiment, the status of each entry of the input / output cache memory is “invalid (“ I ”)”, “coincides with the main storage device, and is shared with another input / output cache memory (“ CS ”). ")" And "not matching the main storage device and not being held in another input / output cache memory (" DE ")".

In step S810, the state becomes "D".
If it is determined that the state is "E", the write data is written to the (own) input / output cache memory as it is (step S815). Then, after the invalidation of the other input / output cache memory is completed, the write data is written to its own input / output cache memory (step S825). In this case, the state of the entry is modified from “CS” to “DE” (step S
826).

If it is determined in step S801 that the requested data does not exist in the input / output cache memory 130, it is further determined whether or not the requested data exists in the read buffer 110 (step S801). S830). If it is determined that the entry exists in the read buffer 110, the corresponding entry in another input / output cache memory is invalidated (step S831). On the other hand, if it is determined that it does not exist in the read buffer 110,
A block including the corresponding data is read from the main storage device 300 (step S841). As a result, the entry in the input / output cache memory 110 is replaced by using the data if it exists in the read buffer 110 and using the data from the main storage device 300 if it does not exist (step S834). That is,
A free entry is created in the input / output cache memory 110, and the data is held in the entry. However, if the state of the entry selected in the replacement is “DE” (step S832), it is necessary to flush the held data to the main storage device 200 before the replacement (step S833).

After replacement is completed, write data is written to the replaced entry (step S8).
35). In this case, the state of the entry is modified to “DE” (step S836).

As described above, in the embodiment of the bus connection device of the present invention, the entry of the I / O cache memory 130 is not replaced even when the I / O cache memory 130 has a mishit at the time of read access. , The read buffer 110 is used. This makes it difficult for frequently used data to be evicted by continuous and non-repeated data transfer such as direct memory access (DMA) transfer.

[0035]

As is apparent from the above description, according to the present invention, in the input / output cache memory, data that is frequently used can be hardly evicted by data that is not frequently used, and traffic on the system bus can be reduced. Can be reduced. Thereby, the performance of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an information processing system to which a bus connection device of the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of a bus connection device according to the present invention.

FIG. 3 is a diagram showing a block diagram of a read buffer in the embodiment of the bus connection device of the present invention.

FIG. 4 is a diagram showing a procedure of a read operation in the embodiment of the bus connection device of the present invention.

FIG. 5 is a diagram showing a procedure of a write operation in the embodiment of the bus connection device of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 bus connection device 110 read buffer 130 input / output cache memory 200 processing device 300 main storage device 400 system bus 500 input / output control device 600 input / output device 700 input / output bus

Claims (6)

[Claims] 1. An input / output cache memory connected between a main storage device and an input / output device, wherein when a read request from the input / output device has a mishit, the mishit occurs. An input / output cache memory which reads data relating to a read request from the main storage device and directly transfers the data to the input / output device without storing the data in the main storage device. 2. A read buffer for holding data relating to the read request read from the main storage device when a mishit occurs in response to a read request from the input / output device. 1. The input / output cache memory according to 1. 3. A bus connection device for connecting a system bus connected to a main storage device and an input / output bus connected to an input / output device, wherein the input / output device retains a part of the contents of the main storage device. An input / output cache memory for transferring data from the main storage device to the input / output device without updating the held content when a mishit occurs in response to a read request from the memory device. Bus connection device. 4. The system according to claim 1, further comprising a read buffer for holding data from said main storage device when a miss occurs in said input / output cache memory in response to a read request from said input / output device. Item 3. The bus connection device according to item 3. 5. The I / O cache memory, when a mishit occurs in response to a write request from the I / O device, updates the held content and writes the write data from the I / O device. The bus connection device according to claim 4, wherein: 6. The read buffer, at least one data register for holding data from the main storage device, at least one address register for holding an address corresponding to the data held in the data register, and reading. 5. A circuit according to claim 4, further comprising: a determination circuit for determining whether an address relating to the request is held in said address register; and a selector for selecting the contents of said data register in accordance with a result of said determination circuit.
The bus connection device as described in the above.