JPH04357542A - Address converter - Google Patents

Abstract

PURPOSE:To carry out the address conversion at a high speed by improving a hit ratio by a random replacing algorithm system address converting buffer (TLB). CONSTITUTION:A TLB registering content holding register 4 to store temporarily the content to be renewed and registered as the entry of a TLB 1, and a TLB replacing entry holding register 5 to store temporarily the content before the renewing of the entry of the TLB 1 are provided apart from the TLB 1, and the content stored in the TLB registering content holding register 4 and the TLB replacing entry holding register 5 is handled in the same way as the entry of the TLB 1 and the address conversion is performed. By a TLB hitting signal 11 or register hitting signals 12-1 and 12-2, a physical address 9-7 corresponding to a logical address 8-1 through tristate buffers 7-1, 7-2 and 7-3 is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation device in a virtual memory system, and more particularly to an address translation device equipped with an address translation buffer in which entries are selectively updated according to a random replacement algorithm.

0002

2. Description of the Related Art In general, in a virtual memory system, pairs of logical addresses and physical addresses are stored in an address translation buffer TLB (Translation Look
A method is adopted in which the data is registered in a side buffer). For a logical address registered in the TLB, a corresponding physical address can be obtained at high speed. If the TLB fails to perform address translation (TLB miss), address translation is performed by referring to a table in the main memory, and the pair of logical address and physical address that is the translation result is registered in the TLB. Prepare for the next address translation.

FIG. 7 is a flowchart showing the process of converting a logical address into a physical address in a conventional address converting device. First, in step 711 a logical address is provided. Then, in step 712, the logical address is T
Check whether there is a hit based on the contents of LB. If TL
If there is a hit in B, the process advances to step 713 and reads the physical address from the TLB. The read physical address is used to access the main memory or cache memory. If there is no hit in the TLB, the process advances to step 714 and address translation is performed by referring to a table in the main memory. Thereafter, in step 715, the pair of logical address and physical address that is the translation result is registered in the TLB. Then, the process returns to step 711 and the TLB
The physical address is obtained by accessing the TLB again using the missed logical address. In this way, when there is a miss in the TLB, it usually takes several tens of times longer than when there is a hit, resulting in a decrease in program execution speed.

0004

[Problems to be Solved by the Invention] As a replacement algorithm for selecting an entry to be rewritten when updating the TLB, for example, LRU (Least Recently
Used) algorithm, FIFO (Fast In
(Fast Out) algorithm and random algorithm. Comparing these three algorithms, the hit rate increases in the order of random, FIFO, and LRU, but the amount of hardware increases in the same order. In other words, when a random replacement algorithm is adopted, a problem arises in that the TLB hit rate is lower than that of other replacement algorithms. When LRU replacement algorithm or FIFO replacement algorithm is adopted, TLB
The problem arises that the circuit becomes complicated and the amount of hardware increases, making it impossible to increase the operating frequency.

Now, T of the random permutation algorithm method
As a case of lowering the hit rate in LB,
For example, there are the following two cases. (1) A TLB miss occurs immediately after the translation of logical address a is performed at entry A in the TLB, and entry A is rewritten when registering a new entry in the TLB. A TLB miss occurs when accessing. (2) If there is a TLB miss at logical address b, the entry B corresponding to logical address b is
After registering at logical address b, the next TLB miss occurs and entry B is rewritten, resulting in a TLB miss occurring the next time logical address b is accessed.

An example of the above (1) will be explained in detail. For example, suppose that a subroutine call occurs from the main program while a certain program is being executed. If the information on the page where the contents of the main program being executed are written is registered in the TLB, but the information on the page where the contents of the jump destination subroutine are written is not registered in the TLB, Steps 714, 7 shown in FIG.
15, the pair of logical address and physical address for the subroutine page must be registered in the TLB. At this time, since the TLB replacement algorithm is a random algorithm, entries storing information for pages of the main program may be rewritten. In this case, when returning to the main program from the subroutine, the TLB
Since there is no corresponding entry in the TLB address, a TLB miss occurs, and address translation is performed again in steps 714 and 715 shown in FIG. 7, resulting in a large drop in performance.

As an example of the above (2), the above (1)
In example (1), this corresponds to the case where the page where the contents of the main program are first written causes a TLB miss, and as in example (1), there is a large drop in performance.

Conventionally, it has not been possible to solve the above-mentioned problem of the random replacement algorithm that the hit rate is low, so the TL of the LRU replacement algorithm or the FIFO replacement algorithm was
B was often adopted.

[0009] In view of the above-mentioned state of the prior art, the present invention
The present invention aims to speed up address translation by improving the hit rate while employing a TLB based on a random permutation algorithm, and to provide an address translation device that simultaneously realizes high-speed translation and small circuit scale.

0010

[Means for Solving the Problems] In order to solve the above-mentioned problems, the address translation device of the present invention, in a TLB based on a random replacement algorithm, saves the contents of entries in the TLB before the update, which would conventionally be erased by rewriting. Register for temporary storage and/or the TL
A register is provided separately from the TLB to temporarily store the content to be updated and registered as an entry in B, and the content stored in this register is accessed for address translation in the same way as the TLB entry. It is something.

Specifically, in the invention of claim 1, a plurality of pairs of logical addresses and physical addresses corresponding to the logical addresses are each registered as an entry, and the entries are selectively replaced according to a random replacement algorithm. The TLB that is updated and the TLB that is updated when the TLB is updated.
TLB in which the contents of the entry before the update are stored
A configuration including a replacement entry holding register and an address translation means for converting a given logical address into a physical address based on the contents stored in the plurality of TLB entries and the TLB replacement entry holding register is adopted. In particular, in the invention of claim 2, the TLB replacement entry holding register is configured as a first-in first-out FIFO register.

[0012] In the invention of claim 3, a TLB registration content holding register in which pairs of logical addresses and physical addresses corresponding to the logical addresses are sequentially stored, and a plurality of pairs of other logical addresses and the other logical addresses. The corresponding physical addresses are each registered as an entry in the TLB.
B A TLB whose entries are selectively updated according to a random replacement algorithm with the contents stored in the registered contents holding register, and a TLB that stores a given logical address in the TLB.
A configuration is adopted that includes address conversion means for converting into a physical address based on a plurality of entries of B and the contents stored in the TLB registered contents holding register. Particularly, in the invention of claim 4, the TLB registered content holding register is configured as a first-in first-out FIFO register.

The invention of claim 5 is a combination of the invention of claim 1 and the invention of claim 3, in which pairs of logical addresses and physical addresses corresponding to the logical addresses are stored sequentially. A TLB registered content holding register, multiple pairs of other logical addresses, and physical addresses corresponding to the other logical addresses are each registered as an entry. A TLB in which entries are selectively updated according to a random replacement algorithm with the contents stored in the registered content holding register, and a TLB in which the contents of the TLB entry before the update are stored when the TLB is updated. A replacement entry holding register and a given logical address are stored in multiple entries in the TLB as well as in the TLB.
This configuration employs a configuration including a registered content holding register and an address translation means for converting into a physical address based on the content stored in the TLB replacement entry holding register. Particularly, in the invention of claim 6, the TLB registered content holding register and the TLB replacement entry holding register are configured as first-in, first-out type FIFO registers.

[0014]

[Operation] According to the invention of claim 1, the T
The contents of the LB entry before updating are stored in the TLB replacement entry holding register, and the entry is also stored in the TLB
It is subject to address translation like other entries in . Therefore, if the logical address to be translated is in the last updated entry, it will be hit in the TLB replacement entry holding register, and address translation can be performed at high speed in the same way as in the case of a hit in the TLB. In particular, according to the second aspect of the invention, since a plurality of entries can be stored in the TLB replacement entry holding register, the hit rate is further improved.

According to the third aspect of the invention, a pair of a logical address and a physical address to be updated and registered as an entry in the TLB is temporarily stored in the TLB registration contents holding register, and the contents of the TLB registration contents holding register are also stored in the TLB registration contents holding register.
Like the B entry, it is subject to address translation, improving the hit rate. Since the TLB registered content holding register is actually registered in the TLB at the time of the next TLB update, the content will be transferred to the TLB when the next update is performed.
B It will not be deleted from the entry. Furthermore, if the logical address to be translated has content that was updated two times before, a TLB hit will always occur, and address translation can be performed at high speed. In particular, according to the fourth aspect of the invention, the content to be updated and registered in the TLB is stored in the FIFO register, and at the same time, the content to be evicted from the FIFO register is registered in the TLB. Moreover, FI
Since a plurality of pairs of logical addresses and physical addresses can be stored in the TLB registration content holding register consisting of the FO register, the hit rate is further improved.

According to the invention of claim 5, the pair of logical address and physical address to be updated and registered as a TLB entry is temporarily stored in the TLB registration content holding register, and the pair of the TLB entry updated immediately before is stored temporarily in the TLB registration content holding register. The contents before the update are temporarily stored in the TLB replacement entry holding register, and the contents stored in both registers are also stored in the TLB replacement entry holding register.
Since it is subject to address translation like the LB entry, the hit rate improves. In particular, according to the sixth aspect of the invention, a plurality of pairs of logical addresses and physical addresses can be stored in each of the TLB registration content holding register and the TLB replacement entry holding register, so that the hit rate is further improved.

[0017]

【Example】

[Embodiment 1] A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an address translation device showing a first embodiment of the present invention. In the figure, 1 is an address translation buffer (TLB), which is composed of a logical address storage section 1-1 and a physical address storage section 1-2. Further, TLB 1 of this embodiment is a fully associative method, and the replacement algorithm is a random replacement method. Logical address storage section 1-1 is a content addressable memory (CAM)
The physical address storage section 1-2 is composed of a random access memory (RAM). Further, in this embodiment, as an example of realizing the random replacement method, the entry to be written is determined by the TLB write entry instruction signal 10 obtained by decoding the output of the counter 2, which is incremented by one every clock, by the decoder 3. 5 is a TLB replacement entry holding register, 5-1 stores the contents of the logical address storage section 1-1 of the entry to be replaced, and 5-2 stores the contents of the physical address storage section 1-2 of the entry. (Hereinafter, the TLB replacement entry holding registers 5-1 and 5-2 will be simply referred to as registers 5-1 and 5-2.) A comparator 6 compares the logical address stored in the register 5-1 with the input logical address; 7
-1 indicates that if a match is detected in comparator 6, register 5-
7-2 is a tri-state buffer that outputs the physical address stored in TLB 1, and 7-2 is a tri-state buffer that outputs the physical address read from the physical address storage section 1-2 when there is a hit in TLB 1. . Further, 13 is a selector that selects a logical address to be input to the logical address storage section 1-1 according to the value of the TLB write signal 14, and in the case of a conversion operation, selects the logical address 8-1 to be converted, In the case of a write operation to TLB 1, the logical address 8-2 to be written is selected.

When performing a conversion operation using TLB 1,
The logical address 8-1 to be translated is input to the TLB 1 as the logical address 8-11 selected by the selector 13. Then, a search is made to see if a logical address that matches the input logical address 8-11 is stored in the logical address storage section 1-1. At the same time, register 5-
The comparator 6 compares the logical address 8-4 stored in 1 and the input logical address 8-1. T
If there is a hit in LB 1, from that TLB to TLB
A hit signal 11 is output, and the physical address storage section 1-2
Physical address 9-5 read from TLB hit signal 11 is output as physical address 9-6 via tri-state buffer 7-2. Also, TL
B When there is a hit in the replacement entry holding register 5, the register hit signal 12 is output from the comparator 6, and the physical address 9-4 stored in the register 5-2 is transferred to the tri-state buffer 7 according to the register hit signal 12. -1 and is output as a physical address 9-6.

If there is no matching logical address in either TLB 1 or register 5-1 (if there is a miss), address translation is performed by referring to a table in the main memory. Then, the pair of logical address 8-2 and physical address 9-2 that is the conversion result is TL
Registered in B1. The logical address 8-2 is selected by the selector 13 in response to the TLB write signal 14 and written into the logical address storage section 1-1 as the logical address 8-11. Further, the physical address 9-2 resulting from the conversion is written into the physical address storage section 1-2. At that time,
TLB write entry instruction signal 10 in TLB 1
The logical address 8-3 of the entry indicated by is the register 5.
-1, and the corresponding physical address 9-3 is written to register 5-2. Then, by accessing TLB 1 again with the logical address that missed earlier, this time, in order to hit TLB 1, physical address 9-
6 is obtained.

Furthermore, if the logical address 8-1 to be converted next is the logical address that was in the previously rewritten entry of TLB 1, the logical address 8-4 stored in the register 5-1 is , so T
A physical address 9-4 corresponding to the logical address hit in the LB replacement entry holding register 5 is output from the register 5-2 as a physical address 9-6 via the tri-state buffer 7-1.

FIG. 2 is a flowchart showing the conversion process from a logical address to a physical address in the address conversion device of the first embodiment. First, in step 111 a logical address is provided. Then, in step 112, it is checked whether the logical address matches the contents of the TLB. If there is a hit in TLB, proceed to step 113 and T
A physical address is read from LB. If T.L.B.
If there is no hit, the process proceeds to step 114 to check whether there is a hit based on the contents of the TLB replacement entry holding register. If there is a hit in the TLB replacement entry holding register, the physical address is read from the TLB replacement entry holding register in step 115. Step 1
If there is also a miss in the TLB replacement entry holding register in step 14, the process proceeds to step 116, and address translation is performed by referring to a table in the main memory. After the address translation, in step 117 the content of the TLB replacement entry is written to the TLB replacement entry holding register and saved, and then in step 118 the pair of the translated logical address and physical address (
(obtained in step 116) is registered in the TLB entry. Then, the process returns to step 111 and the physical address is obtained by accessing the TLB using the logical address that missed the TLB earlier. However, the hit determination in step 112 and step 114 can be executed simultaneously by using the configuration shown in FIG.

Comparator 6 and tri-state in FIG.
The configuration of the buffers 7-1 and 7-2 and the operations of steps 112 to 115 in FIG. An address conversion means for converting into an address is configured.

As described above, in the address translation device of this embodiment, even for an entry in the TLB that has been rewritten, the contents of the entry are stored in the TLB replacement entry holding register until the next write to the TLB is performed. Since it is held, it is possible to perform address translation in the same way as when there is a hit in the TLB. In other words, even if a subroutine call is made from the main program and the TLB entry of the page corresponding to the main program is rewritten, when the main program returns again, address translation can be performed using the TLB replacement entry holding register. can be executed quickly.

Further, in the TLB 1 of the embodiment shown in FIG. 1, a logical address storage section 1-1 and a physical address storage section 1-
2, the logical address storage section 1-1
When registering and using not only the logical address but also the process number and valid bits, or when registering the physical address storage part 1
-2 When registering page attributes and using them, TL
B By configuring the replacement entry holding register 5 to store them as well, it is possible to easily improve the functionality of the address translation device.

Furthermore, by configuring the TLB replacement entry holding register 5 as a first-in, first-out type FIFO register, it is possible to hold a plurality of TLB replacement entries in a FIFO manner, and each TLB replacement entry stored in the register 5-1 If the logical address of the entry is compared with the logical address of the input, and if there is a hit, the physical address of the hit entry is read out from the register 5-2, the hit rate in the address translation device can be further improved.

[Embodiment 2] A second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of an address translation device showing a second embodiment of the present invention. In the figure, 1 is an address translation buffer (TLB), which is composed of a logical address storage section 1-1 and a physical address storage section 1-2. Further, TLB 1 of this embodiment is a fully associative method, and the replacement algorithm is a random replacement method. The logical address storage section 1-1 is composed of a content addressable memory (CAM), and the physical address storage section 1-2 is composed of a random access memory (RA).
M). Further, in this embodiment, as an example of realizing the random replacement method, the entry to be written is determined by the TLB write entry instruction signal 10 obtained by decoding the output of the counter 2, which is incremented by one every clock, by the decoder 3. 4 is a TLB registration content holding register, 4-1 stores the content to be written to the logical address storage section 1-1, and 4-2 stores the content to be written to the physical address storage section 1-2. Content holding register 4-
1 and 4-2 are simply referred to as registers 4-1 and 4-2. )
. 6 is a comparator that compares the logical address stored in register 4-1 with the input logical address, and 7-1 is stored in register 4-2 when a match is detected by comparator 6. 3-state output that outputs physical address
Buffer 7-2 is a tri-state buffer that outputs the physical address read from physical address storage section 1-2 when there is a hit in TLB 1. Also, 13
is a selector that selects the logical address to be input to the logical address storage section 1-1 according to the value of the TLB write signal 14, and in the case of a conversion operation, selects the logical address 8-1 to be converted and writes it to TLB 1. In the case of the write operation, the logical address 8-3 to be written is selected.

[0027] When performing a conversion operation using TLB 1,
The logical address 8-1 to be translated is input to the TLB 1 as the logical address 8-11 selected by the selector 13. Then, a search is made to see if a logical address that matches the input logical address 8-11 is stored in the logical address storage section 1-1. At the same time, register 4-
The comparator 6 compares the logical address 8-3 stored in 1 and the input logical address 8-1. If there is a hit in TLB 1, physical address 9-4 is output from physical address storage 1-2 as physical address 9-5 via tri-state buffer 7-2 in accordance with TLB hit signal 11. Also, TL
B When there is a hit in the registered content holding register 4, the physical address 9-3 stored in the register 4-2 is transferred as the physical address 9-5 via the tri-state buffer 7-1 according to the register hit signal 12. Output.

If there is no matching logical address in either TLB 1 or register 4-1, address translation is performed by referring to a table in the main memory. The converted contents are not immediately registered in TLB 1; first, TLB 1 contains the logical address 8-3 stored in register 4-1 and the physical address 9-3 stored in register 4-2. , TLB is written to the entry indicated by the write entry instruction signal 10. The converted logical address 8-2 is stored in register 4-1, and the corresponding physical address 9-2 is stored in register 4-2.
are written respectively. When TLB 1 is accessed again using the previously missed logical address, the logical address 8-3 stored in register 4-1 matches the physical address 9-3 stored in register 4-2.
3 is output as physical address 9-5 via tristate buffer 7-1. Then, when the next TLB miss occurs, register 4-1 and register 4-
The contents of TLB 2 are registered in TLB 1.

FIG. 4 is a flowchart showing the conversion process from a logical address to a physical address in the address conversion device of the second embodiment. First, in step 311 a logical address is provided. Then, in step 312, it is checked whether the logical address matches the contents of the TLB. If there is a hit in TLB, proceed to step 313 and TLB.
A physical address is read from LB. If T.L.B.
If there is no hit, the process proceeds to step 314, where it is checked whether there is a hit based on the contents of the TLB registered content holding register. If there is a hit in the TLB registered content holding register, the process advances to step 315 and the physical address is read from the TLB registered content holding register. T in step 314
If there is also a mistake in the LB registration content holding register, the process proceeds to step 316, and address translation is performed by referring to a table in the main memory. After the address translation, the contents of the TLB registered content holding register are written to the TLB in step 317, and then the translated pair of logical address and physical address (obtained in step 316) is registered in the TLB in step 318. Register in content holding register. Then, the process returns to step 311 and accesses this address translation device using the logical address that caused the TLB miss earlier. At this time, there is a miss in the TLB, but a hit in the TLB registered content holding register and a physical address is obtained. However, the hit determination in step 312 and step 314 can be executed simultaneously by using the configuration shown in FIG.

Comparator 6 and tri-state in FIG.
The configuration of the buffers 7-1 and 7-2 and the operations of steps 312 to 315 in FIG. An address conversion means for converting into an address is configured.

As described above, in the address translation device of this embodiment, the pair of logical address and physical address obtained immediately before is actually registered in the TLB at the time of the next TLB update. Since the content is not deleted from the TLB entry when the next update is performed, if the logical address to be translated is the content that was updated two times before, it will always be a TLB hit and the address translation will be performed at high speed. be able to.

Further, in the TLB 1 of the embodiment shown in FIG. 3, the logical address storage section 1-1 and the physical address storage section 1-
2, the logical address storage section 1-1
When registering and using not only the logical address but also the process number and valid bits, or when registering the physical address storage part 1
-2 When registering page attributes and using them, TL
B. By configuring the registered content holding register 4 to store them as well, it is possible to easily improve the functionality of the address translation device.

Furthermore, TLB registration content holding register 4
By configuring the 4-1 as a first-in, first-out FIFO register, it is possible to hold multiple pairs of logical addresses and physical addresses in the FIFO format, and each logical address in register 4-1 is compared with the input logical address to detect a hit. Then, store the corresponding physical address in register 4-2.
If the configuration is such that reading is performed from , the hit rate in the address translation device will further improve.

[Embodiment 3] A third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram of an address translation device showing a third embodiment of the present invention. In the figure, 1 is an address translation buffer (TLB), which is composed of a logical address storage section 1-1 and a physical address storage section 1-2. Further, TLB 1 of this embodiment is a fully associative method, and the replacement algorithm is a random replacement method. The logical address storage section 1-1 is composed of a content addressable memory (CAM), and the physical address storage section 1-2 is composed of a random access memory (RA).
M). Further, in this embodiment, as an example of realizing the random replacement method, the entry to be written is determined by the TLB write entry instruction signal 10 obtained by decoding the output of the counter 2, which is incremented by one every clock, by the decoder 3. 4 is a TLB registration content holding register, 4-1 stores the content to be written to the logical address storage section 1-1, and 4-2 stores the content to be written to the physical address storage section 1-2. Content holding register 4-
1 and 4-2 are simply referred to as registers 4-1 and 4-2. )
. 5 is a TLB replacement entry holding register; 5-
1 stores the contents of the logical address storage section 1-1 of the entry to be replaced, and 5-2 stores the contents of the physical address storage section 1-2 (hereinafter, TLB replacement entry holding registers 5-1, 5- 2 simply as register 5-1,
It is called 5-2. ). 6-1 is a comparator that compares the logical address stored in register 4-1 with the input logical address, and 6-2 is a comparator that compares the logical address stored in register 5-1 with the input logical address. 7-1 is a tri-state buffer that outputs the physical address stored in register 4-2 when a match is detected by comparator 6-1, 7-2 is a hit in TLB 1 A tri-state buffer 7-3 outputs the physical address read from the physical address storage section 1-2 when a match is detected by the comparator 6-2, and stores the physical address in the register 5-2. This is a tri-state buffer that outputs the physical address of the current address. In addition, 13 is a TLB which stores the logical address input to the logical address storage unit 1-1.
According to the value of the write signal 14, select the logical address 8-1 to be translated in case of a translation operation and write TLB 1
In the case of a write operation to the logical address 8-
This is a selector for selecting 3.

[0035] When performing a conversion operation using TLB 1,
The logical address 8-1 to be translated is input to the TLB 1 as the logical address 8-11 selected by the selector 13. Then, a search is made to see if a logical address that matches the input logical address 8-11 is stored in the logical address storage section 1-1. At the same time, register 4-
The comparator 6-1 compares the logical address 8-3 stored in register 5-1 with the input logical address 8-1, and the logical address 8-5 stored in register 5-1 and the input logical Comparison with address 8-1 is performed by comparator 6-2. If there is a hit in TLB 1, physical address 9-6 is output from physical address storage 1-2 as physical address 9-7 via tri-state buffer 7-2 in accordance with TLB hit signal 11. In addition, when there is a hit in the TLB registered content holding register 4, the physical address 9-3 stored in the register 4-2 is changed according to the register hit signal 12-1.
It is output as a physical address 9-7 via a tri-state buffer 7-1. Furthermore, if there is a hit in TLB replacement entry holding register 5, register 5-
According to the register hit signal 12-2, the physical address 9-5 stored in the tri-state buffer 7
-3 and is output as a physical address 9-7.

TLB 1 and registers 4-1 and 5-1
If there is no logical address that matches any of them, address translation is performed by referring to a table in the main memory. Then, registration of the converted logical address 8-2 and physical address 9-2 is performed as follows. First, the logical address 8-4 of the entry indicated by the TLB write entry instruction signal 10 is written to the register 5-1, and the physical address 9-4 is written to the register 5-2. Next, the logical address 8-3 stored in the register 4-1 is the TLB write signal 1.
4, the physical address 9-3 selected by the selector 13 and stored in the logical address storage section 1-1 and the register 4-2 is written into the physical address storage section 1-2. Furthermore, the logical address 8-2 of the conversion result executed by referring to the table in the main memory is written to the register 4-1, and the corresponding physical address 9-2 is written to the register 4-2, and the registration operation is performed. finish.

FIG. 6 is a flowchart showing the conversion process from a logical address to a physical address in the address conversion device of the third embodiment. First, in step 511 a logical address is provided. Then, in step 512, it is checked whether the logical address matches the contents of the TLB. If there is a hit in TLB, proceed to step 513 and TLB.
Read the physical address from LB. If there is no hit in the TLB, the process advances to step 514 to check whether there is a hit in the contents of the TLB registered content holding register. If there is a hit in the TLB registered content holding register, the process advances to step 515 and the physical address is read from the TLB registered content holding register. If there is no hit in the TLB registered content holding register, the process advances to step 516 to check whether there is a hit in the contents of the TLB replacement entry holding register. If there is a hit in the TLB replacement entry holding register, step 51
Proceed to step 7 to read the physical address from the TLB replacement entry holding register. If the TLB replacement entry holding register also fails in step 516, step 51
Proceeding to step 8, address conversion is performed by referring to a table in the main memory. After the address conversion, the contents of the TLB replacement entry are written to the TLB replacement entry holding register in step 519 and saved, and then the contents of the TLB registered contents holding register are written to the TLB in step 520. Then, in step 521, the translated logical address/physical address pair (obtained in step 518) is written into the TLB registration content holding register. Then step 511 again
Returning to , the physical address is obtained by accessing this address translation device with the logical address that missed the TLB earlier. However, the hit determinations in steps 512, 514, and 516 can be executed simultaneously by using the configuration shown in FIG.

The configurations of comparators 6-1, 6-2 and tristate buffers 7-1, 7-2, 7-3 in FIG. 5 and the operations of steps 512 to 517 in FIG. An address conversion means is configured to convert a logical address into a physical address based on a plurality of entries of TLB 1 and the contents stored in TLB registered content holding register 4 and TLB replacement entry holding register 5.

As described above, in the address translation device of this embodiment, the TLB entry that was replaced at the time of the previous update is also subject to address translation in the same way as the entries in the TLB. If it is in an updated entry, address translation can be performed as quickly as when there is a hit in the TLB, and the pair of logical address and physical address written just before is actually registered in the TLB. This is when the next TLB is updated, and when the next update is performed, the contents will be updated to the TLB.
Since it is not deleted from the B entry, if the logical address to be translated has contents that were updated two times before, it will always result in a TLB hit, and address translation can be performed at high speed.

Further, in the TLB 1 of the embodiment shown in FIG. 5, a logical address storage section 1-1 and a physical address storage section 1-
2, the logical address storage section 1-1
When registering and using not only the logical address but also the process number and valid bits, or when registering the physical address storage part 1
-2 When registering page attributes and using them, TL
B By configuring the registration content holding register 4 and the TLB replacement entry holding register 5 to also store them, it is possible to easily improve the functionality of the address translation device.

Furthermore, TLB registration content holding register 4
and TLB By configuring the replacement entry holding register 5 as a first-in, first-out FIFO register, the FIF
It is possible to hold multiple pairs of logical addresses and physical addresses using the O method, and the logical addresses stored in registers 4-1 and 5-1 are compared with the input logical address, and if there is a hit, it is handled accordingly. If the configuration is such that the physical address to be read is read from the registers 4-2 and 5-2, the hit rate in the address translation device is further improved.

[0042]

[Effects of the Invention] As explained above, according to the invention of claim 1, even though the random permutation algorithm type TLB is adopted, when the TLB is updated, the content of the TLB entry before the update is temporarily saved. A TLB replacement entry holding register to be stored is provided separately from the TLB, and the TLB
The contents stored in the replacement entry holding register are stored in the TLB.
Since we have adopted a configuration in which address translation is performed by treating the entry in the same way as the entry in address translation is faster. Therefore, it is possible to realize an address translation device that simultaneously satisfies high-speed translation and small circuit scale. According to the invention of claim 2, the TLB
The replacement entry holding register is a first-in, first-out FIFO.
Since it is composed of registers, multiple entries can be stored in the TLB replacement entry holding register, further improving the hit rate.

According to the invention of claim 3, although the TLB based on the random permutation algorithm is adopted, the TLB
A TLB registered content holding register is provided separately from the TLB to temporarily store the content to be updated and registered as an entry in the TLB, and the content stored in the TLB registered content holding register is treated in the same way as a TLB entry to perform address translation. This configuration improves the hit rate by hitting the TLB registered content holding register.
Address translation is faster. Therefore, it is possible to realize an address translation device that simultaneously satisfies high-speed translation and small circuit scale. According to the invention of claim 4, since the TLB registration content holding register is constituted by a first-in, first-out type FIFO register, it is possible to store a plurality of pairs of logical addresses and physical addresses in the TLB registration content holding register. This will further improve your hit rate.

According to the invention of claim 5, even though the TLB based on the random permutation algorithm is adopted, the TLB
A TLB registration content holding register that temporarily stores the contents to be updated and registered as an entry in the TLB, and a TLB replacement entry holding register that temporarily stores the contents of the TLB entry before updating are provided separately from the TLB.
Since we have adopted a configuration in which the contents stored in the LB registered content holding register and the TLB replacement entry holding register are treated in the same way as TLB entries and address translation is executed, hits in the TLB registered content holding register and TLB replacement entry Both hits in holding registers improve the hit rate and speed up address translation. Therefore, it is possible to realize an address translation device that simultaneously satisfies high-speed translation and small circuit scale. According to the invention of claim 6, the TLB, the registered content holding register and the TLB
LB Replacement entry holding register is first-in-first-out F
Since it is composed of IFO registers, it is possible to store a plurality of pairs of logical addresses and physical addresses in both registers, thereby further improving the hit rate.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a first embodiment of an address translation device of the present invention.

FIG. 2 is a flowchart showing a logical address to physical address conversion process in the address translation device of FIG. 1;

FIG. 3 is a configuration diagram of a second embodiment of the address translation device of the present invention.

4 is a flowchart showing a logical address to physical address translation process in the address translation device of FIG. 3; FIG.

FIG. 5 is a configuration diagram of a third embodiment of the address translation device of the present invention.

6 is a flowchart showing a logical address to physical address translation process in the address translation device of FIG. 5. FIG.

FIG. 7 is a flowchart showing a logical address to physical address translation process in a conventional address translation device.

[Explanation of symbols]

1...TLB (address translation buffer) 2...Counter 3...Decoder 4...TLB Registration content holding register 5...TLB replacement entry holding register 6...Comparator (address translation means) 7...Tri-state buffer (address translation means) 8
...Logical address 9...Physical address 10...TLB Write entry instruction signal 11...TLB
Hit signal 12...Register hit signal 13...Selector 14...TLB write signal

Claims (6)

[Claims] 1. An address translation buffer in which a plurality of pairs of logical addresses and physical addresses corresponding to the logical addresses are each registered as an entry, and the entries are selectively updated according to a random replacement algorithm; a TLB in which the contents of the entry before the update are stored; a replacement entry holding register; a plurality of entries of the address translation buffer; and the TL;
B. An address conversion device comprising: address conversion means for converting a given logical address into a physical address based on the contents stored in a replacement entry holding register. 2. The address translation device according to claim 1, wherein the TLB replacement entry holding register is a first-in first-out FIFO register. 3. A TLB in which pairs of logical addresses and physical addresses corresponding to the logical addresses are sequentially stored; a registered content holding register; and a plurality of pairs of other logical addresses and physical addresses corresponding to the other logical addresses. are each registered as an entry, and at the time of said storage, said entry is selectively updated according to a random replacement algorithm with the content stored in said TLB registered content holding register before said storage. , a plurality of entries of the address translation buffer and the T
LB: An address translation device comprising address translation means for translating a given logical address into a physical address based on the contents stored in the registered content holding register. 4. The address translation device according to claim 3, wherein the TLB registration content holding register is a first-in, first-out FIFO register. 5. A TLB in which pairs of logical addresses and physical addresses corresponding to the logical addresses are sequentially stored; a registered content holding register; and a plurality of pairs of other logical addresses and physical addresses corresponding to the other logical addresses. are each registered as an entry, and at the time of said storage, said entry is selectively updated according to a random replacement algorithm with the content stored in said TLB registered content holding register before said storage. and a TLB in which the contents of the entry before the update are stored at the time of the update; a replacement entry holding register; a plurality of entries of the address translation buffer and the TLB;
An address translation device comprising: a registered content holding register; and address translation means for converting a given logical address into a physical address based on the content stored in the TLB replacement entry holding register. 6. The address translation device according to claim 5, wherein the TLB registration content holding register and the TLB replacement entry holding register are first-in, first-out FIFO registers.