JPS6324337A - Cache memory managing system - Google Patents

Abstract

PURPOSE:To avoid a purge operation of invalidated data from a cache memory, by confirming a coincidence of a generation number which has been read out of the cache memory, and a generation number which has been read out of a conversion index buffer TLB, at the time of an access to the cache memory. CONSTITUTION:A computer system executes an access to a main memory 13 by using a virtual address. A converter converts its address to a physical address. Information required for its conversion is stored in a PDIR. A TLB 23 stores a limited number of virtual address/physical address converting information which has been given by the PDIR. When a requested virtual address is not contained in the TLB 23, it is replaced with some existing TLB entry by the converter. In order to check a cache hit or not, the TLB entry which has been retrieved newly in addition to a physical address, and a PGN are also compared, and a coincidence of a generation number to one entry and a generation number which has been read out of the TLB 23 is confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a cache memory management method for improving access time to cache memory in computer system buttons using virtual addresses [Prior art and problems thereof] Most modern computer systems include a central processing unit (CPU) and main memory. The speed at which a CPU can decode and execute instructions and process data has long been such that instructions and operands can be transferred from main memory to the CPU.
It was faster than it could be transferred to U. In an attempt to solve the problems caused by this mismatch, many computers throw a cache memory, or buffer, between the CPU and main memory.

Cache memory is a small, high-speed buffer memory that uses C
It is used to temporarily hold a portion of the main memory contents that are expected to be used by the PU in the near future. The primary purpose of cache memory is to reduce the time required to perform memory accesses for fetching data or instructions. Information placed in cache memory can be accessed in much less time than information placed in main memory. Therefore, a CPU with cache memory need not spend much less time waiting for instructions and operands to be fetched or stored.

For example, in a typical large combinator, main memory can be accessed in 300-600 nanoseconds;
Information can be obtained from cache memory in 50-100 nanoseconds. In this yokka kimono, cash and
Memory significantly increases execution speed.

Cache memory consists of a number of blocks of one or more data words, each block having an associated address tag that uniquely determines which block of main memory it is a copy of. ing. Each time the processor makes a memory reference, the cache
Memory checks to see if it has a copy of the requested data. If a copy is available, the cache memory supplies the data; otherwise, it retrieves the data from main memory, replaces one of the blocks of data stored in the cache memory, and supplies the data to the processor. .

One way that cache memory performance can be improved is through main memory updates and multicache consistency.
The goal is to minimize the overhead of maintaining the

Information is typically retrieved from a cache and associatively determined whether key≠≠#“hit”. However, large-capacity associative memories are very expensive and rather slow. In early cache memories, all elements were searched associatively on each request from the CPtJ. To give it the access time it needs to keep up with the CPU,
The cache memory size was limited, which resulted in a somewhat low hit rate.

Cache memory can also be organized into groups of small associative memories, called sets, each containing a certain number of locations, called a set size. In a cache memory of size m divided into L sets, there are s=m/L locations in each set. When an address in main memory is mapped into a cache memory IJ, it is possible for that address to appear in any of a fixed set.For a given size of cache memory, each set Searching in parallel can improve access time by a factor of L. However, the time to complete a requested associative search is still undesirably long.

As mentioned above, when a cache memory has multiple sets, when a cache miss occurs, the cache memory determines which of the information blocks to swap.
A decision must be made whether to clear space for the new block being retrieved from main memory. Each cache memory uses various schemes to determine which blocks are swapped out.
ly Used) method. According to the LRU replacement method,
For each group of blocks at a particular index, the cache maintains the state of a number of bits that track the order in which these blocks were last accessed. Each time one of the blocks is accessed, it is marked as most recently used and the other blocks are adjusted accordingly. If a cache miss occurs, the block that is swapped out to make room for the block being retrieved from main memory is the block that was least recently used.

Other permutation methods that may be used include first-in, first-out (FIFO) methods and random permutation methods.

Cache-contention memory architectures are complicated when accessing cache-combined memory for systems using virtual addresses, but then cache-access is a two-step process.

That is, the requested virtual address must first be translated to a physical address and the cache memory must be searched for the physical address. This translation step is typically done by a translation lookaside buffer (TLI:!). The TLB is itself a special type of canon that stores recently used virtual address/physical address translations. This cache memory access process includes two serial steps. As a result, the cache memory access time becomes longer by the TLB access time (though depending on the method, many of the accesses can be performed in parallel).

One way to solve this problem is to access the cache memory using only the physical offset portion of the virtual address given by the CPU. Since the physical offset does not change due to virtual memory translation, translation delays are eliminated. However, this approach has the drawback of limiting the size of the cache memory to the size of the physical page multiplied by the set number of cache memories.

Another method is to use a virtual addressed cache memory. Although direct virtual address memory access is faster because no translation is required, it does introduce some problems. That is, the TLB is used to handle the translation to physical addresses in order to access main memory in the event of a cache miss.
is still necessary. Furthermore, the length is increased because virtual tags are required in addition to physical tags as tags associated with data stored in the cache memory.

Therefore, more memory hardware is required and cache memory is more expensive.

For example, if two or more virtual addresses are mapped to the same physical address and therefore share code or data, if the physical tag is not stored in cache memory that is accessed by virtual address, , often requires inverse mapping (i.e., converting physical addresses to virtual addresses). If a cache miss occurs at a virtual address, that address must be translated into a physical address to access main memory. This physical address is then reverse mapped and used to indicate whether there are other virtual addresses associated with this physical address in the cache memory. If such an address exists in cache memory, it must be renamed and moved to a new virtual address location.

Thus, virtual addressed cache memory typically requires additional hardware and expense.

A similar problem arises from the need to reuse the physical addresses that were associated with a process when the process terminates. Each time a virtual address to physical address mapping is changed, according to the prior art steps are taken to purge obsolete data from all cache sets corresponding to the old mapping.

[Purpose of the invention]

The present invention provides cache memory management that can avoid purging of stale data from the cache memory, which would be accompanied by an increase in cache access time, upon changes in the physical address-virtual address mapping in the TLB. The purpose is to provide a method.

[Summary of the invention]

According to one embodiment of the invention, a page generation number is provided as part of the virtual/physical address mapping information. Each time a cache line is loaded into cache memory, whether for instructions or data, an incremented page generation number is added to that cache line.
Placed within the tag for the line. For all accesses to data in cache memory, the TLB
It is checked whether the page generation number within matches the page generation number corresponding to the selected cache line.

If they do not match, the cache line containing the stale data is purged from cache memory, and the correct data block (which contains an incremented page generation number) is retrieved from main memory and stored in the cache.
placed in memory.

[Explanation of Examples]

As seen in Figure 1, the computer system:
It includes a CPU II that communicates with main memory 13 and input/output channel (Ilo) 15 via bus 17 . C.P.
The UII includes a processor 19 that fetches, decodes, and executes instructions to process data. All instructions and data used by a computer system are stored in a CP
Since it is impractical to store them in the UII, those data and instructions are stored in main memory 13 and transferred to processor 19 when they are required during the execution of a program or routine. After completion, it is returned to main memory 13.

Access to main memory 13 is relatively slow compared to the operation of processor 19. If processor y"j 19 had to wait for main memory access to complete each time an instruction or data was needed, its execution speed would be greatly reduced. Processor 19
In order to obtain access times that more closely match the needs of the computer, the buffer memory 21 stores a limited number of instructions and data.

Because key memory 21 is much smaller than main memory 13, it can be economically constructed to have faster access speeds. Nevertheless, there is still a trade-off between access time to cache memory and cache memory size. As mentioned above, as cache memory becomes larger, it becomes more expensive and the time to access it increases. Therefore, if the cache memory 21 is made very large to increase the hit rate, there will be very few references to the main memory 13, but the speed of the processor will increase as the cache memory gets hit more often. However, memory access time may decrease due to increased memory access time. Therefore, it is desirable to reduce access time to cache memory as much as possible.

The computer system shown in FIG. 1 uses virtual addresses to access main memory 13. A translator (not shown) converts the virtual addresses into the physical addresses needed to retrieve the requested instruction or data. Convert. The information required by the converter to implement the conversion is stored in a page directory PDIR located in the main memory 13. The TLB 23, a high speed small memory, stores a limited number of recently used virtual address/physical address translation information given by the PDIR.

TLB 23 can reduce access times to main memory 13 by eliminating the need to perform translation steps corresponding to the address mappings it stores on every memory access. TLB23
does not contain the requested virtual address, the translator returns the called bare address pair to the TLB. The TLB replaces an existing TLB entry for future use.

An understanding of the structure and organization of cache memory 21 and TLB 23 is necessary to fully understand the scheme of the present invention. The structure of TLB 23 is shown in FIG. The structure of cache memory 21 is shown in FIG.

As shown in FIG. 2, TLB23 has virtual address/
Contains an array of locations holding physical address pairs. Each location is labeled with an index 30. This index 3o can be derived from the virtual address. Virtual address entry 32 is the virtual page number of the virtual address used by processor+j19. A physical address entry 34 represents the physical page location of an address in main memory (34, translated from a virtual page number. A complete physical address consists of a physical page number and a physical offset. The physical offset is a virtual Counted directly from the lower part of the address.

As shown in FIG. 3, cache memory 21 includes an array of locations that can hold data from main memory 13. Each location is labeled with an index 31 similar to index 30 of TLB 23 and includes a physical address 33 and data 35. physical address 3
3 corresponds to the physical page number in which the data 35 is stored in the main memory 13.

According to the invention, the TLB23
Each virtual address/physical address mapping information given to the TLB page generation number (Page gen
generation number, PGN). Each catch! 'Entry is also TL
B PGN field 36 is included. Each cache entry includes a cache PGN field 37. Every time it is necessary to change the virtual address/physical address mapping, i.e. to change the virtual address of an existing virtual address/physical address translation pair, the mapping is changed in the PIOR and the PGN of the new translation pair is P
incremented in the DIR and purges old translations from the TLB.

The term "purge" means that at this point, stale data corresponding to the old conversion may still exist in the cache memory without updating the main memory. However, rather than purging the cache memory as is conventionally done (which requires overhead time), the stale data is allowed to remain in the cache memory.

The processor then uses the new virtual address/physical address.
When a virtual address is given for mapping, TLB
23 and the cache 210 both store the TLB and cache memory associated with this virtual address.
Accessed to identify virtual address/physical address mapping within a data block. However, since it has been purged from the old conversion pair ViTLB23, TL
B Mistakes occur. The new transform pair, along with its incremented PGN, is then retrieved from the PDIR by the transformer and provided to the 4LLB23.

As shown in FIG. 4, according to the present invention, in order to check whether there is a cache hit, in addition to the normal physical address comparison, the newly searched TLB entry and the cache hit are compared.
The PGNs in the lines are also compared. A cache miss occurs because the cache line associated with this virtual address contains a PGN that should have been incremented. This results in the purging of stale cache lines and the retrieval of new data blocks from main memory.

The incremented PGN and the physical address field for the new cache block are provided to the cache memory by the TLB, making both the TLB entry and the cache line associated with this virtual address correspond.

To maintain unambiguousness of page generation numbers, cache and TLB entries associated with virtual addresses are wrapped around page generation number values for one entry (
must be flooded whenever it is cycled). The term "flagging" refers to the invalidation of an entry in cache memory. If the IJ becomes dirty (that is, if a write has been performed), it is written back to the main memory. This occurs much less often than mapping changes, resulting in lower system overhead.

〔Effect of the invention〕

As described above, according to the present invention, overhead in cache memory management can be reduced by introducing page generation numbers.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a computer system to which the present invention is applied, Fig. 2 is a diagram illustrating the configuration of a cache memory used in an embodiment of the present invention, and Fig. 3 is an embodiment of the present invention. FIG. 4 is a diagram illustrating the configuration of a TLB used in this embodiment, and FIG. 4 is a diagram illustrating checking of page generation numbers in an embodiment of the present invention. E: CPU. 13: Main memory, 19: Prosensor, 21: Cassosh fist memory 23: TLB 30. 31: Index, 32: Virtual address entry, 33: Physical address, 34: Physical address entry, 35: Data, 36: TLB PGN Field, 37: Cash PGN field.

Claims (1)

[Claims] In a cache memory management method of a system using a virtual address method, a generation number that is updated in response to an update of the translation pair information is added to the virtual address/physical address translation pair information, A generation number is given to a TLB and a cache memory, and when accessing the cache memory, a match between a generation number read from the cache memory and a generation number read from the TLB is confirmed. Memory management method.