JPH05216766A - Method for maintaining coherence of cache between data cache and segment descriptor and memory device of computer - Google Patents

Abstract

PURPOSE: To obtain an improved memory managing device in which the coherence of a memory can be improved. CONSTITUTION: This is a memory managing device for a computer in which coherence between a descriptor cache and a data cache is held by an inclusive bit mechanism. When a descriptor in a data cache in which an inclusive bit is set to the descriptor corresponding to the descriptor cached in a descriptor cache 570 is changed, the overall descriptor cache 570 is always flashed by the set inclusive bit. Moreover, an effective bit is set to the descriptor in data cache cached from a descriptor chart. When the descriptor to which the effective bit is set in the data cache in the descriptor chart is corrected, the overall descriptor cache 570 is always flashed. Therefore, cache coherence among the descriptor cache 570, data cache, and descriptor chart can be maintained in this improved memory managing device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management device for a computer, and more particularly to a memory partitioning device having high data access speed and efficiency.

[0002]

2. Description of the Related Art A memory management device can give an independent address space to each program in order to avoid interference between the programs when several programs are simultaneously executed. Memory management typically consists of partitioning and paging. Partitioning is used to give each program several independent, protected address spaces ("segments"). Paging is used to support environments where a large address space is simulated with a small amount of random access memory (“RAM”) and some disk storage. System designers can choose either or both of these mechanisms. When several programs are running at the same time, either mechanism can be used to protect one program from interference with the other.

By partitioning, like the memory model of a simple 8-bit processor, or as a highly configured memory model with address translation and protection,
The memory can be simple, not completely unified. Each segment is an independent, protected address space. Access to a segment is the size of the segment, the privilege level required to access it, and the type of memory criteria that can be performed on it (instruction fetch, stack push or stack pop, call operation, write Behavior, etc.) and whether it resides in memory or not. Reference is now made to FIG. 1 (a), where a pictorial representation of the memory address translation mechanism is shown. The partitioning mechanism 105 translates the partitioned (logical) address 100 into a contiguous, unpartitioned address space called a linear address 110. Paging mechanism 11 when paging is enabled
5 translates linear address 110 to physical 120. Linear address 110 if paging is not enabled
Is used as the physical address 120. Physical address 120 eventually appears on the address bus exiting the processor.

An example of a memory management device has been implemented in the i486 ™ microprocessor manufactured by Intel, Inc., the assignee of the present application, Santa Clara, Calif., USA. Can be found. That i
In the 486 ™ microprocessor, a logical address consists of a 16-bit segment selector for its segment and 32 bits offset into that segment. According to FIG. 1 (a), by adding an offset to the base address 103 of the segment, the logical address 100 becomes a linear address 110.
Is converted to. The base address 103 is obtained from the segment descriptor 104. The segment descriptor is a data structure in memory that provides the size and location of the segment as well as access control information. For example, i
The segment descriptors in the 486 ™ microprocessor come from two tables: the global descriptor table (GDT) or the local descriptor table (LDT). There is one GDT for every program in the system and one LDT for each separate program or task being executed.
There is. Various programs can share the GDT, if allowed by the operating system. The system can also be configured without LDT. For more information on the i486 (TM), go to Intel Corporation, Santa Clara, CA, USA.
i486 (TM) Microprocessor: Programmer's Reference Manual (i486M
icroprocessor: Programmer '
s Reference Manual).

The translated address is a linear address 110.
Is. If the paging mechanism is not used, linear address 110 is physical address 120.
If paging is used, a second level of access information is needed to generate the physical address 120. Referring again to FIG. 1, the segment selector 102 is shown pointing to the segment descriptors 104 that make up the segment. The i486 ™ microprocessor can require more segments than those segment selectors currently occupy. If this is true, the program uses the form of the MOVE instruction to change the contents of the segment register when it needs a new segment. As shown in FIG. 1B, the segment selector 132 identifies the segment descriptor by specifying the descriptor table 133 and the descriptor index 134.

Reference is now made to FIG. 2 where the descriptor format in the i486 ™ microprocessor is shown. However, because of the descriptor format's need to provide backward compatibility for conventional processor architectures, it is confused when it is stored in memory. In order to simplify the operation of the internal processor, i48
The conversion of the raw jumbled segment descriptor 300 to an unjumbled descriptor 310 for the 6 ™ microprocessor is shown in FIG.

[0007] Further, the pending US patent application No. No. filed on the same day as the US patent application forming the basis of the priority claim of the present application.
"Segment Descriptor Cache for Microprocessors (A SEGMENT DESCRIPT
OR CATCH FORA MICROPROCES
SOR) "specification, a segment descriptor cache is used to drive the descriptor out of the segment descriptor register and the segment descriptor register It may hold descriptors that were previously fetched, tied, and protection tested so that it can be loaded directly into a file, bypassing all the work and overhead normally associated with loading segment registers. it can. FIG. 9 shows the main memory 900 that is present when the descriptor cache 920 is introduced into the microprocessor.
At each level such that the descriptor data maintained at one level, which represents the three level hierarchy of the processor data cache 910 and the processor descriptor cache 90, is consistent with the descriptor data at the previous level. It will be apparent to those skilled in the art that these mechanisms must be adopted.

As will be explained below, the present invention discloses an improved memory management device for a computer in which the coherency between the descriptor cache and the data cache is preserved by the inclusion bit mechanism. is there. In one embodiment, for the descriptors contained in the data cache line indicating that the same organized descriptors are also cached in the descriptor cache, the data
The inclusion bit associated with the cache is set. Therefore, the inclusion bit indicates the association between the data cache and the descriptor cache. A description contained in the descriptor cache that is always flushed when the data in the data cache that has the inclusion bit set is modified, modified, or swapped out. Reflects the fact that the child is no longer valid or the association is no longer valid. Therefore, the inclusion bit maintains cache coherency between the descriptor cache and the data cache.
The existing hardware caching mechanism then maintains cache coherency between the data cache in main memory and the descriptor table.

[0009]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved memory management device with high coherence of the memory. Another object of the present invention is to provide an improved memory management device which has a high cache coherence but does not degrade the performance of segment descriptors.

[0010]

SUMMARY OF THE INVENTION The present invention discloses an improved memory management device for a computer in which coherency between a data cache and a descriptor table is maintained by an inclusion bit mechanism. .. In one embodiment, the inclusion bit is set for a descriptor in the data cache that corresponds to another descriptor cached in the descriptor cache so that associations between descriptors are indicated. The entire descriptor cache due to the fact that the association between two descriptors is no longer valid when a descriptor in the data cache with the inclusion bit set is modified or swapped out. Is always flashed. Therefore, cache coherency between the descriptor cache, the data cache, and the descriptor table is preserved in this improved memory management device. Here, an improved memory for performing memory operations in a microprocessor having particular application for use by a microprocessor memory partitioning device to achieve coherency between a descriptor cache and a data cache. A management device is disclosed. In the following description, specific memories, organizations, architectures, data rates, etc. are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without those specific details. In other instances, well-known circuits are shown in block diagram form in order not to unnecessarily obscure the present invention.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIG. 4, a segment register loading process is shown in block diagram form. Those skilled in the art will appreciate that segment register loading is the basis for any partitioned memory management technique. As shown, the processor is MOVE SE
When encountering a selector from an instruction like G REG,
To prevent protected data from being used by less privileged programs to access protected data, the processor does not allow any privilege interception (Privi).
test the selector for the legion violation). If no privilege interception is found, an 8-byte descriptor is fetched by the processor from the memory / data cache based on the descriptor table and the selector that identifies the descriptor in that table. This descriptor is tested for privilege interception. If no privilege blockages are found, the descriptors are cleaned up and information about the segment, such as size and location of the segment, and control and status information can be loaded into the segment register for the program executing.

Reference is now made to FIG. 5, where a segment register loading apparatus including descriptor cache is shown. Those skilled in the art should understand that the bus dimensions are for illustration purposes only and that the invention may be practiced without the specific details shown. As shown in FIG. 5, the device 500 has a selector privilege tester 510 for testing privilege disturbs in the selector 501 so that less privileged programs cannot access the protected data. As used in this implementation, if the privilege field of the segment selector contains a privilege level that has a greater value than the program (ie, less privilege), the selector overrides the program privilege level.
If selector 501 passes the test by privilege tester 510, the selector is forwarded to descriptor address generator 520. Then the descriptor address generator 520
Generate the appropriate address of the descriptor in the descriptor table for that selector. Currently, two descriptor tables are used, a global descriptor table and a local descriptor table. This address generation process includes changing the current segment to specify the table based on the selection by selector 501 and setting the execution address to the selector index value. The run value allows the descriptor to be retrieved from memory 500 and held in the organizer 550 and descriptor tester 540, which inspects the descriptor and controls its access to the segment. .. If the access is interrupted, the processor is faulted. The organizer 550 transforms the descriptors into the internal organized manner shown in FIG. Successful descriptors are loaded into segment register 560 and updated into descriptor cache 570 for later use.

Reference is now made to FIG. 6, where a flow chart identifying the order of operation of the selector descriptors is shown. MOV Sr
When the selector 501 is encountered, as in the eg instruction, the descriptor cache 570 is indexed. If the corresponding descriptor is found ("hit"), the descriptor is loaded with the selector 570 from the descriptor cache 570 into the segment register file 560. Allows failure of insufficient privilege level selectors if no corresponding descriptor is found (“miss”),
Selector 501 is tested for privilege jamming. When the selector 501 passes the test by the privilege tester 510,
The descriptor linear address can be calculated 520 and the descriptor is retrieved from memory 530. The descriptor is also tested for its privilege level and is faulted for any privilege interception. The descriptors are sorted and the sorted descriptors are loaded into the selector register file 560.
The ordered descriptors are used to update the update descriptor cache 570.

Reference is now made to FIG. 7, where a diagram of the selector descriptor cache is shown. Although a 4 × 16 set associative cache is shown in the figure, it should be understood by those skilled in the art that other organizations can be easily implemented to achieve the desired functionality. The descriptor cache 770 is divided into three arrays: a tag array 720, a data array 730, and a last used (“LRU”) array 710. Selector bits [4: 3] are used as the set number and are indexed into the descriptor cache. Each set consists of four "ways" and each way is associatively searched for the desired entry. The LRU entry 715 is made up of 3 bits used to determine which "way" in the set was last used.
If a new entry is to be placed in the descriptor cache, the LRU entry for that set determines which entry can be exchanged with minimal impact on performance.

When an entry is placed in the descriptor cache, descriptor tag 740 from tag array 720 contains the remaining selector bits and privilege level of the processor. The tag also includes a valid bit 741 indicating whether the entry is valid and a code segment flag (CS) 742. The CS flag 742 is used to identify the type of cached descriptor. The reason is that various protection checks are made as opposed to data segments. Data array 730 includes organized segment descriptors. Each organized segment descriptor has an access right 751 and a base address 7
52 and a limit 753.

Reference is now made to FIG. 8 where a pictorial representation of a memory management device including the present invention is shown. As shown,
The segment descriptor cache 820 maintains coherency with the data cache by using the data cache inclusion bit mechanism. The data cache 810 maintains coherency with the descriptor table 800 in main memory by means of a 4-state encoding protocol called "MESI". The "MESI" protocol is used in many current generation microprocessor designs and will not be described here. The descriptor is stored in the descriptor table 800. The descriptor table 800 is typically contained in main memory. The descriptor 805 is the descriptor table 80.
0 to be loaded into data cache 810 via bus 830. When the data or descriptor is loaded into the data cache line 806, the valid bit 816 is set and the data cache 81
0 indicates that it contains valid data in its cache line. When the descriptor 810 is cached in the descriptor cache 820 in response to a segment selector load, the inclusion bit 814 corresponding to the descriptor 806.
Is set in data cache 810 to associate descriptor 806 in data cache 810 with descriptor 825 in descriptor cache 820. In addition, the descriptor entry valid bit 826 is set,
Indicates that the descriptor cache 820 contains valid entries. The descriptor 825 is a tested and ordered version of the descriptor 806, as described above for the descriptor cache. Typically, the descriptor table may be accessed and modified via bus 830 by another processor (not shown) within the device. Therefore, when the descriptor 806 in the data cache 810 with the inclusion bit 814 set is modified or swapped, the entire descriptor cache 820 is flushed to preserve coherence at all times. Also, all included bits in the data cache 810 are cleared to ensure that the data
6 illustrates the separation between cache 810 and descriptor cache 820. Flush in descriptor cache 820 clears valid bits 826 of all entries. If descriptor 805 were modified in descriptor table 800, its corresponding descriptor would be data cache 810.
Those skilled in the art should understand that it will be effective within.

Further referring to FIG. 8, modifying or swapping out any data cache line with the inclusion bit set flushes all of the entries in the descriptor cache. Since the flushing mechanism does not pinpoint the exact entry in the descriptor cache that is isolated, another entry that can maintain the association is also isolated. Therefore, some entries that are not required to be flushed are flushed. This can adversely affect performance. Those skilled in the art will appreciate that the data cache flush need not be as limited as possible. Flush with data cache line swap
This can be reduced by biasing the exchange algorithm in cache 810. The data cache 810 is bidirectional and is the LRU bit (not shown) to determine which entry to exchange with the least degradation.
To maintain. As shown in FIG. 10, the inclusion bits are used to bias the exchange algorithm. It will also be apparent to those skilled in the art that the cache coherence mechanism with the inclusion bit is in many ways superior to other mechanisms. It is better than a mechanism that uses a pointer to the data cache to indicate which entry to flush and requires an additional addressing bit in the data cache. It is also superior to the mechanism of maintaining the data cache address of the descriptor in the data cache so that the modified descriptor address is compared to the descriptor cache address. The technique typically requires that the data cache always maintain a complete address and compare each of its addresses when an entry to the data cache is modified. Another descriptor cache coherency mechanism typically requires more hardware. This will reduce the size of the data cache that can be built.

Still referring to FIG. Data cache 810 is also shown having valid bits corresponding to descriptors in data cache 810. Descriptor table 80
Valid bit 816 is always set when descriptor 805 from 0 is cached in data cache 810. The valid bit 816 is set until the descriptor 805 in the descriptor table 800 is changed so that the descriptor 806 in the data cache 810 is no longer valid with respect to its association to the descriptor 805 in the descriptor table 800. It remains. Further, when the valid bit 816 is set, the inclusion bit 814 of the descriptor 806 is set, that is, the descriptor 806 is in the descriptor cache 820.
The descriptor cache 820 is also flushed, assuming it is separate from the descriptors in. Data cache 8
When valid data is realized in 10, the inclusion bit 814
At least when descriptor 806 is set in data cache 810 and when descriptor 805 is set in descriptor table 800 with the corresponding valid and inclusion bits set. At one time, the descriptor cache 820 is always flushed so that memory coherency between the descriptor cache 820 and the descriptor table 800 is maintained.

[Brief description of drawings]

FIG. 1 is a pictorial representation of a memory address translation mechanism (a) and a segment selector format (b).
And indicates.

FIG. 2 shows a format of a segment descriptor.

FIG. 3 shows a process for organizing a cluttered segment descriptor.

FIG. 4 shows a block diagram representation of a protected mode segment register process.

FIG. 5 is a block diagram representation of a memory partitioning device.

FIG. 6 is a flow chart showing the operation of a segment descriptor load.

FIG. 7 shows a currently implemented descriptor cache.

FIG. 8 shows a preferred embodiment of the memory management device of the present invention.

FIG. 9 shows a three-level hierarchy currently implemented in the present invention.

FIG. 10 shows a switching algorithm currently implemented in the present invention.

[Explanation of symbols]

 100 logical address 102, 132 segment selector 103 base address 105 partitioning 110 linear address 120 physical address

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Pradeep Davey United States 10606 New York White Plains Martin Avenue number 1015-25 (72) Inventor Mustafis Earl Chowdri United States 94086 Sanny Vale Vicente Dry California B Number F-1260

Claims (2)

[Claims] 1. A descriptor table coupled to a plurality of data processing devices for storing segment descriptors in a first format, and a data processing device for storing segment descriptors in the first format. Of a memory management unit of a computer comprising a data cache coupled to one of the data processing units and a segment descriptor cache coupled to one of said data processing units for storing a segment descriptor in a second format. A method of maintaining cache coherency between a cache and a segment descriptor, the step of providing a segment selector pointing to a segment descriptor in a first format in a descriptor table; Responsive to retrieving the segment descriptor in the first format from the descriptor table A degree, the steps of storing the segment descriptor of the first format into the data cache, the segment descriptor of the first format second
Formatting the segment descriptor of the first format into a segment descriptor cache, the segment descriptor of the first format in the data cache being the segment description. Set an inclusion bit in the data cache corresponding to the segment descriptor of the first format to indicate that it is associated with the segment descriptor of the second format in the child cache. A step of checking whether the segment descriptor of the first format has been changed by the data processing device; and, if the segment descriptor of the first format has been changed by the data processing device, Flush segment descriptor cache A data cache, wherein the segment descriptor cache is always flushed when a segment descriptor in the data cache whose inclusion bit is set is modified by the data processing device. To maintain cache coherency between the and segment descriptors. 2. Represented by a plurality of segments,
A descriptor table coupled to the plurality of agents for storing a plurality of descriptors of a first format each designated by a segment selector received from the plurality of agents in a memory device for a computer; A data cache coupled to one of the agents for caching descriptors of the first format, and coupled by the agent to the data cache for selecting a corresponding segment of the cache Descriptor format means for formatting the descriptors of the first format into descriptors of the second format so that descriptors are used; and one of the segments coupled to the data cache.
A descriptor cache for caching the descriptors in the second format, each of which is used to select one, and a plurality of descriptor caches coupled to the data cache and corresponding to the descriptors in the first format in the data cache. And an inclusion bit of each of said each one to indicate that said descriptor of said first format in said data cache is associated with said descriptor of said second format in said descriptor cache. Inclusion bit setting means for setting an inclusion bit, and determining whether any of the descriptors of the first format in the data cache in which the inclusion bit is set have been modified by the data processing device. An inclusion bit checking means, wherein the inclusion bit in the data cache is set A descriptor cache flush means for flushing the descriptor cache if any of the descriptors of the first format has been modified, whereby an inclusion bit is set in the data cache. A memory management device for a computer, wherein the descriptor cache is always flushed when a descriptor of the first format is changed.