GB2395588A

GB2395588A - Apparatus supporting multiple page sizes with address aliasing

Info

Publication number: GB2395588A
Application number: GB0400594A
Authority: GB
Inventors: Terry L Lyon
Original assignee: Hewlett Packard Co
Current assignee: HP Inc
Priority date: 1999-12-17
Filing date: 2000-12-06
Publication date: 2004-05-26
Anticipated expiration: 2020-12-06
Also published as: GB2395588B; GB0400594D0

Abstract

A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support multiple page sizes with virtual address aliasing. Support for various levels of address aliasing are provided through a physical address CAM and a page size mask comparator. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. In addition, multiple page sizes may be supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.

Description

APPARATUS AND METHOD FOR SUPPORTING MULTIPLE PAGE SIZES

WITH AI)DRESS ALIASING

1 Technical Field

2 The technical field encompasses computer systems having prevalidated cache

3 designs. In particular, the technical field encompasses a computer system that supports

4 virtual multiple page sizes with address aliasing.

5 Background

6 Computer systems may employ a multi-level hierarchy of memory, with relatively 7 fast, expensive, but limited-capacity memory at the highest level of the hierarchy 8 proceeding to relatively slower, lower cost, but higher-capacity memory at the lowest 9 level of the hierarchy. Typically, the hierarchy includes a small fast memory called a 10 cache, either physically integrated within a processor or mounted physically close to the 11 processor for speed. The computer system may employ separate instruction caches and 12 data caches. In addition, the computer system may use multiple levels of caches. The use 13 of a cache is transparent to a computer program at the instruction level and can thus be 14 added to a computer architecture without changing the instruction set or requiring 15 modification to existing programs.

16 A cache hit occurs when a processor requests an item from a cache and the item is 17 present in the cache. A cache miss occurs when a processor requests an item from a cache 18 and the item is not present in the cache. In the event of a cache miss, the processor 19 retrieves the requested item from a lower level of the memory hierarchy. In many 20 processor designs, the time required to access an item for a cache hit is one of the primary 21 limiters for the clock rate of the processor, if the designer is seeking a single cycle cache 22 access time. In other designs, the cache access time may be multiple cycles, but the 23 performance of a processor can be improved in most cases when the cache access time in 24 cycles is reduced. Therefore, optimization of access time for cache hits is critical to the 25 performance of the computer system.

26 Associated with cache design is a concept of virtual storage. Virtual storage 27 systems permit a computer programmer to think of memory as one uniform single-level 28 storage unit but actually provide a dynamic address-translation unit that automatically 29 moves program blocks on pages between auxiliary storage and the high speed storage 30 (cache) on demand.

31 Also associated with cache design is a concept of fully associative or content 32 addressable memory (CAM). Content-addressable memory is a random access memory

I that, in addition to having a conventional wired-in addressing mechanism, also has wired 2 in logic that makes possible a simultaneous comparison of desired bit locations of a 3 specified match for all entries during one memory-cycle time. Thus, the specific address 4 of a desired entry need not be known since a portion of its contents can be used to access 5 the entry. All entries that match the specified bit locations are flagged and can be 6 addressed on the current or subsequent memory cycles.

7 Memory may be organized into words (for example, 32 bits or 64 bits per word).

8 The minimum amount of memory that can be transferred between a cache and the next 9 lower level of memory hierarchy is called a line or a block. A line may be multiple words 10 (for example, 16 words per line). Memory may also be divided into pages, or segments, 11 with many lines per page. In some computer systems page size may be variable.

12 In modern computer memory architectures, a central processing unit (CPU) 13 produces virtual addresses that are translated by a combination of hardware and software 14 to physical addresses. The physical addresses are used to access a physical main 15 memory. A group of virtual addresses may be dynamically assigned to each page. A 16 special case of this dynamic assignment is when two or more virtual addresses are 17 assigned to the same physical page. This is called virtual address aliasing. Virtual 18 memory requires a data structure, sometimes called a page table, that translates the virtual 19 address to the physical address. To reduce address translation time, computers may use a 20 specialized associative cache dedicated to address location, commonly called a translation 21 lookaside buffer (TLB).

22 If a cache stores an entire line address along with the data and any line can be 23 placed anywhere in the cache, the cache is said to be fully associative. For a large cache 24 in which any line can be placed anywhere, the hardware required to rapidly determine if 25 and where an item is in the cache may be very large and expensive. For larger caches a 26 faster, space saving alternative is to use a subset of the address (called an index) to 27 designate a line position within the cache, and then store the remaining set of the more 28 significant bits of each physical address, called a tag, along with the data. In a cache with 29 indexing, an item with a particular address can be placed only within a set of lines 30 designated by the index. If the cache is arranged so that the index for a given address 31 maps exactly to one line in the subset, the cache is said to be direct mapped. If the index 32 maps to more than one line in the subset, or way, the cache is said to be set- associative.

33 All or part of an address may be hashed to provide a set index that partitions the address 34 space into sets.

I With direct mapping, when a line is requested, only one line in the cache has 2 matching index bits. Therefore, the data can be retrieved immediately and driven onto a 3 data bus before the computer system determines whether the rest of the address matches.

4 The data may or may not be valid, but in the usual case where the data is valid, the data 5 bits are available on the data bus before the computer system determines validity. With 6 set associative caches, the computer system cannot know which line corresponds to an 7 address until the full address is compared. That is, in set-associative caches, the result of 8 a tag comparison is used to select which line of data bits within a set of lines is presented 9 to the processor.

10 In a cache with a TLB, the critical timing path for a hit requires a sequence of four 11 operations: 1) a virtual tag must be presented to the TLB to determine the location of a 12 corresponding physical tag in random access memory (RAM) in the TLB; 2) the physical 13 tag must then be retrieved from the TLB random access memory; 3) the physical tag from 14 the TLB RAM must then be compared to physical tag's accessed from the tag section of 15 the cache; and 4) the appropriate data line must be selected. The sequence of four 16 operations is required to read the cache and can be a limiter to processor frequency and 17 processor performance.

I 8 Summary

19 What is disclosed is an apparatus that supports multiple page sizes with address 20 aliasing in a computer architecture having a prevalidated cache. The apparatus includes a 21 prevalidated cache translation lookasidc buffer (TLB), whih in turn includes a virtual 22 address content addressable memory (CAM), a first page size mask random access 23 memory (RAM), a variable page size address RAM, and a prevalidated cache tag 24 operably coupled to the TLB.

25 In an embodiment, the disclosed apparatus includes a virtual address CAM that 26 receives virtual address information for a new TLB entry, a physical address CAM that 27 receives physical address information for the new TLB entry, wherein the physical 28 address CAM compares the physical address information of the new TLB entry with the 29 physical address information of each of existing TLB entries, wherein if the physical 30 address information of the new TLB entry matches the physical address information of 31 one of the existing TLB entries, the matched existing TLB entry is invalidated, and 32 wherein the TLB includes logic to support multiple page sizes, the logic including a page 33 size mask RAM that holds a page size mask and provides a first output signal, a virtual 34 page size address RAM that holds a virtual address for a page size region of all existing

I TLB entries and provides a second output signal, and a multiplexer, and a tag physical 2 address RAM that holds physical address bits corresponding to a range of page sizes and 3 provides a third output signal, wherein the multiplexer receives the first, second and third 4 output signals and provides a partial TLB hit signal.

5 Also what is disclosed is a corresponding method for supporting multiple page 6 sizes with address aliasing in a computer system. The method includes receiving a virtual 7 address for a new TLB entry in a virtual address CAM, receiving a physical address for 8 the new TLB entry in a physical address CAM, and comparing the physical address of the 9 new TLB entry with physical addresses of existing TLB entries. If the physical address 10 of the new TLB entry matches one of the physical addresses of the existing TLB entries, 11 the matched existing TLB entry is invalidated.

12 Finally, what is disclosed is a computer system that supports multiple page sizes 13 and addressing aliasing, the computer system including a translation lookaside buffer 14 (TLB) that in turn includes a virtual address content addressable memory (CAM) that 15 receives virtual address information for a new TLB entry, and a physical address CAM 16 that receives physical address information for the new TLB entry, wherein the physical 17 address CAM compares the physical address information of the new TLB entry with the 18 physical address information of each of existing TLB entries, wherein if the physical 19 address information of the new TLB entry matches the physical address information of 20 one of the existing TLB entries, the matched existing TLB entry is invalidated.

21 Description Of The Drawings

22 The apparatus and method will be described with reference to the following 23 drawings, wherein like numerals refer to like elements and wherein: 24 Figures I and 2 illustrate prior art computer microarchitectures;

25 Figure 3 illustrates a prevalidated cache tag micro-architecture; 26 Figure 4 illustrates a single page size prevalidated tag cache microarchitecture; 27 Figure 5 illustrates a multiple page size prevalidated tag cache micro-architecture; 28 Figure 6 illustrates a prevalidated cache TLB with address aliasing and no saving 29 of cache data; 30 Figure 7 illustrates a prevalidated cache TLB with address aliasing and replacing 31 an existing TLB entry; 32 Figure 8 illustrates a prevalidated cache design with address aliasing incorporating 33 a column copy tag function that supports address aliasing when page sizes are the same;

I Figure 9A illustrates a prevalidated cache design with address aliasing 2 incorporating a colurun copy tag function which supports different page sizes; 3 Figure 9B illustrates a prevalidated cache design with address aliasing 4 incorporating a coluron copy tag function that supports different and multiple page sizes; 5 and 6 Figure 10 is a block diagram of functions carried out by an embodiment of the 7 micro-architecture of Figure 7.

8 Detailed Description

9 A cache having a TLB in which physical tags do not need to be retrieved from the 10 TLB may improve the overall time for the critical path for accessing caches with TLBs.

11 In such a design, instead of storing physical tags in a cache, the cache stores a location 12 within the TLL where the physical tag is stored. The TLB may include two or more 13 CAMs. For a cache hit, one of the CAMs in the TLB may generate a vector, or TLB hit, 14 that specifies a location within the TLB where the physical address is stored. The vector 15 may be compared to a location vector, or hit bit, stored in the cache. The comparison of 16 location vectors provides sufficient information to enable selection of one data line within 17 a set without having to actually retrieve the physical address. As a result, a substantial 18 time consuming operation (physical address retrieval) is removed from the critical time 19 path of a cache hit. In addition, comparing location vectors rather than physical tags 20 enables use of comparison logic that is faster and simpler than convention digital 2 I comparators.

22 Figure I illustrates an example of a prior art cache. The system 10 includes a

23 virtual address 12, a random access memory array 14, a comparator 16 and a physical 24 cache-address register 18. The system 10 employs setassociative logic. The random 25 access array 14 includes a total of 128 (four) entries requiring two virtual page address 26 index bits. Each set of four is part of one physical word (horizontal) of the random access 27 array, so that there are 128 such words, requiring seven address bits. The virtual page 28 number must be used in the address translation to determine if and where the cache page 29 resides. Lower order bits N. which represent the byte within the page, need not be 30 translated. Seven virtual bits are used to select directly one of the 128 words. Words 31 read out of the set are compared simultaneously with the virtual addresses, using the 32 comparator 16. If one of the comparisons gives a "yes," then the correct real or physical 33 address of the page in the cache, which resides in the random access memory array 14, is s

I gated to the physical cache-address register 18. The physical address is used on a 2 subsequent cycle to obtain the correct information from a cache array (not shown).

3 Figure 2 illustrates another prior art cache. Four-way set-associative caches are

4 used for illustration. A virtual address 100 comprises lower order index bits 102 and 5 upper order virtual tag bits 104. The index bits 102 are typically the same for the virtual 6 address and the physical address. The index bits 102 are used to select one set of lines of 7 data in a data section 106 of the cache. The output of the data section 106 is four lines of 8 data 108. The index bits 102 are also used to select a set of physical tags in a tag section 9 110 of the cache. The output of the tag section 110 is four physical tags 112, each 10 corresponding to one data line 108. The virtual tag bits 104 are used to select one entry in 11 a CAM 116 within aTLB 114. The TLB 114 stores both virtualandphysicaltags. If the 12 virtual tag bits 104 do not find a match in the CAM 116, a TLB miss occurs. In the 13 system shown in Figure 2, multiple virtual tags may map to one physical tag. For a TLB 14 hit, the selected CAM 116 entry designates an address in a TLB RAM 118 for a physical 15 tag corresponding to a virtual tag 104. A physical tag is then retrieved from the TLB 16 RAM 118. Each of four digital comparators 120 then compares the physical tag from the 17 TLB RAM 118 to a physical tag 112 from the tag section I 10. A matching pair of 18 physical tags indicates through logic 122 which of four lines of data is selected by a 19 multiplexer 124. For a particular index bit, there may not be a matching pair of physical 20 tags, in which case a cache miss occurs.

21 Figure 3 illustrates a computer nicro-architecture having a four-way set 22 associative cache 200. The cache 200 includes index bits 202, a data section 203 and 23 multiplexer 205. A cache tag section 204 includes physical TLB hit tags corresponding 24 to data lines. When a new line of data is placed in the cache 200, instead of the physical 25 address tag being stored in the cache tag section 204, a vector 212 (called a physical TLB 26 hit vector) is stored in the tag section 204.

27 In the cache 200, a TLB 210 has two CAMs, a physical CAM 206 containing 28 physical tags and a virtual CAM 208 containing virtual tags. When a new virtual tag 207 29 is stored in the virtual CAM 208, a corresponding physical tag 209 is also available via a 30 computer operating system and the corresponding physical tag 209 is stored in the 31 physical CAM 206. A physical TLB hit vector 212 has a binary " 1" corresponding to 32 each location in the physical CAM 206 that has the physical tag 209. Upon entry of a 33 new line into the cache 200, the physical TLB hit vector 212, indicating the location of all 34 the instances in the physical CAM 206 of the physical tag 209 of the new line, is

1 generated by the physical CAM 206 and stored into the cache tag section 204, at a row 2 location determined by the index bits 202 and at a column location determined by a set 3 placement algorithm.

4 For a cache access, a virtual tag 207 is used by the virtual CAM 208 to generate a 5 virtual TLB hit vector 214. If there is a TLB miss, the virtual TLB hit vector 214 is all 6 binary "0s." If there is a TLB hit, the virtual TLB hit vector 214 has a single binary " I," 7 indicating the location of the virtual tag 207 in the virtual CAM 208. Each virtual tag 207 8 in the TLB 210 must be unique.

9 For cache access, the index bits 202 select a set of four physical TLB hit vectors 10 212 in the cache tag section 204. Each ofthe four physical TLB hit vectors 212 in cache l l tag section 204 is compared using one of the four comparators 216, to the virtual TLB hit 12 vector 214 from the virtual CAM 208. For any given set of index bits 202, only one of 13 the four selected physical tags in cache tag section 204 matches the virtual TLB hit vector 14 214 from the TLB 210 for a fixed page size. For a fixed page size, a single pair of 15 matching "is" in the four physical TLB hit vectors 212 then determines which data line is 16 selected by the multiplexer 205. For a given set of index bits 202, if there are no 17 matching " I s" in the compared four physical TLB vectors 212, a cache miss occurs.

18 In the cache 200, the physical address tag from the TLB 210 is not retrieved for 19 cache access. Eliminating the operation of retrieving the physical address tag from the 20 TLB 210 substantially reduces the amount of time in the critical time path for the cache 21 access. Because the cache 200 looks for a pair of matching logical "1 s" to determine a 22 match, the comparators 216 may be simple AND gates followed by a large fan-in OR 23 gate. 24 Additional details related to prevalidated cache architectures are provided in U.S. 25 Patent 6,014,732 entitled CACHE MEMORY WITH REDUCED ACCESS TIME, the 26 disclosure of which is hereby incorporated by reference.

27 Figure 4 shows a prevalidated cache tag micro-architecture 300 that supports a 28 single page size. Figure 4 is a different representation of the prevalidated cache tag 29 design shown in Figure 3, and is shown here to clarify the extensions to the micro 30 architecture given in Figures 59. The micro-architecture 300 includes a prevalidated 31 cache TLB 320 having a virtual address CAM 322. The virtual address CAM 322 is 32 shown containing n entries. Also included in the micro-architecture 300 is a prevalidated 33 cache tag 330 containing physical TLB hit vectors, and a data cache 340. The data cache 34 340 includes m ways. Virtual address 302 includes access size information 310 (bits 0 to

1 3), cache line size information 308 (bits 4 through 6) tag index 306 (bits 7 through 11), 2 and a virtual page number 304 (bits 12 through X). The upper information portion of the 3 virtual address 302, that is the tag index 306 and the virtual page number 304, are 4 provided to the prevalidated cache TLB 320, the prevalidated cache tags 330 and the data 5 cache 340.

6 In normal operation, the prevalidated cache TLB 320 is accessed to find a match 7 with the virtual page number 304 of the memory operation. The virtual address CAM 8 322 outputs a vector of virtual TLB hit bits indicating one or more TLB entries that match 9 the virtual page number 304. At the same time, the prevalidated cache tag 330 is 10 accessed with some index bits of the virtual address 302, and a vector of physical TLB hit 11 bits is read from the prevalidated cache tag 330. The virtual TLB hit bits from the virtual 12 address CAM 322 are ANDed together in logic circuit 332 (an AND gate) with the 13 physical TLB hits from the prevalidated cache tag 330 to determine if there is a match.

14 The n bits are ORed together in the logic circuit 334 (an OR gate) to generate a single 15 cache way hit signal. Data from the data cache 340 is then multiplexed as indicated by 16 the cache way hits in the multiplexer 326 and the result is output as load data.

17 With additional logic, the prevalidated tag cache micro-architecture shown in 18 Figure 4 can support multiple page sizes in the virtual address translation mechanism.

19 Large page sizes may be used to map virtual addresses into large physical address ranges 20 without requiring an extensive number of TLB entries. For example, a 4 megabyte cache 21 would require 1,000 TLB entries to map its entire data if 4 kilobyte pages were used.

22 With larger pages, such as a I megabyte page, this mapping would require only 4 TLB 23 entries. 24 Figure 5 shows extensions to the prevalidated cache tag design of Figure 4 to 25 support multiple page sizes. In Figure 5, the micro-architecture 400 includes a 26 prevalidated cache TLB 420 and a prevalidated cache tag 430. Also included are a 27 multiplexer 440, a bit comparator 442, an AND circuit 444, and an OR circuit 446.

28 The virtual address 402 includes access size 407, cache line size 406, tag index 29 405, page variable size address 404 and virtual page number 403. Also included is a page 30 size mask 408.

31 To provide the additional functionality needed to support y extra pages sizes, the 32 prevalidated cache TLB 420 includes, in addition to a virtual address (VA) CAM 422, a 33 page size mask (PSM) RAM 426 and a variable page size address (VPSA) RAM 424.

34 The PSM RAM 426 is an extension to the TLB 420 structure. The PSM RAM 426 is a

I random access memory block that holds a page size mask, such as the page size mask 2 408, that is wide enough to support the page size capability of the cache design (y bits in 3 this example). The page size mask bits can be reduced to less than y bits if not all power 4 of-2 page sizes are being supported. The PSM RAM 426 is read based on the VA CAM 5 422 hit bits. A single output is needed if multiple virtual to physical address mappings 6 are not maintained in the TLB 420 at one time. Otherwise, multiple outputs (n as shown 7 in this example) are required.

8 The VPSA RAM 424 is also an extension to the TLB 420 structure. The VPSA 9 RAM 424 is a random access memory block that holds the virtual address for the page 10 size region (y bits) for the TLB entry. These bits already reside in a full implementation 11 of a prevalidated cache TLB 420, but now have a function beyond that for a normal 12 content addressable memory. For TLBs 420 with only one virtual address associated with 13 each physical address, the VPSA RAM 424 can be a simple RAM structure selected by 14 the VA CAM 422 hit bits. If the TLB 420 for the cache design supports more than one 15 TLB 420 entry aliased to the same physical address, then multiple VPSA RAM 424 16 outputs may be provided (as shown, n outputs are generated).

17 The prevalidated cache tag 430 functions in the same manner as the corresponding 18 cache 330 shown in Figure 4. However, the prevalidated cache tag 430 also includes a 19 tag physical address RAM 432. The tag PA RAM 432 is an extension to the prevalidated 20 cache tag 430. The tag PA RAM 432 is a random access memory block that holds 21 physical address bits to cover the range of page sizes supported by the cache design (y 22 bits). The tag PA RAM 432 is read out in parallel with the prevalidated cache tag 23 physical TLB hit bits.

24 To reference a data cache 400 that supports multiple page sizes, the VA address 25 bits are compared in the VA CAM 422 with the incoming virtual address IN, and virtual 26 TLB hit bits are generated. The VA CAM 422 does not include potential VA bits that are 27 in the page size region. The virtual TLB hit bits cause RAM cells in the TLB 420 to read 28 out the PSM RAM 426 and the VPSA RAM 424 for each entry that hits in the VA CAM 29 422. Each PSM RAM bit will make a selection for its associated address bit location 30 between the address from the VPSA RAM 424 in the TLB 420 and the physical address 31 read out from the prevalidated cache tag, i.e., tag PA RAM 432. The multiplexer 440 is 32 used to select whether the address information presented with a cache read access is a 33 virtual address or a physical address. The multiplexer 440 receives inputs from the tag 34 PA RAM 432, the VPSA RAM 424 and the PSM RAM 426. Virtual addresses would

I come from the prevalidated cache TLB 420 (i.e., from the VPSA RAM 424) and physical 2 addresses from the tag PA RAM 432. The selected virtual address or physical address 3 bits are grouped to form a VA/PA field of y bits, which are compared as a group against

4 the corresponding bit positions of the virtual address 402 using the bit comparator 442. If 5 both fields compare equally, a "l" is sent to a hit generation AND/OR circuit (AND

6 circuit 444 and OR circuit 446). Depending on the virtual implementation choices for 7 aliasing, I or n compare results could be generated. The virtual TLB hit signals from the 8 VA CAM 422, the bit comparator 442, and the physical TLB hit bits from the 9 prevalidated cache tag 430 are ANDed together in AND circuit 444 and ORed together in 10 OR circuit 446 to generate a final cache way hit.

11 If a prevalidated cache tag system is designed that either invalidates its cache data 12 on the detection of virtual address aliasing (the example shown in Figure 6) or supports 13 multiple TLB entries that are aliased only if they have the same page size (the example 14 shown in Figure 7), then a further simplification may be used. To reduce wiring 15 interconnect and circuit latency, the PSM RAM 426 may be duplicated in the prevalidated 16 cache tag 430 as an extension to the tag PA RAM 432. This allows a localized masking 17 of the tag PA which is more efficient with a content addressable memory implementation.

18 The variable page size address 404 is compared to the tag PA masked with a PSM to 19 generate the partial hit signal 445 (as shown in Figure 5). In this case, in addition to the 20 duplicate PSM array contained in the prevalidated cache tag 430, the VA CAM 422 21 incorporates the VPSA RAM 424 and the PSM RAM 426 into a local CAM function that 22 generates the virtual TLB hits from all of the VA compares needed, including VA bits 23 that may be contained in the page size field. In this embodiment the MUX 440 and the

24 compare 442 are not needed.

25 In some operating system environments, different virtual addresses are sometimes 26 assigned to the same physical address space. For example, an editor used by user C may 27 have a virtual address of C and a physical address of A, while another user may reference 28 the same editor with a virtual address of B. which translates to the same program at 29 physical address A. Since these users may "time-slice" execution in the same processor, 30 both users would use the same program (e.g., the editor), but "point" to it through 31 different virtual addresses. In cases like these, the cache data may be retained for both 32 users and access to the cache data may be made through different virtual addresses as the 33 users change. Address aliasing in the prevalidated tag cache system shown in Figure 4 34 may be accomplished through the use of special logic, for example.

I To accommodate address aliasing support for a prevalidated tag cache design, 2 several options are available. The options vary depending on the level of capability in 3 which the cache data can be saved when transitioning between one virtually addressed 4 space use of a specific physical cache page to another virtually addressed use of the same S page. The options include, for example: 1) not saving the cache data when a new TLB 6 entry will access part or all of the current TLB entry's physical address space; 2) saving 7 the cache data only when the page sizes are the same between the new and current TLB 8 entries; and 3) saving the cachedata when the page size of the new TLB entry is the same 9 or smaller than the current TLB entry.

10 Figure 6 shows a micro-architecture 500 for implementing address aliasing with 11 no saving of cache data. In this micro-architecture, a first user may access a program or 12 data using a first virtual address, resulting in a specific cache line. If a second user were 13 then to access the same program or data, the second user would not find the program or 14 data in the cache because the second user uses a second (different) virtual address. A 15 second cache line would then be saved in the cache with the result that the cache would 16 have two identical cache lines. This is not a desirable situation for cache design since it 17 reduces cache efficiency (lower capacity) and requires multiple cache lines to be written 18 on stores. To prevent this situation, logic may be added to invalidate one of the cache 19 lines.

20 In Figure 6, a new TLB entry 510 for insertion is shown with a page size mask 21 511, a physical address 512 and a virtual address 513. The new TLB entry 510 is 22 provided to a prevalidated cache TLB 520 that includes a PA CAM 522, a page size mask 23 524, and a VA CAM 528 with a valid bit module 526. The PA CAM 522 provides for 24 saving physical addresses in the TLB structure and the page size information for each 25 TLB entry. The physical address 512 of each new TLB entry to be inserted into the TLB 26 520 is compared with the physical addresses of all existing TLB entries masked 27 appropriately with page size information using page size mask 524 and the incoming TLB 28 page size mask 511. Upon detection of a TLB entry that overlaps a physical address 29 space of the new TLB entry, the existing TLB entry is invalidated and a valid bit is 30 provided using the valid bit module 526 with each TLB entry to allow quick invalidation.

31 In the micro-architecture 500 shown in Figure 6, the VA CAM 528 ANDs the valid bits 32 to the compare results to generate the virtual TLB hit outputs.

33 In the example shown in Figure 6, every cache line is associated with only one 34 TLB entry. When that TLB entry is invalidated, the cache line is effectively invalidated

1 and not accessible. Actual invalidation (i.e., clearing the physical TLB hit bits in the 2 prevalidated cache tags) of a cache line may be completed immediately when the TLB 3 entry is invalidated or later when a new TLB entry is assigned to the TLB slot location.

4 In an alternative design, the page size field can be deleted and all TLB entries may

5 be forced to be the smallest page size available. In this altemative, the page size 6 compares are removed. This alternative also requires that large page size TLB entries be 7 broken into multiple TLB entries for the prevalidated cache TLB520.

8 Figure 7 shows an another example of an micro-architecture that supports address 9 aliasing with saving of cache data when the page sizes are the same between new and 10 current TLB entries. A micro-architecture 600 includes a PA CAM (not shown in Figure 11 7) to save physical addresses in the TLB structure and page size information for each 12 TLB entry. The micro-architecture 600 also includes a PA CAM to compare the physical 13 address of a TLB entry to be inserted into the TLB with the physical addresses of all 14 existing TLB entries masked appropriately with page size information. Upon detection of 15 an existing TLB entry that overlaps the physical address space of a new TLB entry, the 16 micro- architecture 600 replaces the current TLB entry with the new TLB entry, retaining 17 the same TLB slot number. The cache line tags are prevalidated to the TLB slot number, 18 so the cache lines are automatically linked to the new TLB entry. The micro-architecture 19 600 prevents the TLB from maintaining two TLB entries that point to the same physical 20 address space.

21 As shown in Figure 7, the micro-architecture 600 includes a prevalidated cache 22 TLB 620. The TLB 620 includes a page size mask 630, match logic 632, a PA CAM 23 622, a page size mask 624, a VA CAM 628 and a valid bit module 626. A new TLB 24 entry 610 for insertion is shown with page size mask data 611, a physical address 612 and 25 a virtual address 613. The page size mask data 611 is provided to the page size mask 630 26 and the physical address 612 is provided to the PA CAM 622. The page size mask 630 27 checks the page size mask data 611 against all existing page size masks. The PA CAM 28 622 compares the incoming physical address 612 with each TLB entry's physical address 29 masked with the page size mask data in the page size mask 624. If the physical address 30 matches and the page size mask data are the same, the matching TLB entry number is 31 saved for inserting the new TLB 620. The virtual address is provided to the VA CAM 32 628, and the VA CAM 628 compare results are ANDed with the valid bits to generate 33 outputs as virtual TLB hits.

I If the PA CAM 622 compares indicate a match but the page size mask compares 2 indicate a different page size, then the existing TLB entry will be invalidated by clearing 3 the associated TLB valid bit in the valid bit module 626, through signal 625.

4 Address aliasing can also be supported with current TLB entries retained as valid 5 and a new TLB entry allocated to a different slot number. In this example, a RAM is 6 provided to save physical addresses in the TLB 620 structure and the page size 7 information for each entry. A CAM is provided to compare the physical address of the 8 new TLB entry to be inserted into the TLB 620 with the physical addresses of all existing 9 TLB entries masked appropriately with the page size information. Upon detection of an 10 existing TLB entry that overlaps the physical address space of the new TLB entry, the 11 cache lines from the current TLB entry are linked to the new TLB entry. A new tag 12 function of column copy is used to copy the valid bits from current TLB entry slot 13 number to the new TLB entry slot number in the prevalidated tag 734, as shown in Figure 14 8. Because a cache line may have multiple physical TLB hits in a system, more than one 15 physical TLB hit flag may be enabled when a cache line is loaded, based on a physical 16 address compare with current entries in the TLB 620. This example allows the TLB 620 17 to maintain multiple TLB entries that point to the same physical address space.

18 Figure 8 shows an example of address aliasing with a column copy tag function.

19 An architecture 700 includes a prevalidated cache TLB 720, a prevalidated cache tag 730, 20 and a data cache 740. A new TLB entry 710 for insertion is shown with page size mask 21 data 711, a physical address 712 and a virtual address 713.

22 The prevalidated cache TLB 720 includes a page size mask 736, match logic 738, 23 PA CAM 722, page size mask 724, valid bit module 726 and a VA CAM 728. The page 24 size mask data 711 from the new TLB entry 710 is checked against all existing page size 25 masks in the page size mask 736. An equal compare result is output to the match logic 26 738. The PA CAM 722 compares the new TLB physical address 712, masked with the 27 page size mask data 711 with each TLB entry's physical address, masked with the stored 28 page size mask data in the pages size mask 724. If the physical address matches and the 29 page size mask are the same, the matching entry numbers are sent to a column copy 30 function module 734 using the match logic 738. The column copy function module 734 31 is shown as an element of the prevalidated cache tag 730. The column copy function 32 module 734 will copy the hit bits from one or more existing columns into a new column 33 location. The column copy function module 734 performs an OR function when multiple 34 columns are copied. A column number is equal to a TLB enky slot number.

I If the PA CAM 722 compares indicate a match, but the page size mask compares 2 indicate a different page size, then the existing TLB entry will be invalidated by clearing 3 the associated TLB valid bit 726 through signal 725.

4 The VA CAM 728 receives virtual address data (n entries) from the TLB entry 5 710 and outputs virtual TLB hits that are ANDed with the physical TLB hits from the 6 prevalidated cache 732 using AND circuit 742. The n outputs are then ORed in OR 7 circuit 744 to produce a final cache way hit. Finally, the output of the data cache 740 is 8 multiplexed as directed by the cache way hit using multiplexer 746 to provide load data.

9 Address aliasing can also be supported in a prevalidated cache architecture by 10 saving cache data only when a new TLB entry has page sizes greater than or equal to a 11 matching current TLB entry. In this example, page sizes are compared for different TLB 12 entries and cache lines are assigned from one TLB entry to another. The architecture 13 includes memory to save physical addresses in the TLB structure and page size 14 information for each entry. A compare is provided to compare a new TLB entry to be 15 inserted into the TLB with the physical addresses of all existing TLB entries, masked 16 appropriately with page sizes information. A further compare is used to compare the 17 page size of the new TLB entry with page sizes of all existing TLB entries to determine if 18 the new TLB entry's page size is greater than or equal to that of the existing TLB entries.

19 Upon detection of a TLB entry that overlaps a physical address space of the new TLB 20 entry, and if the page size of the matching current TLB entry is smaller or equal in size to 21 the page size of the new TLB entry, the current TLB entry is retained as valid and the 22 new TLB entry is allocated to a different TLB slot number. To link the cache lines from 23 the current TLB entry to the new TLB entry, a new tag function of column copy is used to 24 copy the valid bits from one TLB entry slot number to the new TLB entry slot number.

25 Due to the ability for a cache line to have multiple physical TLB hits in the system, more 26 than one physical TLB hit may be enabled when a cache line is loaded, based on a 27 physical address compare with the current entries in the TLB. Upon detection of an 28 existing TLB entry that overlaps a physical address space of the new TLB entry, but with 29 matching current entry page size larger than the page size of the new TLB entry, the 30 current (larger) TLB entry is invalidated. Since the cache line is prevalidated to a TLB 31 entry slot number, the cache lines related to the TLB entry are also invalidated.

32 Figure 9A shows a micro-architecture 800 that supports address aliasing including 33 column copy tag function when a page size of a new TLB entry is the same size or larger 34 than a page size of an existing TLB entry. The architecture 800 includes a prevalidated

1 cache TLB 82O, a prevalidated cache tag 830, data cache 840, multiplexer 846, AND 2 circuit 842 and OR circuit 844. A new TLB entry 810 for insertion in the TLB 820 3 includes page size mask data 811, a physical address 812, and a virtual address 813. The 4 page size mask data 811 is provided to a page size mask module 836 and the physical 5 address 812 and the page size mask data 811 are provided to a PA CAM 822 and a page 6 size mask 824, respectively. In the page size mask module 836, the new page size mask 7 data 811 is checked against all existing page size masks. An equal or greater compare 8 result is output to a match logic 838. The PA CAM 822 compares the incoming physical 9 address 812, masked with the page size mask data 811, with each existing TLB entry's 10 physical address. If the physical address 812 matches a physical address of an existing 11 TLB entry, and the new page size mask data 811 is greater than or equal to a page size 12 mask corresponding to the matched TLB entry, then the match logic 838 outputs a 13 column copy enable signal. Otherwise, the match logic 838 output an invalidate signal to 14 the valid bit module 826.

15 If the current page size mask is larger than the new page size mask and the 16 physical addresses match, then the existing (older) entry is invalidated by a signal from 17 the match logic 838 to the valid bit module 826.

18 A column copy function module 834 in the prevalidated cache tag 830 copies one 19 or more existing columns of hit bits into a new column location. An OR function is 20 performed when multiple columns are copied. A column number is equal to a TLB entry 21 slot number.

22 The VA CAM 828 outputs virtual TLB hits that are ANDed together with 23 physical TLB hits from the prevalidated cache tags in the AND circuit 842. The output of 24 the AND circuit 842 is ORed in the OR circuit 844 to produce an output cache way hit.

25 The output cache way hit bits control the multiplexer 846, and select the data output from 26 the data cache 840 to produce a load data signal.

27 Figure 9B shows a micro-architecture 800' that includes the structure and 28 functions of the micro-architecture 800 of Figure 9A and the microarchitecture 400 of 29 Figure 5.

30 Figure 10 is a block diagram showing some of the functional steps executed by the 31 micro-architecture 600 shown in Figure 7. In step S100, the VA CAM 628 receives 32 virtual address information for a new TLB entry. The VA CAM 628 compares the 33 received virtual address information with virtual address information for existing entries 34 to determine virtual TLB hits. In step S110, the PA CAM 622 receives physical address

l l information for the new TLB entry and in step S120, the page size mask 630 receives 2 page size information for the new TLB entry. In step S130, the PA CAM 622 compares 3 physical addresses of the new TLB entry with physical addresses of existing TLB entries.

4 In step S140, the PA CAM 622 determines if the physical addresses match. If the 5 physical addresses do not match, in step S155, match logic 632 assigns a new TLB slot 6 number to the new TLB entry. Otherwise, if the physical addresses match, in step S 150, 7 the page sizes of the new TLB entry and the existing TLB entry are checked. In step 8 S 160, if the page sizes match, the page size mask 630 provides an output and in step 9 S 170, the match logic 632 assigns the new TLB entry a TLB slot number of the existing 10 TLB entry and the existing TLB entry is invalidated. If the page sizes do not match, a 11 new TLB entry is assigned a new TLB slot number. The process then ends.

12 The terms and descriptions used herein are set forth by way of illustration only

13 and are not meant as limitations. Those skilled in the art will recognize that many 14 variations are possible within the spirit and scope of the invention as defined in the l 5 following claims, and their equivalents, in which all terms are to be understood in their 16 broadest possible sense unless otherwise indicated.

Claims

I In The Claims:

2 1. An apparatus that supports multiple page sizes with address aliasing in a computer 3 architecture having a prevalidated cache, comprising: 4 a prevalidated cache translation lookaside buffer (TLB), the TLB comprising: 5 a virtual address content addressable memory (CAM), 6 a first page size mask random access memory (RAM), 7 a variable page size address RAM; and 8 a prevalidated cache tag operably coupled to the TLB.

9
2. The apparatus of claim 1, wherein the first page size mask RAM comprises a page 10 size mask, wherein the page size mask has a size y comparable to a size of the 11 prevalidated cache, and wherein the page size mask bits are reduced to less than y bits 12 when not all power-ofhvo page sizes are supported by the prevalidated cache.

13
3. The apparatus of claim 1, wherein the variable pages size address RAM holds a 14 virtual address for a page size region of y bits for a TLB entry, and wherein when the 15 TLB supports more than one entry aliased to a same physical address, the variable pages 16 size address RAM comprises multiple outputs.

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4. The apparatus of claim 1, wherein the prevalidated cache tag comprises a tag 18 physical address RAM that holds y physical address bits corresponding to a range of page 19 sizes supported by the prevalidated cache.

20
5. The apparatus of claim 4, wherein the prevalidated cache tag comprises physical 21 TLB hit bits, and wherein the physical address bits of the physical address RAM are read 22 out in parallel with read out of the physical TLB hit bits.

23
6. The apparatus of claim 1, wherein the virtual address CAM comprises: 24 comparison means for comparing virtual address bits with an incoming virtual 25 address; and 26 TLB hit bit generation means for generating virtual TLB hit bits based on the 27 comparison. 28
7. The apparatus of claim 6, wherein the TLB comprises means for reading out the 29 page size mask RAM and the variable page size address RAM for a generated virtual 30 TLB hit bit.

31
8. The apparatus of claim 7, further comprising selection means for selecting 32 whether address information provided by the reading means is a physical address or a 33 virtual address, wherein address bit are generated.

34
9. The apparatus of claim 8, further comprising:

1 1 I means for grouping selected address bits, wherein a field of y address bits is

2 formed; and 3 a bit comparator that compares the field of y address bits as a group and

4 corresponding bit positions of a virtual address.

5
10. The apparatus of claim 9, further comprising hit generation means, wherein when 6 the comparison is equal, a final cache way hit is generated.

7
11. An apparatus that supports multiple page size regions with address aliasing in a 8 computer system having a prevalidated tag cache and a translation lookaside buffer 9 (TLB), comprising: 10 a virtual address content addressable memory (CAM) that receives virtual address 11 information for a new TLB entry; 12 a physical address CAM that receives physical address information for the new 13 TLB entry, wherein the physical address CAM compares the physical address information 14 of the new TLB entry with the physical address information of each of existing TLB 15 entries, wherein if the physical address information of the new TLB entry matches the 16 physical address information of one of the existing TLB entries, the matched existing 17 TLB entry is invalidated, and wherein the TLB comprises 18 logic to support multiple page sizes, the logic comprising:

19 a page size mask random access memory (RAM) that holds a page size 20 mask and provides a first output signal, 21 a virtual page size address RAM that holds a virtual address for a page size 22 region of all existing TLB entries and provides a second output signal, and 23 a multiplexer; and 24 a tag physical address RAM that holds physical address bits corresponding to a 25 range of page sizes and provides a third output signal, wherein the multiplexer receives 26 the first, second and third output signals and provides a partial TLB hit signal.

27
12. The apparatus of claim 11, further comprising a page size mask module coupled to 28 the physical address CAM that receives a page size for the new TLB entry and compares 29 the page size of the new TLB entry with page sizes of the existing TLB entries.

30
13. The apparatus of claim 11, further comprising a valid bit module that provides a 31 valid bit with each TLB entry for the invalidation.

32
14. The apparatus of claim 11, wherein the prevalidated tag cache has one or more 33 cache lines, and wherein each cache line is associated with one TLE} entry.

t 1
15. The apparatus of claim 11, wherein the prevalidated tag cache has one or more 2 cache lines associated with the TLB entries, and wherein a cache line associated with the 3 matched existing TLB entry is invalidated when the matched existing TLB entry is 4 invalidated. 5
16. The apparatus of claim 11, wherein the prevalidated tag cache has one or more 6 cache lines associated with the TLB entries, and wherein a cache line associated with the 7 matched existing TLB entry is invalidated after the new TLB entry is assigned to a TLB 8 slot. 9
17. The apparatus of claim I 1, further comprising: 10 a prevalidated cache tag array that provides TLB hits; 11 a page region comparator that receives the partial TLB hit signal and virtual 12 address information, performs a page size comparison and provides page size hits; and 13 a hit generation logic circuit that receives TLB hits from the virtual address CAM, 14 hits from the prevalidated cache tag array, and hits from the page size comparator, 15 wherein when the page size comparison indicates a match, the comparator provides an 16 output signal to the hit generation logic circuit, the hit generation logic circuit providing a 17 cache way hit.

18
18. A method for supporting address aliasing in a computer system having a 19 prevalidated cache tag and a translation lookaside buffer (TLB), comprising: 20 receiving a virtual address for a new TLB entry in a virtual address content 21 addressable memory (CAM); 22 receiving a physical address for the new TLB entry in a physical address CAM; 23 and 24 comparing the physical address of the new TLB entry with physical addresses of 25 existing TLB entries; and 26 if the physical address of the new TLB entry matches one of the physical 27 addresses of the existing TLB entries, invalidating the matched existing TLB entry.

28
19. The method ofclaim 18, further comprising: 29 receiving a page size for the new TLB entry in a page size mask; 30 comparing the page size for the new TLB entry with page sizes of the existing 31 TLB entries; 32 when the page size of the new TLB entry matches a page size of an existing TLB 33 entry, assigning the new TLB entry to a TLB slot of the matched existing TLB entry.

34
20. The method of claim 18, further comprising:

I holding a page size mask in a memory and providing a first output signal 2 indicative of the page size; 3 holding a virtual address for existing TLB entries and providing a second output 4 signal; 5 holding a physical address corresponding to a range of page sizes and providing a 6 third output signal; and 7 multiplexing the second and third output signals by the control on the first output 8 signal to provide a partial TLB hit signal.

9
21. The method of claim 20 in a prevalidated cache tag array, further comprising: 10 providing TLB hits; 11 comparing page size information based on virtual address information and the 12 partial TLB hit signal; 13 receiving the TLB hits and page size hits; and 14 when the page size comparison indicates a match, providing an output signal to a 15 hit generation logic, the hit generation logic providing a cache way hit.

16
22. A computer system that supports multiple page sizes and addressing aliasing, 17 comprising: 18 a translation lookaside buffer (TLB), comprising: 19 a virtual address content addressable memory (CAM) that receives virtual 20 address information for a new TLB entry; and 21 a physical address CAM that receives physical address information for the 22 new TLB entry, wherein the physical address CAM compares the physical address 23 information of the new TLB entry with the physical address information of each of 24 existing TLB entries, wherein if the physical address information of the new TLB entry 25 matches the physical address information of one of the existing TLB entries, the matched 26 existing TLB entry is invalidated.

27
23. The computer system of claim 22, further comprising: 28 a page size mask module coupled to the physical address CAM that receives a 29 page size for the new TLB entry and compares the page size of the new TLB entry with 30 page sizes of the existing TLB entries; 31 a valid bit module that provides a valid bit with each TLB entry for the 32 invalidation, wherein the prevalidated tag cache has one or more cache lines, and wherein 33 each cache line is associated with one TLB entry.