JPH10254782A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of performance owing to the long stay of unnecessary data which are temporarily used in a cache memory and are not used later. SOLUTION: At the time of giving a memory reference instruction from a CPU to the cache memory 3, flag information showing that a register is used for generating a request memory address and the memory address are stored in the pertinent register of a register file 2. On a CPU-side, an instruction for making replacement selection priority on a cache memory 3-side the highest is transmitted to the cache memory 3 on the memory addresses stored in a pair when the contents of a register generating the memory addresses before are changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing device (computer system) having a cache memory.

[0002]

2. Description of the Related Art In a current computer system, it is common to equip a cache memory to supply data requested by a CPU at a high speed. FIG. 9 is a diagram illustrating a configuration example of a conventional data processing device (computer system). 9, reference numeral 200 denotes an instruction buffer; 201, a register file; 202, an operation pipeline unit; 203, a load / store pipeline unit;
04 is a cache memory, 205 is a main memory, 300 is a tag / data section, and 301 is a replacement control section.

Normally, a portion including an instruction buffer 200, a register file 201, an operation pipeline unit 202, and a load / store pipeline unit 203 is represented by C
Called PU. The tag / data section 300 of the cache memory 204 is configured by an entry including a set of an address, data, and a valid bit. When the CPU performs a memory read, a control unit (not shown) in the cache memory 204 has an address in the tag / data unit 300 that matches the read address, and the valid bit is v
A search is made to see if there is an entry that is valid (valid), and if so, the value of the data part is sent to the CPU. If not, a read request is made to the main memory 205, the data sent from the main memory 205 is sent to the CPU, and the replacement control unit 301 selects an entry of the tag / data unit 300 based on a certain standard (selection of entry), and Is written to the entry, and the valid bit of the entry is set to valid.

When the CPU performs memory writing, C
The PU sends a write address and data to the cache memory 204. The cache control unit (not shown) searches the tag / data unit 300 for an entry that has an address that matches the write address and has an entry whose valid bit is valid, and if so, sends the value of the data unit from the CPU. Rewrite with the data that came. If not, the replacement control unit selects an entry of the tag / data unit 300 based on a certain criterion (selection of an entry), and the address and C
The data sent from the PU is written, and the valid bit of the entry is set to valid.

[0005] In selecting an entry to which a new entry is to be assigned, what criteria is used to select the entry affects the performance of the computer system. direct m
In a cache memory called an applied cache, there is only one cache entry that can be assigned to a certain address, and there is no choice. Therefore, if the entry is currently used, the data is discarded, so that very good performance cannot be obtained.

[0006] n set associative c
The cache memory called “ache” is a system in which there are n cache entries that can be assigned to a certain address. By selecting an entry having data that is least likely to be used in the future from among the n candidates and writing new data, direct
Better performance can be obtained than with mapped cache. However, increasing n requires a large amount of hardware, so it is required to select an appropriate entry while n is kept small.

[0007] set associative cac
In selecting an entry for he, the conventional method is L
It is based on the RU method. That is, assuming that recently used data is likely to be used again, an entry with the oldest used time is selected with a higher priority.

[0008]

However, in this method, even data that is used only temporarily is stored in a cache memory immediately after being used, and it is difficult to select data until a certain time elapses. No. This means that unnecessary data is held in the cache memory for a long time, which leads to performance degradation.

As an example, consider the case where the following two instructions are executed consecutively. The store instruction (store) of store reg1 + 100, reg2 add reg1, 32, reg1 is an instruction to store the value of the second operand at the memory address specified by the first operand. In the instruction example, the operation of storing the contents of the register reg2 at a memory address consisting of a value obtained by adding a constant value 100 to the contents of the register reg1 is executed. Is an instruction for adding the value of the first operand and the value of the second operand and storing the result in the third operand. In this example, the constant value 32 is added to the contents of the register reg1, and the result of the addition is stored in the register reg1.

When the instruction of (1) is executed, the contents of the register reg1 are used for generating a memory address, and the access to the cache memory is executed at the memory address, whereby the replacement selection order of the memory address based on the contents of the register reg1 is changed. Lowest. Next, when the instruction is executed, the content of the register reg1 is rewritten to a different value. In that case, there is almost no possibility that the value before rewriting of the register reg1 will be used again for generating the memory address in the near future.

As a result, in the cache memory,
A memory address that is extremely unlikely to be used in the near future will remain at the priority that is not replaced the most, and will not be used for cache memory until a certain time elapses and the replacement selection order of the own memory address becomes the highest. Will be left as is. SUMMARY OF THE INVENTION It is an object of the present invention to prevent performance degradation caused by unnecessary data remaining in a cache memory for a long time.

[0012]

According to the present invention, a command transmitted from a CPU to a cache memory, which instructs a cache entry having a certain address to increase the priority of the selection (refer to FIG. 1). pri
Ority command) is prepared. By using the command, the CPU performs the replacement control in the cache memory to some extent, thereby expediting the eviction of unnecessary data from the cache.

FIG. 1 is a diagram showing a first principle configuration of the present invention. In FIG. 1, 1 is an arithmetic unit, 2 is a register file, 3 is a cache memory, and 4 is a main memory. The portion including the arithmetic unit 1 and the register file 2 constitutes a CPU. In the configuration of FIG.
When the CPU issues a request to the cache memory 3, the CPU stores the register name and the address used to generate the address of the request. On the CPU side, when the register contents (value) of the register used to generate the address change, a command (priority) for increasing the selection priority in the cache memory 3 for the address stored as a pair. Command) to the cache memory 3.

This means that when accessing the memory, the address is indicated by a certain register (or register + constant value). However, the fact that the value of the register has changed means that the address indicated by the value before the change is not accessed. This is the control based on the high possibility.
An address field and a valid flag (valid bit) are added to the register file 2 in FIG. 1 in addition to a field for storing normal data. When the memory is referred to by the value of the register (or the register + constant value), the address is written into the address field, and the valid bit is set to the valid state. Thereafter, when the value of the register is rewritten, the valid bit is set to inva.
lid. At this time, the valid bit is originally valid
If so, a command for increasing the selection priority in the cache memory is sent to the cache memory together with the corresponding address field value.

FIG. 2 is a diagram showing a second principle configuration of the present invention. As in FIG. 1, 1 is an operation unit, 2 is a register file, 3 is a cache memory, 4 is a main memory, and a portion including the operation unit 1 and the register file 2 constitutes a CPU. In the configuration of FIG.
Information on whether to increase the selection priority in the cache memory 3 is added to the memory reference request from U (priority
cache request with ity). As an instruction, in addition to a normal memory reference instruction, priority
Add a memory reference instruction with a cache request.

In code generation by a compiler,
We analyze the number of times of writing to each variable. In this analysis, a memory reference instruction with a cache request with priority is issued for the last reference to the variable. As shown in FIG. 2, signal lines from the CPU to the cache memory 3 include:
In addition to the normal access address / data signal line, a priority change control instruction line (priority bit) indicating whether or not the request has priority
Is added. The replacement control unit in the cache memory controls the selection priority according to the value of this bit.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of the first embodiment of the present invention. 3, reference numeral 10 denotes an instruction buffer, 11 denotes a register file, 12 denotes an operation pipeline unit, 13 denotes a load / store pipeline unit, 14 denotes a priority control determination unit, 15 denotes a cache memory, 16 denotes a main memory, and 17 denotes a main memory. Tag / data part, 18
Is a replacement control unit, 20 is a normal processing field in the register file, 21 is an address holding field, 22 is a valid flag holding field, 30 is a data signal line, 31 is an address signal line, and 32 is a priority change control instruction line. , 33 are priority change target address signal lines.

In FIG. 3, parts other than the cache memory 15 and the main memory 16 constitute a CPU. When the instruction in the instruction buffer 10 is an arithmetic instruction, the arithmetic pipeline unit 12 executes the specified arithmetic processing on the contents of the normal processing field 20 of the register file 11. If the instruction in the instruction buffer 10 is a load instruction, the load / store pipeline unit 13 reads out data from the cache memory 15 and
It is stored in the normal processing field 20 of the file 11.
If the instruction in the instruction buffer 10 is a store instruction, the load / store pipeline unit 13 reads out the contents of the normal processing field 20 of the register file 11 and stores it in the cache memory 15.

In the first embodiment of the present invention, the register file 11 is provided with an address holding field 21 and a valid flag holding field 22 in addition to the normal processing field 20. Is referred to. When a memory reference address is generated based on the value of the register (the value stored in the normal processing field 20), the address holding field 21 stores the memory reference address itself. Specifically, the memory reference address of the instruction is written into the address holding field 21 of the register passed as the operand of the load / store instruction.

The valid bits stored in the valid flag holding field 22 correspond to the corresponding address holding field 2
It indicates whether the value of 1 is valid or not. Set to “1” when a memory reference address is written to the address holding field 21 by a load / store instruction, and set to “0” when a value is written to the normal processing field 20 by another instruction. You.

When the valid bit of the valid flag holding field 22 changes from "1" to "0", the value of the address holding field 21 and the priority change control are controlled under the control of the priority control determining unit 14. The instruction information (priority command) is transmitted to the cache memory 15 through the priority change target address signal line 33 and the priority change control instruction line 32.

When the cache memory 15 receives the priority change control instruction information (priority command), the cache memory 15 searches the tag / data section 17 with the address transmitted in the same manner as in the normal operation. If the address does not exist on the tag / data section 17, nothing is performed. On the other hand, if the address exists on the tag / data section 17, the replacement control section 18 changes the priority of selection of the address on the tag / data section 17 to a predetermined order (for example, the highest order). .

FIG. 4 is a diagram showing a flow of processing in the first embodiment. As processing on the CPU side, step 1
The instruction type is determined in (S1), and if the instruction is a load / store instruction, the memory reference address is written to the address holding field 21 of the operand register in step 2.
Further, in step 3, a valid bit "1" is set in the valid flag holding field 22 of the operand register.

If it is determined in step 1 (S1) that the instruction is to set a value in the register, the value of the valid bit in the valid flag holding field 22 of the operand register is determined in step 4 (S4). If the valid bit is "1", the priority change control instruction information (priority command) and the contents of the address holding field 21 are sent to the cache memory 15 in step 5 (S5). Then, in step 6 (S6), the valid bit of the valid flag holding field 22 of the operand register is set to "0".

As the processing on the cache memory 15 side, the request type is determined in step 7 (S7), and if it is a read / write request, normal cache processing is performed. If the request type is determined to be a priority change request in step 7 (S7), then in step 9 (S9), the corresponding cache entry for the address sent on the priority change target address signal line 33 is changed to the normal cache entry. It is obtained in the same manner as the cache processing.

In step 10 (S10), it is determined whether the corresponding entry exists in the cache memory.
If it does not exist in the cache memory, nothing is done. If it exists in the cache memory, step 11 (S
In 11), the replacement selection priority of the entry is set to the highest. FIG. 5 is a diagram showing an example of a change in the contents of the register file 11. In the initial state, it is assumed that “100” is set in the normal processing field 20 of the register 1 and “0” is set in the valid flag holding field 22. Here, it is assumed that the above-mentioned instruction, store reg1 + 100, reg2, has been executed. After execution of the instruction, the value of the normal processing field 20 of the register 1 does not change, but the generated memory address value “200” is set in the address holding field 21, and the valid bit “ "1" is set.

Next, it is assumed that the above-mentioned second instruction, add reg1, 32, reg1, has been executed. After the execution of the instruction, the normal processing field 20 of the register 1 stores "13" of the value of the addition result.
2 "is set. At this time, since the value of the valid flag holding field 22 is “1”, the value “200” of the address holding field 21 is sent to the cache memory, and then the value of the valid flag holding field 22 is set to “0”. Is done.

The priority of the replacement selection of the corresponding cache entry becomes higher when the value of the register pointed to by the address is changed by the processing of the first embodiment. When a new cache entry is needed, this cache entry is used and unnecessary data is evicted from the cache memory.

FIG. 6 is a block diagram of a second embodiment of the present invention. 6, 10 is an instruction buffer, 11 is a register file, 12 is an operation pipeline unit, 1
3 is a load / store pipeline unit, 15 is a cache memory, 16 is a main memory, 17 is a tag / data section,
18 is a replacement control unit, 30 is a data signal line, 31 is an address signal line, 32 is a priority change control instruction line, 40 is a priority change control instruction bit unit in the instruction buffer, and 41 is a priority in the load / store pipeline unit. This is a change control instruction bit section.

In FIG. 6, portions other than the cache memory 15 and the main memory 16 constitute a CPU. If the instruction in the instruction buffer 10 is an operation instruction, the operation pipeline unit 1
2 executes the designated arithmetic processing. Instruction buffer 10
Is a load instruction, the load / store pipeline unit 13 reads data from the cache memory 15 and stores it in the register file 11. If the instruction in the instruction buffer 10 is a store instruction, the load / store pipeline unit 13 reads out the contents of the register file 11 and stores it in the cache memory 15.

In the second embodiment of the present invention, in addition to a normal memory reference instruction, a memory reference instruction (p
(memory reference instruction with cache request with priority). As hardware, as shown in FIG. 6, priority change control instruction bit units 40 and 41 are provided in the instruction buffer 10 and the load / store pipeline unit 13, and a request is sent as a signal line from the CPU to the cache memory. priori
A priority change control instruction line 32 indicating whether or not ty is attached is added.

A memory reference instruction with a cache request with priority differs from a normal memory reference instruction only in that a request is issued to the cache memory when the priority bit is "1". The compiler issues a cache reference with priority and a memory reference with cache request for the last reference to each variable. FIGS. 7 and 8 show an example of compiling. 7 shows a case where there is no conditional branch, and FIG. 8 shows a case where there is a conditional branch.

In FIG. 7, the compiler sets an instruction group (a [0] = 1, a [0]) that refers to the same variable from the original program.
.. A [0] = n), and the last reference instruction (a [0] = n in the example of FIG. 7) includes a memory reference instruction with a cache request with priority (FIG. 7). Issues priority-store reg1 + 0, a). In the case of FIG. 8, as in the case of FIG. 7, an instruction group that refers to the same variable is detected from the original program. 8, a memory reference instruction with a cache request with priority (in the example of FIG. 8, priority-store reg1
+ 0, 10 and priority-store reg1 + 0, 9).

When a request is received with the priority bit on the priority change control instruction line 32 being "1", the cache memory 15 of FIG. 6 performs normal cache processing, and then performs priority selection for replacement selection of the corresponding cache entry. To the highest degree. This, in turn,
When a new cache entry is needed,
This cache entry is used, and unnecessary data is evicted from the cache.

[0035]

As described above, according to the present invention,
Unnecessary data can be quickly expelled from the cache memory, the effective use of the cache memory is improved, and high-speed data processing can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first principle configuration of the present invention.

FIG. 2 is a diagram showing a second principle configuration of the present invention.

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is a diagram showing a processing flow in the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of the contents of a register file according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of a second embodiment of the present invention.

FIG. 7 is a diagram illustrating an example (part 1) of a compile operation according to the second embodiment of the present invention;

FIG. 8 is a diagram illustrating a compile operation example (part 2) according to the second embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration example of a conventional data processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Operation unit 2 Register file 3 Cache memory 4 Main memory 21 Address holding field 22 Valid flag holding field 32 Priority change control instruction line 40, 41 Priority change control instruction bit section

Claims (3)

[Claims] When a memory reference instruction is issued from a processing unit to a cache memory, address generation register instruction information indicating that a register has been used to generate a requested memory address, and the memory address are stored in a corresponding register. When the processing unit detects, based on the address generation register instruction information, that a write operation to the register has been performed with respect to a register for which a memory address has been previously generated, A data processing device configured to send, to a cache memory, a memory address stored in association with a corresponding register and information instructing to increase the replacement selection priority for the memory address. 2. A processing unit having a built-in register file, a cache memory, and a main memory.
A data processing device having a configuration for performing a read / write operation between a file and a cache memory, and when the processing target data does not exist in the cache memory, reading the processing target data from the main storage and writing the data to the cache memory. A memory address holding area and a valid flag holding area for holding a valid flag indicating the validity of the contents of the memory address holding area are provided in each entry of the file, and a memory address is generated when a load instruction and a store instruction are executed. Write the generated memory address to the memory address holding area of the register used for this purpose, turn on the valid flag of the corresponding valid flag holding area, and write to the register file using instructions other than load and store instructions. When doing the register If the valid flag of the corresponding entry in the file is on, the memory address written in the corresponding memory address holding area is sent to the cache memory, and an instruction is given to increase the replacement priority of the memory address in the cache memory. A data processing device for setting a valid flag of a corresponding entry in a register file to an off state. 3. A processing unit having a built-in register file, a cache memory, and a main memory. When data to be processed exists in the cache memory, read / write operations are performed between the register file and the cache memory. When the data to be processed does not exist in the cache memory, the data processing apparatus has a configuration in which the data to be processed is read from the main memory and written to the cache memory, and information for instructing to increase the replacement priority in the cache memory is provided. A memory reference instruction with a replace priority change function is provided, and the instruction that becomes the last reference to the variable in the group of instructions that makes a series of references to each variable at compile time refers to the memory with the replace priority change function Issue an instruction, and when executing the instruction, 1. A data processing apparatus, wherein when a functionable memory reference instruction is executed, a cache memory is instructed to increase the replacement priority of a memory address referenced by the instruction.