JP2927160B2 - Register device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and a register device in a microcontroller.

[0002]

2. Description of the Related Art A conventional register device is disclosed, for example, in Japanese Patent Application Laid-Open No. Hei 4-90038. FIG. 3 is a block diagram of a system using the conventional register device, and FIG. 4 is a program showing an operation example of the conventional example. 1 is a register device, 2 is an instruction execution unit, 3 is a data cache memory, 4 is a main storage device, 9 is a memory unit of the register device 1 for storing data in each entry, and 15 is a register including a write detection circuit. 100 and 101 are an access request signal and a read / write signal for accessing the register device 1 from the instruction execution unit 2, and 103 is an address bus for selecting an entry in the memory unit 9. , 105 are data buses for reading and writing to and from the memory unit 9, and 107 is a prefetch request signal. Also,
Reference numeral 110 denotes data transfer means between the instruction execution unit 2 and the data cache memory 3, and reference numeral 120 denotes data transfer means between the data cache memory 3 and the main storage device 4. The operation of the conventional register device configured as described above will be described with reference to FIG. It should be noted that the register device 1 in the conventional example has four registers, which are called registers r0, r1, r2, and r3, respectively.

(1) set r0, ADDR This is an instruction to set the address ADDR in the register r0. AD
DR is an address where data obtained later in the register r2 is stored. In response to this instruction, the instruction execution unit 2 asserts the access request signal 100, enables the read / write signal 101 to write enable, and sets the address bus 10
3 and outputs the address of the register r0 to the data bus 105.
To output the value of address ADDR. The control circuit 15 enables the read / write signal 200 because the access request signal 100 is asserted and the read / write signal 101 is write-enabled, and the memory unit 9 selects the entry selected by the address bus 103. Is written to the data bus 105. Further, the control circuit 15 enables the read / write signal 200 to read and asserts the prefetch request signal 107. Since the read / write signal 200 is asserted, the memory unit 9 outputs the data of the entry selected by the address bus 103 to the data bus 105. When the prefetch request signal 107 is asserted, the data cache memory 3 outputs a data bus (prefetch address bus).
Prefetch is performed with 105 as an address. In the prefetch, the requested address is stored in the data cache memory 3
If not, the data is read from the main storage device 4 and stored in the data cache memory 3. Thus, data having the address ADDR as an address can be prefetched into the data cache memory 3. Also, the prefetch is automatically performed in the same manner even when the value of the register r0 is changed from the next time. Thereafter, while the data cache memory 3 is performing prefetch, the instruction execution unit 2 can execute other instructions. Is executed.

[0004] (2) load r2, [r0] This is an instruction to store data having the value of the register r0 as an address in the register r2. Since the data having the address of the register r0 as the address is stored in the data cache memory 3 by the prefetch of (1), the reading to the data cache memory 3 is hit, and the main storage device 4 is not accessed. Can be read.

(3) set r1, DATA An instruction to set data DATA in the register r1. This instruction also sets the value in register r1 in the same way as instruction (1),
Prefetch of data having the data DATA as an address is performed.

[0006]

However, in the above configuration, when the value of the register is changed, the changed value is always prefetched regardless of the address and data. For example, the data DA in the instruction (3) in FIG.
TA is not an address, but prefetch has been performed. Such prefetch execution is useless processing,
The time required to execute such prefetch is a factor that degrades performance. Further, since data that should not be used is stored in the data cache memory, usable data is replaced from the data cache memory, and the hit rate of the data cache memory is reduced.
Furthermore, when the value of the data DATA is an inappropriate value as an address, exception processing that does not originally occur, such as a memory access violation, may be caused.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a register device that does not perform useless prefetch by changing a register that holds non-address data.

[0008]

Means for Solving the Problems The present invention, in a processor register, a plurality of entries, the each entry, read by the instruction execution unit of the processor
Out, and a memory unit having a pointer attribute field that holds a writable pointer attribute by the data field <br/> de and the instruction execution unit that holds a writable data, from the instruction execution unit to the memory unit A write detection circuit for detecting that a write has been performed; reading means for reading data of the data field of the entry and a pointer attribute of the pointer attribute field where the write has been performed when the write is detected; If it is a register device having means to issue a prefetch request to the de-<br/> chromatography data was read out by said reading means to the data cache memory and prefetch address.

[0009]

According to the above configuration, the registers that perform prefetching by updating can be limited to those having the pointer attribute, so that useless prefetching due to the change of the register that holds non-address data is prevented. Therefore, performance degradation due to useless prefetch can be eliminated, and a decrease in hit rate can be avoided by storing unused data in the data cache memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A register device according to an embodiment of the present invention will be described.
This will be described with reference to the drawings. FIG. 1 is a block diagram of a system using a register device according to an embodiment of the present invention, and FIG. 2 is a program showing an operation example of the embodiment.

In FIG. 1, 1 is a register device, 2 is an instruction execution unit, 3 is a data cache memory, and 4 is a main storage device. 9 is a memory unit of the register device 1,
Numerals 10 and 11 denote a data field and a pointer attribute field of the memory unit 9, respectively, 12 a control circuit of the register device 1 including a write detection circuit, 13 a pointer attribute signal 104 of 1 and a prefetch enable signal 106
Is asserted, the prefetch request signal 10
7 is a prefetch request signal generation circuit that asserts 7 and deasserts the rest. Reference numerals 100 and 101 denote an access request signal and a read / write signal for access from the instruction execution unit 2 to the register device 1, reference numeral 102 denotes a pointer attribute control signal for setting / resetting a pointer attribute, and reference numeral 103 denotes an entry in the memory unit 9. Is a pointer attribute signal for reading and writing the pointer attribute field; 104 is a data bus for reading and writing the data field 10; and 106 is a register from the instruction execution unit to the register. A prefetch enable signal for generating a prefetch by writing to the device 1; 107, a prefetch request signal from the register device 1 to the data cache memory 3; 200, control of reading or writing to the data field 10 Read / write signal 201, pointer attribute field 1
1 is a read / write signal for controlling the read or write for 1. 110 is a data transfer means between the instruction execution unit 2 and the data cache memory 3;
Reference numeral 0 denotes a data transfer unit between the data cache memory 3 and the main storage device 4.

The operation of the register device configured as described above will be described with reference to FIG. 1 in the order of the program shown in FIG.
Note that the register device 1 in this embodiment has four entries and corresponds to four registers. The four registers are respectively called registers r0, r1, r2, and r3.

(1) pointer r0 This is an instruction to set the pointer attribute of the register r0. This instruction causes the instruction execution unit 2 to access the access request signal 1
00 and the pointer attribute control signal 102 are asserted, the address of the register r0 is output to the address bus 103, and 1 is output to the pointer attribute signal 104. Since the access request signal 100 and the pointer attribute control signal 102 are asserted, the control circuit 12 enables the read / write signal 201 to be write-enabled. The memory unit 9 writes the value of the pointer attribute signal 104 to the entry of the pointer attribute field 11 selected by the address bus 103 in response to the read / write signal 201. As a result, the instruction execution unit 2 sets the pointer attribute bit of the register r0 to 1
Write.

(2) data r1 This is an instruction to reset the pointer attribute of the register r1.
With this instruction, the instruction execution unit 2 asserts the access request signal 100 and the pointer attribute control signal 102, outputs the address of the register r1 to the address bus 103, and outputs 0 to the pointer attribute signal 104. The control circuit 12 includes an access request signal 100 and a pointer attribute control signal 102
Is asserted, the read / write signal 201 is
Is write enabled. Read / write signal 201
Accordingly, the memory unit 9 writes the value of the pointer attribute signal 104 to the entry of the pointer attribute field 11 selected by the address bus 103. As a result, the instruction execution unit 2 writes 0 to the pointer attribute bit of the register r1.

(3) set r0, ADDR This is an instruction to set the address ADDR in the register r0. The address ADDR is an address where data obtained later in the register r2 is stored. With this instruction, the instruction execution unit 2 asserts the access request signal 100, enables the read / write signal 101 to write, outputs the address of the register r0 to the address bus 103, and outputs the value of the address ADDR to the data bus 105. Control circuit 12
Enable the read / write signal 200 because the access request signal 100 is asserted and the read / write signal 101 is write enabled. In response to the read / write signal 200, the memory unit 9 writes the value of the data bus 105 to the entry selected by the address bus 103 of the data field 10.

Further, the control circuit 12 enables the read / write signals 200 and 201 to read and asserts the prefetch enable signal 106. The read / write signals 200 and 201 cause the memory unit 9 to transfer the data of the entry selected by the address bus 103 of the data field 10 and the pointer attribute field 11 to the data bus 105 and to transfer the pointer attribute to the pointer attribute signal 10.
4 is output. The pointer attribute signal 104 and the prefetch enable signal 106 are input to the prefetch request signal generation circuit 13, and the prefetch request signal 107 is asserted because the pointer attribute signal 103 is 1 and the prefetch enable signal 106 is asserted. When the prefetch request signal 107 is asserted, the data cache memory 3 performs prefetch using the data bus (prefetch address bus) 105 as an address. In the prefetch, when the requested address is not in the data cache memory 3, data is read from the main storage device 4 and stored in the data cache memory 3. Thus, data having the address ADDR as an address can be prefetched into the data cache memory 3. Similarly, the prefetch is automatically performed in the subsequent change of the value of the register r0, and continues until the pointer attribute is reset. After this instruction, while data cache memory 3 is prefetching, instruction execution unit 2 can execute another instruction. Therefore, several instructions until the prefetch is completed perform memory access and pointer change. Assume that no instruction is being executed.

(4) load r2, [r0] This is an instruction to store data having the value of the register r0 as an address in the register r2. The instruction execution unit 2 asserts the access request signal 100 and reads / writes the read / write signal 101
Is read enabled, and the address of the register r0 is output to the address bus 103. The control circuit 12 enables the read / write signal 200 to be read, and the memory section 9 outputs the data of the entry selected by the address bus 103 of the data field 10 to the data bus 105. The instruction execution unit 2 reads the data on the data bus 105 from the data cache memory 3 as an address. In this case, since the prefetch is performed by the instruction (3), a hit occurs in the data cache memory 3, and the data can be read immediately. Next, the instruction execution unit 2 asserts the access request signal 100, enables the read / write signal 101 to write, outputs the address of the register r2 to the address bus 103, and outputs the data bus 1
At 05, the data read from the data cache memory 3 is output. The control circuit 12 outputs the access request signal 1
00 is asserted and the read / write signal 101
Is write enabled, the read / write signal 200 is write enabled. The memory unit 9 writes data on the data bus 105 to an entry of the data field 10 selected by the address bus 103.
By doing so, the data cache memory 3 does not hit the data having the address of the register r0 as a mishit,
It can be stored in register r2. Where load r2,
Even in the case of an effective address such as [r0 + 4], if it is within one line of the data cache memory 3, the data cache memory 3 hits similarly.

(5) set r1, DATA This is an instruction to set data DATA in the register r1. This instruction causes the instruction execution unit 2 to access the access request signal 10
0 is asserted, the read / write signal 101 is write-enabled, the address of the register r1 is output to the address bus 103, and the value of the data DATA is output to the data bus 105. The control circuit 12 enables the read / write signal 200 because the access request signal 100 is asserted and the read / write signal 101 is write enabled. The read / write signal 200 causes the memory unit 9 to add the data bus 10 to the entry selected by the address bus 103 of the data field 10.
Write the value of 5. Further, the control circuit 12 makes the read / write signals 200 and 201 read-enable, and asserts the prefetch enable signal 106. The memory unit 9 outputs the data of the entry selected by the address bus 103 of the data field 10 and the pointer attribute field 11 to the data bus 105, and outputs the pointer attribute to the pointer attribute signal 104. Pointer attribute signal 1
03 and the prefetch enable signal 106 are input to the prefetch request signal generation circuit 13, and the pointer attribute signal 103 is 0 and the prefetch enable signal 106 is asserted, so that the prefetch request signal 107 is deasserted. The data cache memory 3 does not execute prefetch because the prefetch request signal 107 is deasserted.

As described above, the pointer attribute of each register can be set by the instruction, and the prefetch is performed only when the register in which the pointer attribute is set is updated.

Although the present embodiment shows an example of a load instruction, the same applies to a store instruction.

[0021]

As described above, according to the present invention, the pointer attribute of each register can be set by the instruction, and the prefetch is performed only when the register in which the pointer attribute is set is updated. Therefore, compared to the case where the prefetch is performed for all register updates as in the case of the conventional register device, unnecessary prefetch execution time is not required, so that the prefetch can be performed effectively and the performance can be improved. .

Further, it is possible to avoid a decrease in the hit rate due to the storage of unused data in the data cache memory due to useless prefetch in the conventional register device, and the effect is large.

[Brief description of the drawings]

FIG. 1 is a system block diagram using a register device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a program showing an operation example in the embodiment of the present invention.

FIG. 3 is a system block diagram using a register device in a conventional example of the present invention.

FIG. 4 is an explanatory diagram showing a program showing an operation example in a conventional example of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 register device 2 instruction execution unit 3 data cache memory 4 main storage device 9 memory unit of register device 10 data field of memory unit 9 pointer attribute field of memory unit 12 control circuit including write detection circuit 13 prefetch request signal generation Circuit 100 Access request signal 101 Read / write signal 102 Pointer attribute control signal 103 Address bus 104 Pointer attribute signal 105 Data bus

Claims (1)

(57) [Claims] 1. A processor of the register has a plurality of entries, the each entry, read out by the instruction execution unit of the processor, it can be written by the data field and the instruction execution unit that holds a writable data Memory section having a pointer attribute field for holding a pointer attribute , a write detection circuit for detecting that the instruction execution unit has written to the memory section, and the entry to which writing has been performed when writing has been detected. said prefetch reading means for reading the data field of the data pointer attributes of the pointer attribute field, a <br/> data when the pointer attribute is set to the read out by the reading means to the data cache memory Address Register apparatus characterized by having means for issuing a fetch request.