JPH07141174A - Register - Google Patents

Abstract

PURPOSE:To provide a register making it unnecessary to execute useless prefetching due to a change in a register storing data other than addresses. CONSTITUTION:The register includes a memory part 9 having plural entries, a data field 10 for storing data to be read out/written from/in respective entries by a processor instruction execution unit 2 and a pointer attribute field 11 for storing pointer attributes to be written by the unit 2, a control circuit 12 for detecting the writing of data from the unit 2 to the memory part 9, reading means 104, 105 for reading out the data of the field 10 for a written entry and the pointer attribute of the field 11 at the time of detecting the writing, and a means 13 for outputting a prefetch request 107 for using the read data as a prefetch address to a data cache memory 3 when the pointer attribute is set up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to register devices in microprocessors and microcontrollers.

[0002]

2. Description of the Related Art A conventional register device is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-90038. FIG. 3 is a block diagram of a system using this conventional register device, and FIG. 4 is a program showing an operation example of this conventional example. 1 is a register device, 2 is an instruction execution unit, 3 is a data cache memory, 4 is a main memory device, 9 is a memory unit of the register device 1 for storing data in each entry, and 15 is a register including a write detection circuit. Reference numeral 100 is a control circuit of the device 1, 100 and 101 are access request signals and read / write signals for accessing the register device 1 from the instruction execution unit 2, and 103 is an address bus for selecting an entry of the memory unit 9. , 105 are data buses for reading and writing to the memory section 9, and 107 is a prefetch request signal. Also,
Reference numeral 110 is a data transfer means between the instruction execution unit 2 and the data cache memory 3, and 120 is a data transfer means between the data cache memory 3 and the main storage device 4. The operation of the conventional register device configured as described above will be described in the order of programs shown in FIG. 4 with reference to FIG. The register device 1 in this conventional example has four registers, which will be referred to as registers r0, r1, r2, and r3, respectively.

(1) set r0, ADDR This is an instruction to set the address ADDR in the register r0. AD
DR is an address at which data obtained later in the register r2 is stored. By this instruction, the instruction execution unit 2 asserts the access request signal 100, enables the read / write signal 101, and enables the address bus 10.
3 outputs the address of register r0 to data bus 105
The value of address ADDR is output to. Since the access request signal 100 is asserted and the read / write signal 101 is write enabled, the control circuit 15 enables the read / write signal 200, and the memory unit 9 is the entry selected by the address bus 103. The value of the data bus 105 is written in. Further, the control circuit 15 sets the read / write signal 200 to read enable and asserts the prefetch request signal 107. Since the read / write signal 200 is asserted, the memory unit 9 outputs the data of the entry selected by the address bus 103 to the data bus 105. The data cache memory 3 has a data bus (prefetch address bus) when the prefetch request signal 107 is asserted.
Prefetch is performed with 105 as an address. In the prefetch, the requested address is the data cache memory 3
If not present, it is read from the main memory 4 and stored in the data cache memory 3. As a result, data having the address ADDR as an address can be prefetched into the data cache memory 3. Further, the prefetch is automatically performed in the same manner even when the value of the register r0 is changed next time. After that, while the data cache memory 3 is prefetching, the instruction execution unit 2 can execute other instructions, so that some instructions until the prefetch is completed do not access the memory or change the pointer. Is executed.

(2) load r2, [r0] This is an instruction to store data having the value of the register r0 as an address in the register r2. Since the data having the value of the register r0 as the address is stored in the data cache memory 3 by the prefetch of (1), the reading to the data cache memory 3 will be a hit, and the main memory 4 will not be accessed. Can be read.

(3) set r1, DATA This is an instruction to set the data DATA in the register r1. This instruction also sets the value in register r1 in the same way as instruction (1),
Prefetch data with data DATA as an address.

[0006]

However, in the above structure, when the value of the register is changed, the changed value is always prefetched regardless of the address and data. For example, data DA in command (3) in FIG.
TA is not an address but prefetch is being executed. Such prefetch execution is a wasteful process,
The time required to execute such prefetch is a factor that reduces performance. Further, since the data that should not be used is stored in the data cache memory, the usable data is replaced from the data cache memory, and the hit rate of the data cache memory decreases.
Furthermore, when the value of the data DATA is an inappropriate value for the address, it may be possible to cause exception processing that does not occur, such as a memory access violation.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a register device which does not perform useless prefetching due to a change in a register that holds non-address data.

[0008]

According to the present invention, there are provided a plurality of entries in a register of a processor, each entry having a field for holding writable data read by an instruction execution unit of the processor and the instruction. A memory unit having a field holding a pointer attribute writable by the execution unit, a write detection circuit for detecting that the instruction execution unit has written to the memory unit, and a write operation when writing is detected. And means for reading the data in the data field of the entry and the pointer attribute in the pointer attribute field, and issuing a prefetch request to the data cache memory when the pointer attribute is set, using the read data as the prefetch address. Have means It is a register system.

[0009]

With the above structure, the registers to be prefetched by updating can be limited to those having the pointer attribute, so that unnecessary prefetching due to the change of the register holding the data which is not the address is not performed. Therefore, it is possible to prevent performance deterioration due to useless prefetching, and it is possible to avoid a decrease in hit rate because unused data is stored in the data cache memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A register device according to an embodiment of the present invention,
A description will be given with reference to the drawings. FIG. 1 is a block diagram of a system using a register device in one embodiment of the present invention, and FIG. 2 is a program showing an operation example of this embodiment.

In FIG. 1, 1 is a register device, 2 is an instruction execution unit, 3 is a data cache memory, and 4 is a main memory device. Further, 9 is a memory unit of the register device 1,
Reference numerals 10 and 11 respectively denote a data field of the memory unit 9, a pointer attribute field, 12 a control circuit of the register device 1 including a write detection circuit, 13 a pointer attribute signal 104 of 1 and a prefetch enable signal 106.
Prefetch request signal 10 when is asserted
This is a prefetch request signal generation circuit that asserts 7 and deasserts the others. Reference numerals 100 and 101 are access request signals and read / write signals for accessing the register device 1 from the instruction execution unit 2, 102 is a pointer attribute control signal for setting / resetting pointer attributes, and 103 is an entry of the memory unit 9. Is an address bus for selecting a pointer attribute field for reading and writing a pointer attribute field, 105 is a data bus for reading and writing a data field 10, and 106 is a register from an instruction execution unit. A prefetch enable signal for generating a prefetch by writing to the device 1, 107 is a prefetch request signal from the register device 1 to the data cache memory 3, and 200 is a read or write control for the data field 10. Read / write signal, 201 indicates pointer attribute field 1
This is a read / write signal for controlling the read or write for 1. Reference numeral 110 denotes a data transfer unit between the instruction execution unit 2 and the data cache memory 3, and 12
Reference numeral 0 is a data transfer means between the data cache memory 3 and the main storage device 4.

The operation of the register device configured as described above will be described in the order of programs shown in FIG. 2 with reference to FIG.
The register device 1 in this embodiment has four entries and corresponds to four registers. The four registers are referred to as registers r0, r1, r2, r3, respectively.

(1) pointer r0 This is an instruction to set the pointer attribute of the register r0. This instruction causes the instruction execution unit 2 to access the access request signal 1
00 and the pointer attribute control signal 102 are asserted, the address of the register r0 is output to the address bus 103, and 1 is output to the pointer attribute signal 104. The control circuit 12 enables the read / write signal 201 because the access request signal 100 and the pointer attribute control signal 102 are asserted. By the read / write signal 201, the memory unit 9 writes the value of the pointer attribute signal 104 to the entry selected by the address bus 103 of the pointer attribute field 11. As a result, the instruction execution unit 2 sets 1 to the pointer attribute bit of the register r0.
Write.

(2) data r1 This is an instruction to reset the pointer attribute of the register r1.
By this instruction, the instruction execution unit 2 asserts the access request signal 100 and the pointer attribute control signal 102, outputs the address of the register r1 to the address bus 103, and outputs 0 to the pointer attribute signal 104. The control circuit 12 uses the access request signal 100 and the pointer attribute control signal 102.
Is asserted, the read / write signal 201
Write enable. Read / write signal 201
Thus, the memory unit 9 writes the value of the pointer attribute signal 104 to the entry selected by the address bus 103 of the pointer attribute field 11. As a result, the instruction execution unit 2 writes 0 in the pointer attribute bit of the register r1.

(3) set r0, ADDR This is an instruction to set the address ADDR in the register r0. The address ADDR is the address where the data obtained later in the register r2 is stored. This instruction causes the instruction execution unit 2 to assert the access request signal 100, enable the read / write signal 101, output the address of the register r0 to the address bus 103, and output the value of the address ADDR to the data bus 105. Control circuit 12
Since the access request signal 100 is asserted and the read / write signal 101 is write enable, the read / write signal 200 is write enabled. The memory unit 9 writes the value of the data bus 105 to the entry selected by the address bus 103 of the data field 10 by the read / write signal 200.

Further, the control circuit 12 sets the read / write signals 200 and 201 to read enable and asserts the prefetch enable signal 106. In response to the read / write signals 200 and 201, the memory section 9 causes the data field 10 and the data of the entry selected by the address bus 103 of the pointer attribute field 11 to the data bus 105 and the pointer attribute to the pointer attribute signal 10
Output to 4. The pointer attribute signal 104 and the prefetch enable signal 106 are input to the prefetch request signal generation circuit 13, and the prefetch request signal 107 is asserted because the pointer attribute signal 103 is 1 and the prefetch enable signal 106 is asserted. When the prefetch request signal 107 is asserted, the data cache memory 3 performs prefetch with the data bus (prefetch address bus) 105 as an address. In the prefetch, when the requested address is not in the data cache memory 3, the data is read from the main memory 4 and stored in the data cache memory 3. As a result, data having the address ADDR as an address can be prefetched into the data cache memory 3. Similarly, the next time the value of register r0 is changed, prefetching is automatically performed in the same manner until the pointer attribute is reset. After this instruction, while the data cache memory 3 is performing the prefetch, the instruction execution unit 2 can execute another instruction, so that several instructions until the prefetch is completed perform memory access and change of the pointer. Assume that you are executing an instruction that does not exist.

(4) load r2, [r0] This is an instruction to store data having the value of the register r0 as an address in the register r2. The instruction execution unit 2 asserts the access request signal 100, and the read / write signal 101
Is read-enabled, and the address of the register r0 is output to the address bus 103. The control circuit 12 enables the read / write signal 200, and the memory unit 9 outputs the data of the entry selected by the address bus 103 of the data field 10 to the data bus 105. The instruction execution unit 2 reads the data of the data bus 105 as an address from the data cache memory 3. In this case, since the prefetch is performed by the instruction (3), the data cache memory 3 is hit and the data can be immediately read. Next, the instruction execution unit 2 asserts the access request signal 100, enables the read / write signal 101 for writing, outputs the address of the register r2 to the address bus 103, and outputs the data bus 1
The data read from the data cache memory 3 is output to 05. The control circuit 12 uses the access request signal 1
00 is asserted and read / write signal 101
Is write-enabled, the read / write signal 200 is write-enabled. The memory unit 9 writes the data of the data bus 105 to the entry selected by the address bus 103 of the data field 10.
By doing so, the data cache memory 3 does not miss the data whose address is the register r0,
It can be stored in register r2. Where load r2,
Even in the case of an effective address such as [r0 + 4], if it is within one line of the data cache memory 3, the data cache memory 3 also hits.

(5) set r1, DATA This is an instruction to set the data DATA in the register r1. This instruction causes the instruction execution unit 2 to access the access request signal 10
0 is asserted, the read / write signal 101 is write-enabled, the address of the register r1 is output to the address bus 103, and the value of the data DATA is output to the data bus 105. The control circuit 12 enables the read / write signal 200 because the access request signal 100 is asserted and the read / write signal 101 is write enabled. In response to the read / write signal 200, the memory unit 9 sets the data bus 10 to the entry selected by the address bus 103 of the data field 10.
Write the value of 5. Further, the control circuit 12 sets the read / write signals 200 and 201 to read enable and asserts the prefetch enable signal 106. The memory unit 9 outputs the data of the entry selected by the address bus 103 of the data field 10 and the pointer attribute field 11 to the data bus 105 and the pointer attribute to the pointer attribute signal 104. Pointer attribute signal 1
03 and the prefetch enable signal 106 are input to the prefetch request signal generation circuit 13, and since the pointer attribute signal 103 is 0 and the prefetch enable signal 106 is asserted, the prefetch request signal 107 is deasserted. The data cache memory 3 does not execute prefetch because the prefetch request signal 107 is deasserted.

As described above, the pointer attribute of each register can be set by an instruction, and prefetching is performed only when the register for which the pointer attribute is set is updated.

In this embodiment, the load instruction is shown as an example, but the same applies to the store instruction.

[0021]

As described above, according to the present invention, the pointer attribute of each register can be set by an instruction, and the prefetch is performed only when the register having the pointer attribute is updated. Therefore, as compared with the case where prefetching is performed for all register updates as in the case of the conventional register device, unnecessary prefetch execution time is unnecessary, so prefetching can be performed effectively and performance can be improved. .

Further, it is possible to prevent the hit rate from being lowered by storing the unused data in the data cache memory due to the useless prefetch in the conventional register device, which is a great effect.

[Brief description of drawings]

FIG. 1 is a system block diagram using a register device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a program showing an operation example in the embodiment of the present invention.

FIG. 3 is a system block diagram using a register device in a conventional example of the present invention.

FIG. 4 is an explanatory diagram showing a program showing an operation example in a conventional example of the present invention.

[Explanation of symbols]

 1 Register Device 2 Instruction Execution Unit 3 Data Cache Memory 4 Main Memory 9 Memory Unit of Register Device 10 Data Field of Memory Unit 9 Pointer Attribute Field of Memory Unit 9 Control Circuit Including Write Detection Circuit 13 Prefetch Request Signal Generation Circuit 100 Access request signal 101 Read / write signal 102 Pointer attribute control signal 103 Address bus 104 Pointer attribute signal 105 Data bus

Claims (1)

[Claims] 1. A processor register has a plurality of entries, each entry having a field for holding data writable and writable by an instruction execution unit of the processor and a pointer writable by the instruction execution unit. A memory section having a field for holding an attribute; a write detection circuit for detecting that there is a write from the instruction execution unit to the memory section; and the data field of the entry having a write when the write is detected. And a means for reading the pointer attribute of the pointer attribute field, and a means for issuing a prefetch request to the data cache memory when the pointer attribute is set, using the read data as a prefetch address. To Register apparatus.