JPH0784886A - Method and unit for cache memory control - Google Patents

Abstract

PURPOSE:To provide the cache memory control method and cache memory control unit which can shorten the process time of even an information processor, using a device which is rewritten only in block units of constant size like a flash memory and long in rewriting time, as a storage device. CONSTITUTION:An address comparison part 4 when reading data out of a cache memory 3 to the flash memory 2 confirms the addresses of all the data on the cache memory 3 and counts the data in address ranges at certain intervals to select the address range containing the largest number of data as an object to be written out. A replacement execution part 5 writes all the data in the address range, selected by the address comparison part 4, out of the cache memory 3 to the flash memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method and a control device for a storage device and a cache memory in an information processing device.

[0002]

2. Description of the Related Art Generally, when configuring an information processing apparatus, a small-capacity cache memory that can be accessed at high speed is provided between a processing apparatus and a storage apparatus, and frequently used data is transferred from the storage apparatus to the cache memory. A method of copying and using by the processing device is often used.

This cache memory has no data at the start of the system, and the accessed data is copied every time the processing device accesses the storage device, that is, reads or writes the data. When the processing device uses the data already copied to the cache memory, the storage device is not accessed, and only the high-speed cache memory is accessed.

However, since the cache memory has a small amount of data capacity as compared with the storage device, eventually all the data is copied to the area of the cache memory, and in order to copy new data to the cache memory, the cache memory has already been cached. It is necessary to write the data in the memory to the storage device, create an empty area, and copy new data to the empty area.

Therefore, conventionally, even when data is written from the processor, if there is corresponding data in the cache memory, only the data in the cache memory is changed, the data in the storage device is not changed, and the cache memory is full. Then, when it became necessary to copy new data to the cache memory, the copy back method of replacing the data, that is, writing the data to the storage device, was adopted for the first time.

In addition to the copy-back method, there is a write-through method in which not only the data in the cache memory but also the data in the storage device is changed when writing data from the processing device. It is commonly used because it can reduce access to devices and improve system performance. In the case of the copy-back method, it is necessary to decide which data in the cache memory should be written to the storage device when the cache memory is full. LRU (Least Recently Used) to select
Method, random method to select arbitrarily, FIFO (First In Last Ou) to select the data copied most in the past
t) method.

[0007]

However, in the above-mentioned conventional copy-back method, there is no problem if the memory device is composed of a device such as SRAM or DRAM that can read and write in individual data units. Like NOR-type flash memory, reading is possible in individual data units, but data rewriting can be performed in a storage device when it is configured by a device that can only be in units called blocks in which a fixed number of data are collected. There is a problem that performance is deteriorated due to the processing.

That is, in the case of the NOR type flash memory, although reading of data can be executed in byte units at a speed similar to that of a normal DRAM or the like, in order to change the already written data, the data is once erased. Then you need to write. Since this data erasing can be executed only in units of several kbytes to tens of kbytes called a block, it is necessary to actually read the data in block units once, erase the blocks, and write the data again in block units. Becomes Further, since erasing and writing of data takes much time as compared with a normal DRAM or the like, the processing time becomes long when data is rewritten frequently.

As described above, the conventional cache memory control system does not consider rewriting in block units. Therefore, when a flash memory is used as the storage device, the number of times of rewriting of the storage device increases. ,
There is a problem that the processing time increases. The present invention has been made in view of such circumstances, and even in an information processing apparatus that uses a device having a long rewriting time as a storage device, such as a flash memory, in which rewriting can be executed only in units of blocks of a certain size, An object of the present invention is to provide a cache memory control method and a cache memory control that can reduce the processing time.

[0010]

According to a first aspect of the present invention, when a processing device accesses data in a storage device, a copy existence confirmation step of determining whether or not the corresponding data has been copied to a cache memory, If the existence of the copy is confirmed in the copy existence confirmation step, the cache memory access step in which only the data in the cache memory is accessed, and if the copy existence is not confirmed in the copy existence confirmation step, the corresponding data is stored in the cache memory. An empty area existence confirmation step for confirming whether or not there is an empty area to be copied, and a first copy for copying the corresponding data from the storage device to the cache memory if the existence of the empty area is confirmed in the empty area existence confirmation step. The existence of an empty area must be confirmed in the step and the empty area existence confirmation step. For example, a step of creating an empty area by writing the data in the cache memory to the storage device to create an empty area, and a second copying step of copying the corresponding data from the storage device to the empty area created in the step of creating the empty area. In the cache memory control method of the copy-back method to be executed, when writing data from the cache memory to the storage device, the address confirmation step for confirming the addresses of all the data in the cache memory, and the address confirmed in the address confirmation step Based on this, the write target selection step that selects the write target address range that has the largest number of data items in the fixed address range, and the cache memory that stores all the data that is included in the write target selection step From storage to storage It is characterized by performing a and writing steps out come.

According to a second aspect of the present invention, a cache memory is provided between the processing device and the storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, If only the data in the cache memory is accessed and it is not copied, it is confirmed whether there is an empty area in the cache memory to copy the corresponding data. If there is an empty area, the corresponding data is transferred from the storage device to the cache memory. If there is no free area, write the data in the cache memory to the storage device to create an empty area, and copy the relevant data from the storage device to the empty area. When writing data to the storage device, check the addresses of all data in the cache memory A selection unit that counts the number of data included in the remote address range and selects the address range having the largest number of data as a write target, and all data included in the address range selected by the selection unit from the cache memory to a storage device. It is characterized by having a writing section for writing to.

According to a third aspect of the present invention, when the processing device accesses the data in the storage device, a copy existence confirmation step of determining whether or not the corresponding data is copied to the cache memory, and a copy existence confirmation step are performed. If the existence of the copy is confirmed, the cache memory access step for accessing only the data in the cache memory, and if the copy existence confirmation step does not confirm the existence of the copy, there is an empty area for copying the corresponding data in the cache memory. Whether there is an empty area in the empty area existence confirmation step, and if there is an empty area existence in the empty area existence confirmation step, a first copy step of copying the corresponding data from the storage device to the cache memory, and an empty area existence If empty space is not confirmed in the confirmation step, cache Copy for executing an empty area creating step for writing the data on the memory to the storage device to create an empty area, and a second copying step for copying the corresponding data from the storage apparatus to the empty area created in the empty area creating step In the cache memory control method of the back method, when writing data from the cache memory to the storage device, a constant is determined based on the address confirmation step of sequentially confirming the address of the data in the cache memory and the address confirmed in the address confirmation step. The address range in which the number of data included in the address range of the interval exceeds a specific number is selected as the write target, and all the data included in the address range selected in the write target selection step is written from the cache memory. Write to storage Is characterized by performing the out come step.

According to a fourth aspect of the present invention, a cache memory is provided between the processing device and the storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, If only the data in the cache memory is accessed and it is not copied, it is confirmed whether there is an empty area in the cache memory to copy the corresponding data. If there is an empty area, the corresponding data is transferred from the storage device to the cache memory. If there is no free area, write the data in the cache memory to the storage device to create an empty area, and copy the relevant data from the storage device to the empty area. When writing data to the storage device, check the address of the data in the cache memory in order and A selection unit that selects an address range in which the number of data included in the address range exceeds a specific number as a writing target, and writing all data included in the address range selected by the selection unit from the cache memory to the storage device It is characterized by having a section and.

According to a fifth aspect of the present invention, when the processing device accesses the data in the storage device, a copy existence confirmation step of determining whether or not the corresponding data has been copied to the cache memory and a copy existence confirmation step are performed. If the existence of the copy is confirmed, the cache memory access step for accessing only the data in the cache memory, and if the copy existence confirmation step does not confirm the existence of the copy, there is an empty area for copying the corresponding data in the cache memory. Whether there is an empty area in the empty area existence confirmation step, and if there is an empty area existence in the empty area existence confirmation step, a first copy step of copying the corresponding data from the storage device to the cache memory, and an empty area existence If empty space is not confirmed in the confirmation step, cache Copy for executing an empty area creating step for writing the data on the memory to the storage device to create an empty area, and a second copying step for copying the corresponding data from the storage apparatus to the empty area created in the empty area creating step In the back-type cache memory control method, the data area of the cache memory is divided into groups by a specific number, a selection confirmation flag is set for each group, and the cache memory is copied when the corresponding data is copied from the storage device to the cache memory. If the existence of the data is confirmed in the data existence confirmation step and the data existence confirmation step that determines whether the data included in the same address range as the above data already exists, copy the corresponding data in the same group. In the third copy step and the data existence confirmation step If the existence of the data is not confirmed, the fourth copy step of copying the corresponding data to a new group where no data has been copied, and if the data included in the same address range is copied to one of the groups When the selection confirmation flag ON step that turns on the selection confirmation flag of the corresponding group is executed and the data is written from the cache memory to the storage device, one of the groups for which the selection flag is on is selected as the write target It is characterized in that the selecting step and the writing step of writing all the data included in the address range of the data in the group selected in the writing target selecting step from the cache memory to the storage device are executed.

According to a sixth aspect of the present invention, a cache memory is provided between the processing device and the storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, If only the data in the cache memory is accessed and it is not copied, it is confirmed whether there is an empty area in the cache memory to copy the corresponding data. If there is an empty area, the corresponding data is transferred from the storage device to the cache memory. If there is no empty area, the data in the cache memory is written to the storage device to create an empty area, and the corresponding data is copied from the storage device to the empty area. The data area is divided into groups by a specific number, a selection confirmation flag is set for each group, and When copying the relevant data to Luo cache memory, copies the corresponding data into the same group if the data is already included in the same address range as the corresponding data in the cache memory, there if the data is 1
Data is copied from the cache memory to the storage device by copying the relevant data to a new group that has not been copied at all, and turning on the selection confirmation flag of the relevant group when all the data included in the same address range is copied to that group. When writing out, the selection unit that selects one of the groups whose selection flag is on as the writing target, and all the data included in the address range of the data in the group selected by the selection unit from the cache memory It is characterized by having a writing section for writing to.

[0016]

According to the first aspect of the present invention, when writing data from the cache memory to the storage device, the address confirmation step confirms the addresses of all the data in the cache memory, and the write target selection step performs the address confirmation step. Based on the addresses confirmed in, select the address range with the largest number of data included in the address range of the constant interval as the write target, and in the write step, select all the addresses included in the address range selected in the write target selection step. Data is written from the cache memory to the storage device.

In the invention of claim 2, when the data is written from the cache memory to the storage device, the selection unit confirms the addresses of all the data in the cache memory,
The number of data included in the address range at regular intervals is counted, and the address range having the largest number of data is selected as the writing target. The writing unit writes all data included in the address range selected by the selecting unit from the cache memory to the storage device.

According to the third aspect of the present invention, when writing data from the cache memory to the storage device, the address confirmation step sequentially confirms the address of the data on the cache memory, and the write target selection step includes the address confirmation step. Based on the confirmed address,
Select an address range in which the number of data included in the address range at regular intervals exceeds a specific number as the write target, and in the write step, write all the data included in the address range selected in the write target selection step from the cache memory. Write to storage.

In the invention of claim 4, when the data is written from the cache memory to the storage device, the selection unit sequentially checks the addresses of the data on the cache memory, and determines the number of data included in the address range at a constant interval. Select an address range that exceeds a specified number for writing. The writing unit writes all data included in the address range selected by the selecting unit from the cache memory to the storage device.

According to the invention of claim 5, the data area of the cache memory is divided into groups by a specific number,
When setting the selection confirmation flag for each group and copying the corresponding data from the storage device to the cache memory, in the data existence confirmation step, whether data included in the same address range as the corresponding data already exists in the cache memory. If the existence of data is confirmed in the data existence confirmation step in the third copy step,
If the existence of data is not confirmed in the data existence confirmation step in the fourth copy step, the corresponding data is copied into the same group, and the corresponding data is copied to a new group in which no data is copied, and the selection confirmation When data included in the same address range is copied to any of the groups in the flag on step, the selection confirmation flag of the corresponding group is turned on, and when writing the data from the cache memory to the storage device, in the write target selection step, Select one of the groups whose selection flag is on as the write target, and in the write step, write all the data included in the address range of the data in the group selected in the write target selection step from the cache memory to the storage device. .

In the invention of claim 6, when the data registration unit copies the relevant data from the storage device to the cache memory, if there is already data included in the same address range as the relevant data in the cache memory, the data registration unit To the new group where no data has been copied, and if all the data in the same address range is copied to that group, the selection confirmation flag of the corresponding group is turned on. . When writing the data from the cache memory to the storage device, the selection unit selects any of the groups for which the selection flag is on as the writing target. The writing unit writes all the data included in the address range of the data in the group selected by the selecting unit from the cache memory to the storage device.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of an information processing system including a cache memory control device according to a first embodiment of the present invention. This information processing system includes a CPU 1, a flash memory 2, a cache memory 3 and an address. Comparison unit 4
And a replacement execution unit 5 and a save memory 6. The CPU 1 performs various kinds of arithmetic processing. The flash memory 2 has a capacity of 1 Mbyte, and erasable blocks are in units of 1 kbyte. The cache memory 3 has a capacity of 100 entries and stores 1-byte data and an address of the data in the flash memory for each entry. The address comparison unit 4 looks at the address of each entry of the cache memory 3, counts the number of data included in the block unit of the flash memory 2, and checks the block having the largest number. The replacement execution unit 5 executes replacement of the cache memory 3 and the flash memory 2. The save memory 6 saves the data in the block when the replace executing unit 5 erases the block of the flash memory 2. That is, the CPU 1 constitutes a processing device, the flash memory 2 constitutes a storage device, the address comparison unit 4 constitutes a selection unit, and the replacement execution unit 5 and the save memory 6 constitute a writing unit. is doing.

Next, the operation will be described. When accessing the flash memory 2, the CPU 1 first determines whether or not the cache memory 3 has the data.
The address of each entry is compared and judged, and if there is, the cache memory 3 is accessed. And CPU1
If there is no corresponding data in the cache memory 3, until all entries in the cache memory 3 are full,
In the case of read access, the relevant data is fetched from the flash memory 2, copied to the cache memory 3 and then read, and in the case of write access, the cache memory 3
Write the relevant data to. The above operation is similar to that of the conventional cache memory control device.

Next, when the CPU 1 accesses data that is not in the cache memory 3 when all the entries in the cache memory 3 are full, the data in the cache memory 3 is written to the flash memory 2 and the entry is emptied. Then, it is necessary to register the access data in the empty entry. The operation in this case will be described with reference to the flowchart of FIG. First, the address comparison unit 4 reads the addresses of 100 entries in the cache memory 3, counts the number in 1 kbyte block units, and notifies the replacement execution unit 5 of the block having the largest number (step S1). As a result, the replacement execution unit 5 reads the 1 kbyte data of the corresponding block from the flash memory 2 to the save memory 6 (step S
2) Erase all data in the corresponding block of the flash memory 2 (step S3). Then, all the data in the cache memory 3 included in the corresponding block are written to the corresponding position in the save memory 6 (step S
4). Finally, the data in the save memory 6 is written in the original block of the flash memory 2 (step S5).

As described above, since the block having the largest number of data on the cache memory 3 is to be replaced, the number of times of rewriting of the flash memory 2 can be reduced and the empty entries of the cache memory 3 can be efficiently increased. it can. (Embodiment 2) The cache memory control device in Embodiment 2 has the same configuration as that of FIG. 1, but only the operation of the address comparison unit 4 at the time of replacement is different. That is, as shown in FIG.
When the replacement becomes necessary, the address comparison unit 4
The address of the first entry of the cache memory 3 is read (step S11). Then, it is sequentially compared with the 2nd to 100th entries (step S12), and it is determined whether or not there are a preset number of entries, for example, 5 or more, included in the same block as the address of the first entry ( Step S13) If there are five or more blocks, the replacement execution unit 5 is notified of the block (step S14). If not, n = n + 1 is set (step S15), and the process returns to step S11. That is, the address of the second entry is read and compared with the third to 100th entries in order,
If there are five entries included in the same block as the address of the second entry, the replacement execution unit 5 is notified of the block. The same process is repeated for the third entry and thereafter, and the block to be replaced is determined. Although not shown in FIG. 3, if five or more data are not included in the same block, the replacement target is appropriately determined using, for example, a random method.

As described above, since the entries in the cache memory 3 are sequentially confirmed, the address comparison unit 4 only needs to internally store the address of one entry in the cache memory 3, which reduces the amount of hardware. be able to. In addition, since the data accessed by the CPU 1 is often concentrated in a specific address range, finding a block occupying a certain number or more in the cache memory 3 in this manner normally determines the block having the largest number of data. Equal to discovering. (Third Embodiment) FIG. 4 is a block diagram of an information processing system including a cache memory control device according to a third embodiment of the present invention. This information processing system includes a CPU 11, a flash memory 12, a cache memory 13, and a replacement. Execution unit 14, save memory 15, and data registration unit 16
And a flag confirmation unit 17. CPU11
Performs various arithmetic processes. The flash memory 12 has a capacity of 1 Mbyte, and erasable blocks are in units of 1 kbyte. The cache memory 13 has a capacity of 100 entries, and stores 1-byte data and the address of the data in the flash memory 12 for each entry. The cache memory 13 is divided into groups of 5 entries, and each group is provided with a 1-bit check flag. An initial value of this check flag is set to 0 at the system start. The replacement execution unit 14
The replacement of the cache memory 3 and the flash memory 2 is executed. The save memory 15 is the replacement execution unit 1
4 erases a block of the flash memory 12,
Save the data in the block. The data registration unit 16
Data is copied to the cache memory 3 and a check flag is set. The flag checking unit 17 checks the check flag of the cache memory 3 and determines the block to be replaced. The CPU 11 constitutes a processing device, the flash memory 12 constitutes a storage device, the replacement execution unit 14 and the save memory 15 constitute a writing unit, and the flag confirmation unit 17 constitutes a selection unit. is doing.

Next, the operation will be described. When accessing the flash memory 12, the CPU 11 first determines whether or not the data exists in the cache memory 13 by comparing the address of each entry of the cache memory 13, and accesses the cache memory 13 if any. The above operation is similar to that of the conventional cache memory control device.
If there is no corresponding data in the cache memory 13, until all entries in the cache memory 13 are full,
In the case of read access, the CPU 11 takes out the relevant data from the flash memory 12, copies it to the cache memory 13 and then reads it, and in the case of write access, writes the relevant data in the cache memory 13.
At this time, the data registration unit 16 checks the address of the entry in the cache memory 13 to which the data has already been copied, and if there is data included in the same block as the relevant data and the group to which the data belongs is empty. If the entry remains, the corresponding data is copied to the empty entry. Then, when the five entries of the group are full, the addresses of the five data of the group are checked, and if they are all included in the same block, the check flag of the group is set to 1. When all the entries in the cache memory 13 are checked, if there is no data included in the same block, or if there is data in the same group but there is no empty entry in that group, no data is registered yet. Copy the relevant data to an empty group that has not been created. If there is no empty group, copy the corresponding data to an appropriate empty entry.

Next, when all the entries in the cache memory 13 are full and the CPU 11 accesses data that is not in the cache memory 13, the data in the cache memory 13 is written to the flash memory 12 and the entries are emptied. Then, it is necessary to register the access data in the empty entry. Regarding the operation in this case,
This will be described with reference to the flowchart of FIG. First,
The flag checking unit 17 sequentially checks the 20 check flags of the cache memory 13 and determines whether or not there is a group in which the check flag is set to 1 (step S21). The included block is notified to the replacement executing unit 14 (step S
22). If all the check flags are 0, a block to be replaced is appropriately determined by using, for example, a random method (step S23). As a result, the replacement execution unit 14 saves 1 kbyte of data of the corresponding block from the flash memory 12 to the save memory 15
To the flash memory 12 (step S24).
The corresponding block of is erased (step S25). Then, the cache memory 1 included in the corresponding block
All the data on 3 are written to the corresponding positions in the save memory 15 (step S26). Finally, the data in the save memory 15 is written in the original block of the flash memory 12 (step S27).

As described above, when copying data to the cache memory 13, data included in the same block should be registered in one group as much as possible, and a check flag provided in the cache memory 13 for each predetermined number. As a result, it is possible to determine that there is a certain number or more of data included in the same block, so that the process of determining the block to be replaced at the time of executing replacement can be speeded up.

[0030]

As described above, according to the present invention, a cache memory is provided between a processing device and a storage device, and when the processing device accesses data in the storage device, the corresponding data is stored in the cache memory. If it is copied, only the data in the cache memory is accessed.If it is not copied, it is confirmed whether there is an empty area in the cache memory to copy the corresponding data. Copy-back cache memory control that copies from the storage device to the cache memory, writes the data in the cache memory to the storage device if there is no free space, creates a free space, and copies the relevant data from the storage device to the free space When writing data from the cache memory to the storage device in the device, all the data in the cache memory is added. Check the data, count the number of data items in the address range at regular intervals, and select the address range with the largest number of data items for writing, and all the data items included in the address range selected by the selection unit. And a writing unit that writes the data from the cache memory to the storage device. Therefore, the address of the data in the cache memory is confirmed, the number of data contained in the block unit of the storage device is checked, and the data to be replaced is selected. Therefore, rewriting can be executed only in units of blocks of a certain size, such as flash memory, and even in an information processing device that uses a device with a long rewriting time as a storage device, the block unit of the storage device can be changed by replacing the cache memory. The number of rewrites can be reduced, and the processing time can be shortened.

Further, when writing data from the cache memory to the storage device, the addresses of the data in the cache memory are checked in order, and the address range in which the number of data included in the address range at a constant interval exceeds a specific number is written. If a selection unit to be selected as a target and a writing unit that writes all the data included in the address range selected by the selection unit from the cache memory to the storage device are provided, in addition to the above effect, the entry of the cache memory Since the confirmation is performed in order, only the address of one entry in the cache memory needs to be stored in the confirmation processing, and the amount of hardware can be reduced.

Further, the data area of the cache memory is divided into groups by a specific number, a selection confirmation flag is set for each group, and when the relevant data is copied from the storage device to the cache memory, the relevant data is stored in the cache memory. If there is already data included in the same address range as above, copy the corresponding data in the same group, if not, copy the corresponding data to a new group in which no data is copied, and all the groups include in the same address range. Data registration unit that turns on the selection confirmation flag of the corresponding group when the data to be copied is copied, and a selection unit that selects one of the groups whose selection flag is on when writing the data from the cache memory to the storage device as the write target. And the data in the group selected by the selection part All data included in the scan range of the cache memory and a writing unit that writes to a storage device,
In addition to the above effect, when data is copied to the cache memory, data included in the same block is registered in one group as much as possible, and the data is provided for each predetermined number in the cache memory. Since it is possible to determine that the data included in the same block is a certain number or more by the check flag, it is possible to speed up the process of determining the block to be replaced when the replacement is executed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing system including a cache memory control device according to a first embodiment and a second embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of the cache memory control device according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of the cache memory control device according to the second embodiment of the present invention.

FIG. 4 is a configuration diagram of an information processing system including a cache memory control device according to a third embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the cache memory control device according to the third embodiment of the present invention.

[Explanation of symbols]

 1 CPU 2 flash memory 3 cache memory 4 address comparison unit 5 replacement execution unit 6 save memory 11 CPU 12 flash memory 13 cache memory 14 replacement execution unit 15 save memory 16 data registration unit 17 flag confirmation unit

Claims (6)

[Claims] 1. A copy existence confirmation step of determining whether or not the data is copied to a cache memory when the processing device accesses data in the storage device, and existence of a copy is confirmed in the copy existence confirmation step. If so, a cache memory access step for accessing only the data on the cache memory, and if there is no copy existence confirmed in the copy existence confirmation step, is there an empty area for copying the corresponding data on the cache memory? An empty area existence confirming step of confirming whether there is any, and a first copy step of copying the corresponding data from the storage device to the cache memory if existence of an empty area is confirmed in the empty area existence confirming step, In the empty area existence confirmation step, the existence of empty area is not confirmed. In this case, an empty area creating step of writing data in the cache memory to the storage device to create an empty area, and a second step of copying the corresponding data from the storage device to the empty area created in the empty area creating step In a cache memory control method of a copy back method that executes a copying step, an address checking step of checking addresses of all data on the cache memory when writing data from the cache memory to the storage device, Based on the addresses confirmed in the address confirmation step, the write target selection step of selecting the address range having the largest number of data included in the address range of the constant interval as the write target, and the address selected in the write target selection step All in range Cache memory control method characterized by the data execution and a writing step of writing to the storage device from the cache memory. 2. A cache memory is provided between a processing device and a storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, the cache memory. If only the data in the memory is accessed and if it is not copied, it is confirmed whether or not there is an empty area in the cache memory for copying the corresponding data. If there is an empty area, the corresponding data is cached from the storage device. Copy-back type cache memory control device for copying to memory, writing data in the cache memory to the storage device to create an empty region if there is no empty region, and copying the corresponding data to the empty region from the storage device In writing the data from the cache memory to the storage device, Check the address of all the data, count the number of data included in the address range at regular intervals, and select the address range with the largest number of data as the write target, and the address range selected by the selecting unit. A cache memory control device, comprising: a writing unit that writes all included data from the cache memory to the storage device. 3. A copy existence confirming step of judging whether or not the corresponding data is copied to the cache memory when the processing device accesses the data of the storage device, and the existence of the copy is confirmed in the copy existence confirming step. If so, a cache memory access step for accessing only the data on the cache memory, and if there is no copy existence confirmed in the copy existence confirmation step, is there an empty area for copying the corresponding data on the cache memory? An empty area existence confirming step of confirming whether there is any, and a first copy step of copying the corresponding data from the storage device to the cache memory if existence of an empty area is confirmed in the empty area existence confirming step, In the empty area existence confirmation step, the existence of empty area is not confirmed. In this case, an empty area creating step of writing data in the cache memory to the storage device to create an empty area, and a second step of copying the corresponding data from the storage device to the empty area created in the empty area creating step A copy-back type cache memory control method that executes a copy step, and an address check step that sequentially checks the address of the data in the cache memory when writing data from the cache memory to the storage device; Based on the addresses confirmed in the confirming step, a write target selecting step of selecting a write target as an address range in which the number of data included in the address range of a certain interval exceeds a specific number, and the write target selecting step is selected in the write target selecting step. Included in the address range Cache memory control method characterized by all data executes a writing step of writing to the storage device from the cache memory. 4. A cache memory is provided between a processing device and a storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, the cache memory. If only the data in the memory is accessed and if it is not copied, it is confirmed whether or not there is an empty area in the cache memory for copying the corresponding data. If there is an empty area, the corresponding data is cached from the storage device. Copy-back type cache memory control device for copying to memory, writing data in the cache memory to the storage device to create an empty region if there is no empty region, and copying the corresponding data to the empty region from the storage device In writing the data from the cache memory to the storage device, The address of the data is sequentially checked, and a selection unit that selects an address range in which the number of data included in the address range at a constant interval exceeds a specific number as a writing target, and an address range selected by the selection unit A cache memory control device comprising: a writing unit that writes all data from the cache memory to the storage device. 5. A copy existence confirmation step of determining whether or not the data is copied to a cache memory when the processing device accesses the data of the storage device, and the existence of the copy is confirmed in the copy existence confirmation step. If so, a cache memory access step for accessing only the data on the cache memory, and if there is no copy existence confirmed in the copy existence confirmation step, is there an empty area for copying the corresponding data on the cache memory? An empty area existence confirming step of confirming whether there is any, and a first copy step of copying the corresponding data from the storage device to the cache memory if existence of an empty area is confirmed in the empty area existence confirming step, In the empty area existence confirmation step, the existence of empty area is not confirmed. In this case, an empty area creating step of writing data in the cache memory to the storage device to create an empty area, and a second step of copying the corresponding data from the storage device to the empty area created in the empty area creating step A copy-back type cache memory control method for executing the copying step, wherein a data area of the cache memory is divided into groups by a specific number, a selection confirmation flag is set for each group, and the cache memory from the storage device is set. When the corresponding data is copied to, the data existence confirmation step of determining whether or not the data included in the same address range as the corresponding data already exists in the cache memory, and the existence of the data in the data existence confirmation step If confirmed, copy the corresponding data in the same group A third copying step, and a fourth copying step, in which if the existence of the data is not confirmed in the data existence confirming step, the corresponding data is copied to a new group in which no data is copied, When all the data included in the same address range is copied, the selection confirmation flag ON step of turning on the selection confirmation flag of the corresponding group is executed, and when the data is written from the cache memory to the storage device, the selection is performed. A write target selection step of selecting one of the groups whose flags are on as a write target; and storing all data included in the address range of the data in the group selected in the write target selection step from the cache memory Export step to export to the device And a cache memory control method characterized by executing the following. 6. A cache memory is provided between a processing device and a storage device, and when the processing device accesses data in the storage device, if the corresponding data is copied to the cache memory, the cache memory is provided. If only the data in the memory is accessed and if it is not copied, it is confirmed whether or not there is an empty area in the cache memory for copying the corresponding data. If there is an empty area, the corresponding data is cached from the storage device. Copy-back type cache memory control device for copying to memory, writing data in the cache memory to the storage device to create an empty region if there is no empty region, and copying the corresponding data to the empty region from the storage device In, the data area of the cache memory is divided into groups by a specific number and selected for each group. When a corresponding flag is set and the corresponding data is copied from the storage device to the cache memory, if the data included in the same address range as the corresponding data already exists in the cache memory, the corresponding data is copied into the same group. If there is none, copy the corresponding data to a new group in which no data is copied, and if the data included in the same address range is copied to the group, a data registration unit that turns on the selection confirmation flag of the corresponding group, When writing data from the cache memory to the storage device, a selection unit that selects one of the groups in which the selection flag is turned on for writing, and an address range of data in the group selected by the selection unit All the data contained in the cache memory is stored in the storage device. A cache memory control device comprising: a writing unit for writing data to a storage device.