JP2924708B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache memory for holding a copy of the contents of a main memory.

[0002]

2. Description of the Related Art The performance of a processor has been remarkably improved by the improvement of semiconductor technology and architectural measures. However, the access time of a main storage device for storing data has not been able to keep up with the performance of the processor. Costs are increasing relatively. High-performance processors reduce the memory access cost and address this problem by providing a high-speed cache memory by utilizing the temporal locality and spatial locality of memory access. However, since there is almost no locality of memory access in large-scale scientific and technical calculations, cache memory does not work effectively, and it is difficult to process these calculations at high speed with a general-purpose processor due to delay due to memory access. There was a problem.

In order to process such large-scale scientific and technological calculations at high speed, a conventional supercomputer increases the bandwidth to main memory or prepares a large-capacity vector register for calculation data. It is a well-known technology to configure a system that does not rely on cache memory (for example, Journal of Information Processing Society of Japan Vol. 34, NO. 3, pp. 361-
371, 1993). FIG. 6 shows a configuration example of such a computer.
In FIG. 6, a vector register 905 includes a register storage device 908, a read pointer 909 for designating a position where reading and writing are performed, and a read selector 9
11, a write pointer 910, a write selector 912, an adder 913, and the like. Data in a discontinuous arrangement on the main storage device 901 is continuously loaded from the load pipeline 902, and the operation pipeline 9
In step 04, calculations can be performed continuously. In addition,
903 is a store pipeline, 906 is a register write bus, and 907 is a register read bus. Such a system configuration has a problem that the cost is high and the application is limited.

There have also been proposed some techniques for adding the above-described vector register and a dedicated register instead of the above-described vector register to a general-purpose microprocessor, and applying the above-described vector register to scientific and technological calculations as described above. For example, a paper published by Nakamura et al. In 1993 (Hiroshi Nakamura, Hiromitsu Domori, Kisaburo Nakazawa, "Evaluation of pseudo vector processor using register window method", IPSJ Journal Vol. 34, No. 4, pp. 669-680, 1993) addresses the latency problem of the main storage device by extending the register for storing the floating point used for scientific and technical calculations in a window system and prefetching the value into this register. FIG. 7 shows the configuration of the floating-point register according to this method. In this method, the local register 1006, the overlap register 1007, the global register 100
8 is prepared by hardware, and the currently valid register is switched by switching windows. As a result, data can be loaded and stored into registers other than the register used for the operation at the same time as the operation, and the efficiency of the operation is improved. In addition, in FIG.
Reference numeral 005 denotes a physical register, which corresponds to windows 0 to 3, respectively.

[0005]

However, in the above-mentioned processing method, dedicated registers specializing in numerical calculations are prepared, so that it is costly to prepare registers necessary and sufficient for large-scale calculations. In addition, these resources cannot be used for purposes other than those in which registers can be used effectively. Therefore,
It is difficult to adopt it for a general-purpose processor that is required to improve the price-performance ratio. For this reason, a general-purpose processor having a normal cache memory must be used.However, when a calculation using discontinuous data is executed by a conventional general-purpose processor, The hit ratio decreases, and the access delay of the main storage device cannot be concealed. Therefore, in a general-purpose processor having an arithmetic pipeline, the supply of desired data cannot keep up, and a large number of pipeline stalls occur. In the cache memory, data is cached in a unit called a line of a predetermined size (for example, 4 words). Therefore, even when one piece of data is read, a plurality of adjacent data unnecessary for calculation is also cached. This causes a problem of performance degradation.

Accordingly, the present invention is to solve the above-mentioned problem by increasing the cache hit rate by effectively utilizing a cache memory widely used in general-purpose processors for data arranged discontinuously. It is.

[0007]

In order to solve the above-mentioned problems, an information processing apparatus according to the present invention has a higher speed than a main storage device.
A storage device for data relocation for storing the relocated data, and a series of data discontinuously present on the main storage device as a series of data continuous on the data relocation storage device. What is a processor core to be relocated?
A cache memory that holds a copy of the contents of the data relocation storage device and the contents of the main storage device, and a series of data that is discontinuously present on the main storage device. Is configured to access the data after the relocation.

In another embodiment, a data relocation area on a main storage device is used in place of the data relocation storage device to store the relocated data, and the address translation device uses a main storage device. A series of data that is discontinuously present on the device is rearranged as a series of continuous data on the data relocation area, and the cache memory holds a copy of the contents of the main storage device. An application program that uses a discontinuous set of data is configured to access the rearranged data.

When the address of a series of data discontinuously existing in the main storage device has a certain regularity, the address translating device relocates the data to be relocated according to the relocation information indicating the regularity. When the address of a series of data discontinuously present on the main storage device is indicated by a pointer stored in another location on the main storage device, the read address indicating the storage address of the pointer is read again. The reading of the pointer and the reading of the data to be relocated are performed according to the location information.

[0010]

According to the present invention, a series of data discontinuously present on a main storage device used by an application program is transferred from an address translation device to a data relocation storage device separate from the main storage device or to a main storage device. The data is rearranged as a series of data having continuous addresses on a data rearrangement area provided on the storage device, and the cache memory sets the data after the rearrangement as a cache target.

[0011]

FIG. 2 is a conceptual diagram of memory access in an information processing apparatus according to one embodiment of the present invention. In the present embodiment, the discontinuous arrangement data 206 existing in the virtual address space 201 accessed by the software operating on the processor core 101 can be accessed as the continuous data 205 on the data rearrangement virtual address space 202. Rearrange. For this purpose, a data rearrangement memory space 203 is prepared on the physical address space, and discontinuous data 208 (corresponding to the discontinuous layout data 206) on the physical address space 204 using the address translator 107.
Is stored in the data relocation memory space 203.
7 (corresponding to the continuous data 205).

The data thus rearranged is mapped to another virtual address space. Therefore, the application code for accessing discontinuous data is rewritten to access continuous data in another address space. This rewriting is performed by a user or a compiler.

FIG. 1 is a block diagram of a main part of an embodiment of an information processing apparatus of the present invention having a data rearrangement function as described in FIG. In FIG. 1, a processor core 101
Is a core part of a normal processor composed of an operation pipeline and a register set. Processor core 10
1 is connected to the cache memory interface 103 by a processor data bus 151 for reading and writing necessary data. The cache memory interface 103 is connected to the cache memory 104 by the cache data bus 153 and the cache address bus 167, and
2 and the main storage device physical address bus 166, and the main storage device interface 105 is connected to the main storage device 106 by the main storage device internal data bus 154 and the main storage device internal address bus 168. . Also, in order to convert a virtual address into a physical address, a TLB (Translation Lookasid) is used.
e Buffer) 102 and processor core 1
01 is connected to the processor virtual address bus 165 and the TLB control line 181, and is connected to the cache memory interface 103 via the address bus 175. The part so far is no different from a normal processor.

In this embodiment, further, for data relocation, the address translator 107, the data relocation storage device 109, and the data relocation storage device interface 1
08 is provided.

The address translator 107 is connected to the cache memory interface 103 via a signal line 183, a physical address bus 173 for accessing an address translation main storage device, and a read data bus 157 for an address translation device. The TLB 102 is connected by a main storage device access physical address bus 173, an address translation device read data bus 158, and an address translation device write data bus 159.
, An address conversion virtual address bus 171, 172 and a signal line 186, and further, a data relocation storage device interface 108, an address conversion relocation storage device access physical address bus 174, and an address conversion device write data bus 160 and the address conversion device read data bus 162. The data relocation storage device interface 108 is also connected to the cache memory interface 103 by a data relocation storage device data bus 155 and a data relocation physical address bus 169, and furthermore, the data relocation storage device internal data bus 156. Also, it is connected to the data relocation storage device 109 via the data relocation internal address bus 170.

The address translator 107 is a special register 131 for specifying relocation from software, a relocation address generator 132 for generating a physical address after relocation, and a relocation source physical address. A physical address generating device 133, a sequencer 134 for controlling the entire system, and a conversion information table device 135 for storing conversion information. In addition, a read buffer 136, a shifter 137, and a multiplexer 138 are provided for actually relocating data. , Write buffer 139, write bus 140
And a read bus 141.

The special register 131 is a processor core 1
01, the special register access control line 182, the conversion information table device 135 and the conversion information table input / output bus 184, the sequencer 134 and the signal line 191, the physical address generation device 133 and the signal line 193, respectively. The sequencer 134 is connected to the special register 131, connected to the TLB 102 by a signal line 186, and
32, physical address generator 133, read buffer 1
36, a shifter 137, a multiplexer 138, and a write buffer 139, which are connected to the sequencer control line 185 for control. The relocation address generation device 132 receives control from the sequencer 134 through the control line 185 and
A relocation address is generated from the value transmitted through the TLB 102 and the physical address supplied from the TLB 102, and a physical address bus 174 for accessing a storage device for address translation and relocation.
Storage interface 108 for data relocation through
To communicate. The physical address generation device 133 controls the control line 1
85 receives control from the sequencer 134 and sends the TLB 10 through the physical address bus 172 for address conversion.
2 and a value supplied from the special register 131 via the signal line 193, and generates a physical address for address conversion to the cache memory interface 103 and the main memory interface 105 via the physical address bus for address conversion 173. introduce.

The write bus 140 is connected to the main memory interface 105 by the write data bus 159 for the address translator and to the storage interface 108 for data relocation by the write data bus 160 for the address translator. Data bus 161
Is connected to the write buffer 139. The read bus 141 is a read data bus 157 for the address translator.
To the main memory interface 105 via the address translation device read data bus 158, to the data relocation storage device interface 108 via the address translation device read data bus 162, and to the read buffer 136 via the output bus 195. , The output bus 196 and the multiplexer 13
8 respectively.

Further, the output of the read buffer 136 is connected to the input of the shifter 137, and the output of the shifter 137 is connected to the input of the multiplexer 138 together with the output of the read bus 141 and the output of the write buffer 139. The output of the multiplexer 138 is connected to the input of the write buffer 139, and the output of the write buffer 139 is connected to the write bus 140 by the write data bus 161 for the address translation device, and is fed back to the input of the multiplexer 138.

Hereinafter, the operation of the embodiment constructed as described above will be described step by step.

Data relocation according to the present invention is realized by cooperation between hardware and software. First, it is necessary to set data relocation information. Since the data relocation information is determined according to the order of data reference by software, the setting is performed by software. As a method of instructing by software, a method of expanding an instruction set and a method of setting a value in a special register are conceivable. In the present embodiment, a method of setting by a special register 131 is adopted. The special register 131 is shown in FIG.
The relocation information such as data unit (byte, word, long word, etc.) data start virtual address data arrangement rule data number relocation virtual address The special register 131 is set through the special register access control line 182 in accordance with an instruction from software operating on the processor core 101. The relocation information set in the special register 131 is also transmitted to the conversion information table device 135 via the conversion information table input / output bus 184, and is stored until a later-described write back.

For example, data starting from a virtual address 0x1000, 0x1010, 0x1020, 0x
When rearranging a total of 100 pieces of data such as 1030,... After readout from a virtual address 0x20000, the following is required: data unit word data start virtual address 0x1000 data layout rule + 0x10 data number 100 Relocation information such as a relocation virtual address 0x40000 is set in the special register 131.

The special register 131 is controlled by software.
When the necessary relocation information is set, the sequencer 134
Is activated, and the relocation process is executed under the control.
First, the sequencer 134 sends the start virtual address of the data set in the special register 131 to the TLB 102 via the address bus 171 to convert it into a physical address.
The physical address obtained by the conversion in the TLB 102 is transmitted to the physical address generator 133 via the bus 172. The physical address generation device 133 includes a sequencer 134
First, the physical address transmitted from the TLB 102 is selected, and the selected physical address is transmitted to the main memory interface 105 via the physical address bus 173 as it is. Since the latest data of the address may exist in the cache memory 104, the same address is sent to the cache memory interface 103. Thereafter, the physical address generation device 133 sequentially generates the second and subsequent physical addresses from the generated physical address and the data arrangement rule set in the special register 131, and sequentially outputs the physical addresses to the physical address bus 173. The operation is performed by the special register 131
Is continued until the generation of the physical addresses for the number of data set in the step (c) is completed. That is, in the above example, the virtual address 0x
Assuming that 1000 is mapped to a physical address 0x2000, the TLB 102 converts 0x1000 to an address 0x2000.
For 33, a total of 10 for each address from 0x2000 to 0x10
Generate and output zero addresses.

The physical address generator 133 sends the bus 17
When the cache memory interface 103 receives the supply of the physical address via the data bus 157, the cache memory interface 103 transfers the line including the data to the read bus 141 via the data bus 157 when the corresponding data exists in the cache memory 104.
Send to Further, the main storage interface 105 transmits a line including the relevant data read from the main storage 106 to the read bus 141 via the data bus 158.

The read bus 141 sends the data sent from the cache memory interface 103 to the read buffer 136 when the data is sent from the cache memory interface 103, and sends the data sent from the main memory interface 105 to the read buffer 136 when the data is not sent from the cache memory interface 103. Write. This read buffer 136
Is logically shifted as necessary by the shifter 137 at the next stage and supplied to the multiplexer 138. The multiplexer 138 selects the data supplied from the shifter 137 and the data stored in the write buffer 139 on a byte-by-byte basis and newly writes the data to the write buffer 139, so that the data to be relocated is written on the write buffer 139. Sort as continuous data. The data in the write buffer 139 is transferred to the data bus 161, the write bus 140 and the data bus 1
60 for data relocation storage device interface 1
08, the data relocation storage device interface 108 writes the above data to the data relocation storage device 109 indicated by the physical address that is simultaneously supplied from the relocation address generation device 132 through the physical address bus 174.

The details of the operation of these functions will be described below using specific examples. The data bus is 8 bytes wide, and the address 0x40000 of the data relocation virtual memory space is set to the address 0x0 of the data relocation storage device 109 by the TLB102.
And the other settings are the same as in the above-described example.

In this case, the main storage device interface 10
5 or the data at the address 0x2007-0x2000 is transmitted first in units of 8 bytes from the cache memory interface 103 and stored in the read buffer 136 having a capacity of 8 bytes. 0x2003 in this data
The portion at address 0x2000 is the storage device 10 for data relocation.
9 is to be stored in the address 0x3-0x0. In this case, there is no need to shift the data. Therefore, the data is stored in the write buffer 139 through the multiplexer 138 without being shifted by the shifter 137. Next, 0x2017-
The data at the address 0x2010 is sent and stored in the read buffer 136. 0x2013 in this data
The portion at −0x2010 is the data relocation storage device 1
Since the data is to be stored in addresses 0x7-0x4 of 09, the shifter 137 shifts left by 4 bytes, and the multiplexer 139 selects the contents of the write buffer 139 for the lower 4 bytes and the contents of the shifter 137 for the upper 4 bytes. Then, the data is stored in the write buffer 139. As a result, the physical address 0x2 is sequentially stored in the write buffer 139.
013, 0x2012, 0x2011, 0x2010,
0x2003, 0x2002, 0x2001, 0x20
The data at address 00 is stored.

This data is stored in the data relocation storage device 10.
Since the data is to be stored starting from the address 9x0, the relocation address generator 132 generates the address 0x0. This is because the sequencer 134 sets the relocation virtual address 0x40000 set in the special register 131 to the TLB10
2, the physical address 0x0 is converted to a physical address 0x0 and transmitted to the relocation address generator 132 via the bus 172, and the relocation address generator 132 outputs the transmitted physical address 0x0 as it is. It should be noted that the relocation address generation device 132 outputs the first physical address 0x
After generating 0, the physical address 0x8, 0x16,... Is obtained from the generated physical address and the increment value (0x8) input from the sequencer 134 via the signal line 194.
Thus, an address is generated for each address 0x8.

The physical address 0x0 generated by the relocation address generating device 132 is sent to the data relocation storage device interface 108 through the physical address bus 174, and at the same time, the above data stored in the write buffer 139 is transferred to the write data bus. 161, light bus 14
The data is transmitted to the data relocation storage device interface 108 via the 0 and write data bus 160, and the data relocation storage device interface 108 stores the data from the address 0x0 of the data relocation storage device 109. As described above, the data relocation storage device 1 for the first two words of data (total 8 bytes) of the data to be relocated.
This means that the relocation to 09 has been completed. The address translator 107 repeats the above operation to execute the relocation for all the relocation target data set in the special register 131. When the relocation is completed, the sequencer 134 sends the processor core 101 and the cache memory interface 1 to the TLB 102.
03, the conversion request corresponding to the data relocation virtual address space 202 is instructed to be validated.

Next, an operation at the time of memory access by software operating on the processor core 101 will be described.

The application program operating on the processor core 101 accesses the data relocated as described above to the relocated virtual address, and executes predetermined processing such as calculation. . For this reason, for example, in the application program, The code part that refers to the data at the address before relocation like It has been rewritten as Although an example of rewriting at the C language level has been described here, it is generally desirable that the relocation and the setting of the preceding relocation information to the special register be automatically performed by a compiler in combination.

When the processor core 101 executing the application code accesses the relocation virtual address, for example, address 0x40000, the corresponding data is initially stored in the cache memory 104.
Therefore, the cache memory interface 103 reads the line containing the relevant data from the data relocation storage device 109 through the data relocation storage device interface 108, and
4 and the corresponding data in the line is returned to the processor core 101. This is performed as follows.

First, the access address 0x40000 is transmitted to the TLB 102 via the address bus 175,
The data is converted into an address for accessing the data relocation memory space 203 by the LB 102. Next, the cache memory interface 103 transmits the line address including the converted address to the data relocation storage device interface 108 via the address bus 169. The data relocation storage device interface 108
The line of the transmitted line address is read from the data rearrangement storage device 109 and returned to the cache memory interface 103. The cache memory interface 103 stores the returned line in the cache memory 104, and returns the corresponding data in the line to the processor core 101. Thus, after the rearrangement, the rearranged data can be handled in the same manner as the normal data. If the processor core 101 accesses the data relocation virtual address space 202 before the relocation is completed, the TLB 102 does not yet validate the conversion request from the processor core 101 for the data relocation virtual address space. The processing of the processor core 101 waits until the rearrangement is completed.

The cache memory 104 is cached in units of lines, and only data accessed by application codes is packed in continuous addresses in the data rearrangement storage device 109. All data cached from the data relocation storage device 109 to the cache memory 104 at the time of a mishit is data to be accessed by the application code. As a result, the cache miss rate decreases.

As described above, according to this embodiment,
The processor core 101 can handle data at a continuous address in the cache memory 104. As a result, there is no need to load unnecessary data into the cache memory. Avoid waste of the cache memory, and reduce the possibility that required data is replaced from the cache memory. Thus, the cache memory 104 can be used efficiently. By performing the relocation processing sufficiently before actually using the data, the processor core 101 can perform other calculation processing during the data relocation time, and more efficient execution can be performed. It becomes possible.

Next, a description will be given of the operation of rewriting the relocated data to the normal space when the use of the relocated data is completed.

When the use of the relocated data is completed, the application program operating on the processor core 101 sets that fact in the special register 131 and writes the data back to the normal space to the address translator 107. Instruct. In the address translation device 107, first, the sequencer 134 moves the relocation information relating to the relocation data instructed to be written back from the translation information table device 135 to the special register 131, and sends the processor core 101 and the cache memory interface to the TLB 102. An instruction is issued to invalidate the conversion request corresponding to the data relocation virtual address space 202 from the virtual machine 103.

Next, the sequencer 134 generates an address of the relocation data in the data relocation storage device 109 by the relocation address generation device 132 to sequentially read the relocation data, 133
Are sequentially written to the addresses on the main storage device 106 generated in step (1). Here, as described above, the main storage device 1
06 is read / write only in a specific byte unit, the data at the write destination is once read, and the relocation data portion in the read data is replaced with the relocation data read from the data relocation storage device 109. Write back to the address. In the case of the above example, the following operation is specifically performed.

The sequencer 134 has a special register 131
The relocation virtual address 0x40000 set in TL
In B102, the physical address is converted to the physical address 0x0 and given to the relocation address generation device 132,
32 first transmits the physical address 0x0 to the data relocation storage device interface 108 through the physical address bus 174, and the data relocation storage device interface 108 transfers the data address from the data relocation storage device 109 to the data relocation memory space. 203 address 0x7-0x0
The data at the address is read and stored in the read buffer 136 via the read data bus 162, the read bus 141, and the output bus 195. At the same time, the sequencer 134
The start virtual address 0x1000 set in the special register 131 is given to the TLB 102 to be converted into a physical address (for example, 0x2000), and the address bus 1
72 to the physical address generator 133,
Initially, the physical address generation device 133
The address x2000 is generated and transmitted to the cache memory interface 103 and the main memory interface 105 via the address bus 173 to request a read. The read physical address 0x2007-0x
The data at the address 2000 is transmitted from the cache memory interface 103 or the main memory interface 105 to the read bus 141, and the read bus 141 outputs this to the multiplexer 138 via the output bus 196.

0x3-0x0 of data relocation memory space
The data of the address is a physical address 0x2003-0x200
In this case, the shifter 137 outputs the data of 0x2007-0x2000 stored in the read buffer 136 to the multiplexer 138 without performing the shift operation. Data (0x2007)
The lower 4 bytes select data (data at addresses 0x3-0x0) from the shifter 137 and store them in the write buffer 139. The data stored in the write buffer 139 is
The data is sent to the main storage device interface 105 through 40, and is written into an 8-byte area starting from the address 0x2000 generated by the physical address generation device 133 at that time. Thus, the write-back of the relocation data of 0x3-0x0 has been completed.

Next, the sequencer 134 generates the next address 0x2010 from the physical address generator 133, loads the data at the address 0x2017-0x2010 from the main memory 106 or the cache memory 104 onto the read bus 141, and Take as input. Data at addresses 0x7-0x4 remaining in the upper 4 bytes of the read buffer 136 is a physical address 0x201.
To write back to address 3-0x2010, shifter 1
37 shifts 4 bytes to the right in this case, the multiplexer 138 shifts the upper 4 bytes of the data (data at addresses 0x2017-0x2014) from the read bus 141,
The lower 4 bytes are data (0x7-
0x4) is selected and the write buffer 139 is selected.
To be stored. The data stored in the write buffer 139 is sent to the main memory interface 105 via the write bus 140,
3 is written in an 8-byte area starting at address 0x2010. This means that the rewriting of the relocation data of 0x7-0x4 has been completed.

By repeating the above operation, all the rearranged data is written back to the main storage device 106.

FIG. 3 is a block diagram of a main part of an information processing apparatus according to another embodiment of the present invention, and FIG. 4 is a conceptual diagram of memory access in the embodiment. In the embodiment described with reference to FIGS. 1 and 2, the data relocation storage device 109 is provided as a dedicated storage device for the data relocation memory space, and the data relocation storage device interface 108 is provided as an interface therefor. . Since the data relocation storage device 109 requires less storage capacity than the main storage device 106, a high-speed storage device can be used.
Since the data to be used is explicitly rearranged prior to its use, the effect is considered to be sufficient. However, in a general-purpose system, it is necessary to reduce the number of devices as much as possible to reduce the cost. Therefore, in the embodiment shown in FIGS. 3 and 4, the storage device dedicated to data relocation is omitted, and software for performing memory management is extended, so that relocation data can be allocated on the main storage device. . Less than,
This embodiment will be described.

As shown in FIG. 3, in this embodiment, the data relocation storage device 109 and the data relocation storage interface 108 are removed from the embodiment of FIG.
The internal structure of the address translator 107 is changed so that the relocation address generator 132 and the physical address generator 133
Are selected by the selector 301 and supplied to the main memory interface 105 and the cache memory interface 103 via the address bus 302.

To relocate data, the application program issues a system call to the OS or the like, and as shown in FIG.
The data relocation virtual address space 402 is secured above.
At this time, a data relocation physical address space 403 corresponding to the data relocation virtual address space 402 is allocated in the physical address space 404. After that, the application program sets the same reallocation information in the special register 131 as in the embodiment of FIG. The address relocation processing is the same as that of the embodiment of FIG.
The selector 301 selects the address generated by the relocation address generation device 132 when the desired data is stored in the storage device and sends it to the main storage device interface 105. As a result, data can be relocated to the data relocation physical address space 403 of the main storage device 106.

When rewriting the relocation data, the processing proceeds in substantially the same manner as in the embodiment of FIG. However, since the relocation data exists in the main storage device 106, when the relocation data is loaded into the read buffer 136, the selector 30
1 differs in that the address generated by the relocation address generator 132 is transmitted to the main storage interface 105, and the main storage interface 105 sends relocation data to the read buffer 136.

FIG. 5 is a block diagram of a main part of an information processing apparatus according to still another embodiment of the present invention. In the embodiment described with reference to FIG. 1 and FIG. 3, the order of referring to the data in the discontinuous arrangement is given to the address translator by a mathematical expression, and the data is rearranged into the continuous data. However, reference to discontinuous data is not a regularity that can be represented by a mathematical expression, and a case where it is indicated by a pointer as shown below frequently appears in scientific and technical calculations.

In the case of such processing, the rule of data reference cannot be given to the address translation device by a mathematical expression. Therefore, in the embodiment shown in FIG. 5, in order to cope with such a case, by specifying a pointer in which a variable indicating data storage information is stored, the address translation device automatically reads out the pointer and reads the pointer. The data is relocated. This makes it possible to refer to discontinuous data by the index of a variable in the framework of the same relocation mechanism.

The embodiment of FIG. 5 is different from the embodiment of FIG.
An address queue 501 is newly provided in the address translator 107. The address queue 501 is a FIFO that stores the contents of the pointer variables stored in the main storage device 106.
This is an O (First In First Out) type queue. Further, the selector 301 transfers the contents of the address queue 501 to the TLB 102 through the virtual address bus 171 for address conversion.
Has been expanded so that an address converted to a physical address by the user can be selected. Hereinafter, the operation of this embodiment will be described with reference to FIGS. 5 and 4 focusing on the differences from the embodiment of FIG.

The application program operating on the processor core 101 secures the data relocation virtual address space 402 in the virtual memory space 401 and then sets the following relocation information in the special register 131, for example. Reference type Pointer Data unit Word Pointer start virtual address 0x1000 Pointer arrangement rule + 0x10 Number of pointers 100 Relocation virtual address 0x40000

In the case of such relocation information, 0x100
It is necessary to load the data at the address indicated by the address stored at address 0 as the first data. Therefore, the sequencer 134 converts the pointer start virtual address 0x1000 set in the special register 131 into a physical address by the TLB 102, and generates this physical address from the physical address generator 133 first. At this time, the selector 301 selects this address, and the cache memory interface 103 and the main memory interface 10
Send to 5. The data of the corresponding address (the pointer of the virtual address expression) thus read out is read from the read bus 14.
1 in the address queue 501. The pointer stored in the address queue 501 is converted into a physical address by the TLB 102, and the selector 301 selects this address and
3 and the main storage interface 105. The data obtained as a result is data to be rearranged and stored in the read buffer 136, and the same rearrangement and address conversion rearrangement as in the embodiment of FIG. 3 are performed.

Similarly, when the rearranged data is written back to the main storage device 106, the data is transferred via the address queue 501.
Load data pointer, load necessary data,
After rearrangement, it will be rewritten. If the pointer has been rewritten after the rearrangement and before the rewriting, the data is rewritten to the location indicated by the new pointer variable. Therefore, the address translation device 107 can be used for copying the data.

[0053]

As described above, according to the present invention, a series of data discontinuously existing in the main storage device is rearranged as data of a continuous address in another memory area, and the data after the rearrangement is read. Is set as a target of caching and a target of access of an application program, the locality of memory access during execution of the application program is increased, the cache hit rate is improved by that amount, and the execution processing speed of the application program is improved. In the present invention, the data rearrangement process is an overhead, but once rearranged, subsequent rearrangement is unnecessary, so that a series of discontinuous data on the main storage device is accessed many times. In such a case, it does not matter much.

According to the configuration using the data relocation area on the main storage device, the amount of hardware can be reduced and the cost can be reduced as compared with the case where the dedicated data relocation storage device is used. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of memory access in the information processing apparatus of the embodiment in FIG.

FIG. 3 is a main part block diagram of an information processing apparatus according to another embodiment of the present invention;

FIG. 4 is a conceptual diagram of a memory access in the information processing apparatus of the embodiment in FIG. 3;

FIG. 5 is a main block diagram of an information processing apparatus according to yet another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional vector computer.

FIG. 7 is a conceptual diagram of a register window.

[Explanation of symbols]

101: Processor Core 102: TLB (Translation Lookaside Buffer) 103: Cache Memory Interface 104: Cache Memory 105: Main Storage Interface 106: Main Storage 107: Address Transformer 108: Storage Interface for Data Relocation 109: Data Relocation Arrangement storage device 131 Special register 132 Relocation address generation device 133 Physical address generation device 134 Sequencer 135 Conversion information table device 136 Read buffer 137 Shifter 138 Multiplexer 139 Write buffer 140 Write bus 141 Read bus 151 Processor data bus 152 Main storage device data bus 153 Cache data bus 154 Main storage device internal data bus 155 Data storage for data relocation Device data bus 156 ... Data storage internal data bus for data relocation 157 ... Read data bus for address converter 158 ... Read data bus for address converter 159 ... Write data bus for address converter 160 ... Write data bus for address converter 161, a write data bus for an address conversion device 162, a read data bus for an address conversion device 165, a processor virtual address bus 166, a main storage device physical address bus 167, a cache address bus 168, a main storage device internal address bus 169, a data relocation Physical address bus 170 for data relocation internal address bus 171 virtual address bus for address conversion 172 physical address bus for address conversion 173 physical address bus for address conversion main storage device access 17 ... Physical address bus for accessing the storage device for address conversion and relocation 175... Address bus 181... TLB control line 182... Special register access control line 183. 185: sequencer control line 186: signal line for transmitting address translation device to TLB information 201: virtual address space 202: data relocation virtual address space 203: data relocation memory space 204: physical address space 205: on virtual address space Relocation data 206: discontinuous location data on virtual address space 207: relocation data on data relocation memory space 208: discontinuous data on physical address space 301: selector 302: physical address for address conversion main storage device access Bus 401 ... virtual address space 402 ... data relocation virtual address space 403 ... data relocation physical address space 404 ... physical address space 405 ... relocation data on the virtual address space 406 ... discontinuous data on the virtual address space 407 ... data relocation Relocated data on the physical address space 408: discontinuous data on the physical address space 501: address queue

Claims (5)

(57) [Claims] A storage device which is faster than a main storage device.
Repositioning as a series of continuous data and the data rearrangement storage device for storing the rearranged data, a series of data present discontinuously on the main memory to the data rearrangement memory on Te , Provided separately from the processor core
Applications that use the address translation device, and a cache memory which holds a copy of the contents of the contents and the main memory of the data rearrangement memory device, a series of data present discontinuously on the main storage device The information processing apparatus, wherein the program is configured to access the data after the rearrangement. 2. The method according to claim 1, wherein when the addresses of a series of data discontinuously present on the main storage device have a certain regularity, the address translation device should relocate according to the relocation information indicating the regularity. 2. The information processing apparatus according to claim 1, wherein data is read. 3. When the address of a series of data discontinuously present on the main storage device is indicated by a pointer stored in another location on the main storage device, relocation indicating the storage address of the pointer is performed. 2. The information processing apparatus according to claim 1, wherein the address translator reads data to be rearranged according to the pointer according to the information. 4. A cache memory for holding a copy of the contents of a main storage device, and a cache memory for storing rearranged data.
Includes a data rearrangement area on the main memory, and a series of address translator to relocate as continuous data a series of data in the data rearrangement over region present discontinuously on the main memory, the main One that exists discontinuously on the storage device
When the address of a series of data has a certain regularity
The address according to the relocation information indicating its regularity.
The converter reads the data to be relocated,
One application program that uses a series of data present discontinuously on the main storage device, an information processing apparatus characterized by being configured to access the data after the relocation. 5. A cache memory for holding a copy of the contents of a main memory, and a cache memory for storing rearranged data.
Includes a data rearrangement area on the main memory, and a series of address translator to relocate as continuous data a series of data in the data rearrangement over region present discontinuously on the main memory, the main One that exists discontinuously on the storage device
The address of the data set is stored in another location on the main storage device.
If indicated by the stored pointer, the pointer's case
The address conversion according to the relocation information indicating the delivery address
Read data to be relocated by device according to pointer
And, an application program that uses a series of data discontinuously present on the main storage device,
An information processing apparatus configured to access the data after the rearrangement.