JPH08286928A - Information processor - Google Patents

Abstract

PURPOSE: To improve a hit rate of cache by effectively utilizing a cache memory for discontinuously arranged data. CONSTITUTION: An address translating device 107 rearranges series of data, which discontinuously exist on a main storage device, on a storage device 109 for data rearrangement as series of data having continuous addresses. A cache memory 104 holds the copy of contents of these storage device 109 for data rearrangement and main storage device 106 and is controlled by a cache memory interface 103. Besides, an application program to use series of data discontinuously existent on the main storage device is reloaded to access the rearranged data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache memory for holding a copy of the contents of main memory.

[0002]

2. Description of the Related Art The performance of a processor has been remarkably improved due to improvements in semiconductor technology and architectural innovations, but the access time of a main storage device for storing data has not kept pace with the improvement in the performance of the processor. The cost is increasing relatively. In a high-performance processor, the memory access cost is reduced and a problem is addressed by providing a high-speed cache memory by utilizing the temporal locality and spatial locality of memory access. However, since there is almost no locality of memory access in large-scale scientific and technological calculations, the cache memory does not work effectively, and it is difficult for a general-purpose processor to process these calculations at high speed due to the delay due to memory access. There was a problem.

In order to process such a large-scale scientific and technological calculation at high speed, the conventional supercomputer increases the bandwidth to the main memory and prepares a large-capacity vector register for the calculation data. It is a well-known technique to construct a system that does not rely on cache memory (for example, Journal of Information Processing Society of Japan, Vol.34, NO.3, pp.361-).
371, 1993). An example of the configuration of such a computer is shown in FIG.
In FIG. 6, the vector register 905 includes a register storage device 908, a read pointer 909 for designating a position for reading and writing, and a read selector 9.
11, a write pointer 910, a write selector 912, an adder 913, etc., and continuously loads the discontinuously arranged data on the main storage device 901 from the load pipeline 902, and the arithmetic pipeline 9
In 04, the calculation can be continuously performed. In addition,
Reference numeral 903 is a store pipeline, 906 is a register writing bus, and 907 is a register reading bus. Such a system configuration has a problem of high cost and limited applications.

Further, some techniques have been proposed in which a vector register as described above or a dedicated register instead of the above is added to a general-purpose microprocessor so as to be applied to the scientific and technological calculation as described above. For example, Nakamura et al. Published a paper in 1993 (Hiroshi Nakamura, Hiromitsu Imori, Kisaburo Nakazawa, “Evaluation of Pseudo Vector Processors Using Register Window Method”, IPSJ Journal Vol, 34, No. 4, pp669-680, 1993) address the latency problem of the main memory by expanding the register that stores the floating point used in scientific and engineering calculations by the window method and prefetching the value into this register. The structure of the floating point register according to this method is shown in FIG. In this method, the local register 1006, the overlap register 1007, the global register 100
A physical register 1001 composed of 8 is prepared in hardware, and the currently valid register is switched by switching the window. As a result, it is possible to load and store data in a register other than the register used for the operation at the same time as the operation, and the efficiency of the operation is improved. In addition, in FIG. 7, 1002-1
A physical register 005 corresponds to windows 0 to 3, respectively.

[0005]

However, in the above processing method, since dedicated registers specialized for numerical calculation are prepared, it is costly to prepare registers necessary and sufficient for large-scale calculation. Moreover, these resources cannot be utilized except for the purpose where the registers can be effectively used. Therefore,
It is difficult to apply it to general-purpose processors that require improved price / performance. For this reason, it is unavoidable to use a general-purpose processor having an ordinary cache memory. However, when a calculation using discontinuously arranged data is executed by a conventional general-purpose processor: The hit rate decreases, and the access delay of the main storage device cannot be hidden. Therefore, in a general-purpose processor having an operation pipeline, supply of desired data cannot catch up, and thus pipeline stall often occurs. In the cache memory, data is cached in units called lines of a predetermined size (for example, 4 words), so that even when one data is read, a plurality of adjacent data that are unnecessary for calculation are also cached. This causes a problem of performance degradation.

Therefore, the present invention intends to solve the above-mentioned problem by making it possible to effectively use a cache memory widely used for a general-purpose processor for discontinuously arranged data, thereby increasing the cache hit rate. Is.

[0007]

In order to solve the above problems, an information processing apparatus of the present invention discontinues a data relocation storage device for storing relocated data and a main storage device. An address translation device that relocates a series of existing data as a series of continuous data on the data relocation storage device, and the cache memory stores a copy of the contents of the data relocation storage device and the main storage device. An application program that holds the data and uses a series of data that exists discontinuously on the main memory is configured to access the relocated data.

In another embodiment, a data relocation area on a main storage device is used instead of the data relocation storage device to store the relocated data, and the address translation device uses the main storage. A series of data existing discontinuously on the device is rearranged as a series of continuous data on the data relocation area, and the cache memory holds a copy of the contents of the main storage device, and the data is stored on the main storage device. An application program that uses a series of discontinuous data is configured to access the rearranged data.

If the addresses of a series of data discontinuously existing in the main storage device have a certain regularity, the address translation device relocates the data according to the relocation information indicating the regularity. When the address of a series of data that exists discontinuously in the main memory is indicated by a pointer stored in another location in the main memory, the memory address of that pointer is rewritten. The pointer is read and the data to be rearranged is read according to the arrangement information.

[0010]

According to the present invention, the address translator converts a series of data, which is used by an application program and exists discontinuously in the main memory device, into a main memory device or a data rearrangement memory device different from the main memory device. The data is rearranged as a series of data having continuous addresses in the data rearrangement area provided on the storage device, and the cache memory sets the rearranged data as a caching target.

[0011]

FIG. 2 is a conceptual diagram of memory access in an information processing apparatus according to an embodiment of the present invention. In the present embodiment, the discontinuously arranged data 206 existing in the virtual address space 201 accessed by the software operating on the processor core 101 can be accessed as the continuous data 205 on the data relocation virtual address space 202. Relocate to. For this purpose, the data relocation memory space 203 is prepared in the physical address space, and the address conversion device 107 is used to provide the discontinuous data 208 in the physical address space 204 (corresponding to the discontinuous allocation data 206).
Continuous data 20 on the data relocation memory space 203.
7 (corresponding to the continuous data 205).

The data thus rearranged is mapped to another virtual address space. Therefore, the application code that accesses the discontinuous data is rewritten to access the continuous data in another address space. This rewriting is performed by the user or the compiler.

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus of the present invention having a data relocation function as described with reference to FIG. In FIG. 1, the processor core 101
Is the core part of an ordinary processor that consists of an arithmetic pipeline and register set. Processor core 10
1 is connected to the cache memory interface 103 by the processor data bus 151 for reading and writing necessary data. The cache memory interface 103 is connected to the cache memory 104 by a cache data bus 153 and a cache address bus 167, and also has a main memory device data bus 15
2 and a main memory physical address bus 166 to connect to the main memory interface 105, and the main memory interface 105 is connected to the main memory 106 via a main memory internal data bus 154 and a main memory internal address bus 168. . Also, in order to translate a virtual address into a physical address, TLB (Translation Lookasid
e Buffer) 102 is provided, and processor core 1
01 and the processor virtual address bus 165 and the TLB control line 181, and the cache memory interface 103 and the address bus 175. The part up to this point is no different from a normal processor.

Further, in this embodiment, for the purpose of data relocation, the address translation device 107, the data relocation storage device 109, and the data relocation storage device interface 1
08 and are provided.

The address translation device 107 is connected to the cache memory interface 103 by a signal line 183, a physical address bus 173 for address translation main storage device access, and a read data bus 157 for address translation device, and the main memory device interface 105 and address translation. The main memory device access physical address bus 173, the address conversion device read data bus 158, and the address conversion device write data bus 159 are connected, and the TLB 102 is connected.
And the address conversion virtual address buses 171 and 172 and the signal line 186, and the data relocation storage device interface 108 and the address translation relocation storage device access physical address bus 174 and the address translation device write data bus. 160 and an address translator read data bus 162. The data relocation storage device interface 108 is also connected to the cache memory interface 103 by the data relocation storage device data bus 155 and the data relocation physical address bus 169, and further, the data relocation storage internal data bus 156. Also, it is connected to the data relocation storage device 109 via the data relocation internal address bus 170.

The address translation device 107 is for generating a special register 131 for designating relocation from software, a relocation address generation device 132 for generating a relocated physical address, and a relocation source physical address. Of the physical address generator 133, a sequencer 134 for controlling the whole, a conversion information table device 135 for storing conversion information, and a read buffer 136, a shifter 137, a multiplexer 138 for actually rearranging data. , Write buffer 139, write bus 140
And a read bus 141.

The special register 131 is used for the processor core 1.
01 and the special register access control line 182, the conversion information table device 135 and the conversion information table input / output bus 184, the sequencer 134 and the signal line 191, and the physical address generation device 133 and the signal line 193, respectively. The sequencer 134 is connected to the special register 131, is also connected to the TLB 102 by the signal line 186, and the rearrangement address generator 1
32, physical address generator 133, read buffer 1
36, the shifter 137, the multiplexer 138, and the write buffer 139 are connected to them by a sequencer control line 185. The rearrangement address generation device 132 receives the control from the sequencer 134 via the control line 185, and the signal line 194 from the sequencer 134.
Via the physical address supplied from the TLB 102 and a physical address supplied from the TLB 102, and a physical address bus 174 for access to the address conversion relocation storage device is generated.
Through the data relocation storage device interface 108
To communicate. The physical address generation device 133 uses the control line 1
85 receives control from the sequencer 134, and the TLB 10 is transmitted through the address conversion physical address bus 172.
2 to generate a physical address for address conversion from the physical address supplied from 2 and the value supplied from the special register 131 through the signal line 193, and to the cache memory interface 103 and the main memory device interface 105 through the physical address bus for address conversion 173. introduce.

Further, the write bus 140 is connected to the main memory interface 105 by the address translator write data bus 159, to the data relocation memory interface 108 via the address translator write data bus 160, and the address translator write. Data bus 161
Is connected to the write buffer 139. The read bus 141 is a read data bus 157 for the address conversion device.
To the cache memory interface 103, the address translator read data bus 158 to the main memory interface 105, the address translator read data bus 162 to the data relocation memory interface 108, and the output bus 195 to the read buffer 136. , Output bus 196 allows multiplexer 13
8 are connected respectively.

Further, the output of the read buffer 136 is connected to the input of the shifter 137, and the output of the shifter 137 is connected to the input of the multiplexer 138 together with the output of the read bus 141 and the output of the write buffer 139. The output of the multiplexer 138 is connected to the input of the write buffer 139, and the output of the write buffer 139 is connected to the write bus 140 by the write data bus 161 for the address conversion device and fed back to the input of the multiplexer 138.

The operation of the present embodiment thus constructed will be described below in order.

The data relocation according to the present invention is realized by the cooperation of hardware and software. First, it is necessary to set the data relocation information. This data rearrangement information is determined according to the order in which the software refers to the data, so the setting is performed by the software. As a method of instructing by software, a method of expanding an instruction set or a method of setting a value in a special register can be considered, but in the present embodiment, a method of setting by the special register 131 is adopted. The special register 131 is shown in FIG.
In the address translation device 107, as shown in, It is set in the special register 131 through the special register access control line 182 in accordance with an instruction from software operating on the processor core 101. The rearrangement information set in the special register 131 is also transmitted to the conversion information table device 135 through the conversion information table input / output bus 184 and is stored until the time of writing back described later.

For example, data starting from the virtual address 0x1000, 0x1010, 0x1020, 0x
When relocating a total of 100 pieces of data such as 1030, ... to the virtual address 0x20000 and beyond by reading only, a unit word of data, a start virtual address of data 0x1000, a data arrangement rule + 0x10, and the number of data 100. Relocation information such as relocation virtual address 0x40000 is set in the special register 131.

Special register 131 by software
When the relocation information necessary for the
Is started, and the relocation process is executed under the control.
First, the sequencer 134 sends the start virtual address of the data set in the special register 131 to the TLB 102 via the address bus 171, and converts it into a physical address.
The physical address obtained by being translated by the TLB 102 is transmitted to the physical address generator 133 via the bus 172. The physical address generator 133 includes a sequencer 134.
Under the control of, the physical address transmitted from the TLB 102 is first selected, and the selected physical address is sent to the main memory device interface 105 through the physical address bus 173 as it is. Since the latest data at that address may exist in the cache memory 104, the same address is also sent to the cache memory interface 103. After that, the physical address generation device 133 sequentially generates the second and subsequent physical addresses based on the physical address generated this time and the data arrangement rule set in the special register 131, and sequentially outputs them to the physical address bus 173. The operation of the special register 131
Continue until the physical addresses for the number of data set in are generated. That is, in the above example, the virtual address 0x
Assuming that 1000 is mapped to the physical address 0x2000, the TLB 102 converts 0x1000 to the address 0x2000, and the physical address generation device 1
In 33, a total of 10 from 0x2000 to 0x10
Generates and outputs 0 addresses.

Physical address generator 133 to bus 17
The cache memory interface 103, which has been supplied with the physical address via No. 3, sends the line including the data to the read bus 141 via the data bus 157 when the corresponding data exists in the cache memory 104.
Send to Further, the main memory device interface 105 transmits a line including the corresponding data read from the main memory device 106 to the read bus 141 via the data bus 158.

The read bus 141 sends the data sent from the cache memory interface 103 to the read buffer 136 when the data is sent, and the data sent from the main memory device interface 105 to the read buffer 136 when the data is not sent. Write. This read buffer 136
The data written in (1) is logically shifted by the shifter 137 at the next stage as necessary and is supplied to the multiplexer 138. The multiplexer 138 selects the data supplied from the shifter 137 and the data stored in the write buffer 139 in byte units and newly writes the selected data in the write buffer 139, so that the data to be rearranged on the write buffer 139. Marshal as continuous data. The data of the write buffer 139 is the data bus 161, the write bus 140 and the data bus 1.
Data relocation storage device interface 1 via 60
08, and the data relocation storage device interface 108 writes the above data to the data relocation storage device 109 indicated by the physical address simultaneously supplied from the relocation address generation device 132 through the physical address bus 174.

Details of the operation of these functions will be described below with reference to specific examples. The data bus has a width of 8 bytes, and the address 0x40000 of the data relocation virtual memory space is the address 0x0 of the data relocation storage device 109 and the TLB 102.
The other settings are the same as the above-mentioned example.

In this case, the main memory device interface 10
5 or the data of addresses 0x2007-0x2000 are first transmitted in 8-byte units from the cache memory interface 103 and stored in the read buffer 136 having an 8-byte capacity. 0x2003 in this data
Data relocation storage device 10 is at address 0x2000
This is data to be stored at addresses 0x3-0x0 of 9 and, in this case, there is no need to shift, so it is stored in the write buffer 139 through the multiplexer 138 without being shifted by the shifter 137. Next, 0x2017-
The data at the address 0x2010 is sent and stored in the read buffer 136. 0x2013 in this data
-The address 0x2010 is the data relocation storage device 1
Since it is the data to be stored in the address 0x7-0x4 of 09, the shifter 137 shifts it to the left by 4 bytes, and the multiplexer 139 selects the content of the write buffer 139 for the lower 4 bytes and the content of the shifter 137 for the upper 4 bytes. Then, it is stored in the write buffer 139. As a result, the physical address 0x2 is sequentially stored in the write buffer 139.
013, 0x2012, 0x2011, 0x2010,
0x2003, 0x2002, 0x2001, 0x20
The data at address 00 will be stored.

This data is stored in the data relocation storage device 10.
Since the data is to be stored starting from the address 0x0 of 9, the relocation address generator 132 generates the address 0x0. This is because the sequencer 134 sets the relocation virtual address 0x40000 set in the special register 131 to the TLB10.
It is performed by converting the physical address 0x0 by 2 and transmitting it to the relocation address generating device 132 via the bus 172, and the relocation address generating device 132 outputs the transmitted physical address 0x0 as it is. The reallocation address generation device 132 uses the first physical address 0x.
After the generation of 0, the physical address generated by itself and the increment value (0x8) input from the sequencer 134 through the signal line 194 are used to determine the physical address 0x8, 0x16, ...
In this way, an address is generated for each 0x8 address.

The physical address 0x0 generated by the relocation address generation device 132 is sent to the data relocation storage device interface 108 through the physical address bus 174, and at the same time, the above data stored in the write buffer 139 is the write data bus. 161, light bus 14
0 and is sent to the data relocation storage device interface 108 through the write data bus 160, and the data relocation storage device interface 108 stores the above data from the address 0x0 of the data relocation storage device 109. As described above, the data relocation storage device 1 for the first two words of data to be relocated (8 bytes in total)
The relocation to 09 is completed. The address translation device 107 repeats the above-described operation to perform relocation for all relocation target data set in the special register 131. Then, when the rearrangement is completed, the sequencer 134 notifies the TLB 102 of the processor core 101 and the cache memory interface 1.
It is instructed to validate the conversion request corresponding to the data relocation virtual address space 202 from 03.

Next, the operation at the time of memory access by the software operating on the processor core 101 will be described.

The application program operating on the processor core 101 accesses the relocated data as described above to the relocated virtual address and executes a predetermined process such as calculation. . Therefore, in the application program, for example, The code part that refers to the data at the address before relocation like It has been rewritten as. Although an example in which the rewriting is performed at the C language level is shown here, it is usually desirable to automatically perform a combination of these relocations and the setting of the previous relocation information in the special register by a compiler.

When the processor core 101 executing the application code accesses the relocated virtual address, for example, address 0x40000, the corresponding data is initially cached in the cache memory 104.
Since it does not exist in the cache memory interface 103, the cache memory interface 103 reads the line including the corresponding data from the data relocation storage device 109 through the data relocation storage device interface 108, and reads the line.
No. 4, and the corresponding data in the line is returned to the processor core 101. This is done as follows.

First, the access address 0x40000 is transmitted to the TLB 102 by the address bus 175, and Tx
It is converted by the LB 102 into an address for accessing the data relocation memory space 203. Next, the cache memory interface 103 transmits the line address including the converted address to the data relocation storage device interface 108 through the address bus 169. The data relocation storage device interface 108
The line of the transmitted line address is read from the data relocation storage device 109 and returned to the cache memory interface 103. The cache memory interface 103 stores the returned line in the cache memory 104, and returns the corresponding data in the line to the processor core 101. In this way, after the rearrangement, the rearranged data can be handled like normal data. If the processor core 101 accesses the data relocation virtual address space 202 before the relocation is completed, the TLB 102 has not yet validated the conversion request from the processor core 101 for the data relocation virtual address space. The processing of the processor core 101 is kept waiting until the rearrangement is completed.

Further, the cache memory 104 is cached line by line, and only the data accessed by the application code is packed in consecutive addresses and arranged in the data relocation storage device 109. All data cached in the cache memory 104 from the data relocation storage device 109 at the time of a mishit is data to be accessed by the application code. As a result, the cache mishit rate decreases.

As described above, according to this embodiment,
The processor core 101 can use the cache memory 104 to handle data of consecutive addresses. As a result: -Unnecessary data is not loaded into the cache memory. -Avoid waste of cache memory and reduce the possibility that necessary data will be replaced from cache memory. That is, the cache memory 104 can be efficiently used. It should be noted that by performing the relocation processing well before the data is actually used, the processor core 101 can perform other calculation processing during the time during the data relocation, resulting in further efficient execution. It will be possible.

Next, the operation of writing back the relocated data to the normal space when the use of the relocated data is completed will be described.

When the use of the relocated data is completed, the application program operating on the processor core 101 sets a special effect to the special register 131 and writes the data back to the normal space to the address translation device 107. Instruct. In the address translation device 107, the sequencer 134 first transfers the relocation information regarding the relocation data instructed to be written back from the translation information table device 135 to the special register 131, and also transfers the processor core 101 and the cache memory interface to the TLB 102. It is instructed to invalidate the conversion request corresponding to the data relocation virtual address space 202 from 103.

Next, the sequencer 134 causes the relocation address generation device 132 to generate addresses of the relocation data in the data relocation storage device 109 so that the relocation data is sequentially read, and the physical addresses are generated by the physical address generation device. 133
The addresses are sequentially written to the addresses on the main storage device 106 generated in step. Here, as described above, the main storage device 1
Since 06 can be read / written only in a specific byte unit, the write destination data is read once, and the relocation data portion in the read data is replaced with the relocation data read from the data relocation storage device 109 to obtain the original data. Write back to the address of. In the case of the above example, specifically, the following operation is performed.

The sequencer 134 is a special register 131.
Relocation virtual address 0x40000 set to TL
At B102, the physical address is converted to 0x0 and given to the relocation address generation device 132, and the relocation address generation device 1
32 first transmits the physical address 0x0 to the data relocation storage device interface 108 via the physical address bus 174, and the data relocation storage device interface 108 transfers data from the data relocation storage device 109 to the data relocation memory space. 203 address 0x7-0x0
The address data is read and stored in the read buffer 136 through the read data bus 162, the read bus 141 and the output bus 195. At the same time, the sequencer 134
The start virtual address 0x1000 set in the special register 131 is given to the TLB 102 to be converted into a physical address (for example, 0x2000), and the address bus 1
To the physical address generator 133 through 72,
The physical address generator 133 initially sets the address 0
The address x2000 is generated and transmitted to the cache memory interface 103 and the main memory device interface 105 through the address bus 173 to request a read. Physical address 0x2007-0x read by this
The data at address 2000 is transmitted from the cache memory interface 103 or the main memory device interface 105 to the read bus 141, and the read bus 141 outputs this to the multiplexer 138 through the output bus 196.

0x3-0x0 of data relocation memory space
Address data is physical address 0x2003-0x200
Since it suffices to write back to the address 0, the shifter 137 in this case outputs the data of 0x2007-0x2000 stored in the read buffer 136 to the multiplexer 138 without performing the shift operation, and the multiplexer 138 outputs the upper 4 bytes of the read bus 141. Data from (0x2007
(0x2004 address data), the lower 4 bytes select the data (0x3-0x0 address data) from the shifter 137, and store it in the write buffer 139. The data stored in the write buffer 139 is the write bus 1
It is sent to the main memory device interface 105 through 40, and is written in an 8-byte area starting from the address 0x2000 generated in the physical address generator 133 at that time. This completes the writing back of the relocation data of 0x3-0x0.

Next, the sequencer 134 causes the physical address generator 133 to generate the next address 0x2010, loads the data at the address 0x2017-0x2010 from the main memory 106 or the cache memory 104 to the read bus 141, and causes the multiplexer 138 to store the data. Input it. The data of addresses 0x7-0x4 remaining in the upper 4 bytes of the read buffer 136 is the physical address 0x201.
It is enough to write it back to the address 3-0x2010, so shifter 1
In this case, 37 shifts to the right by 4 bytes, and the multiplexer 138 stores the upper 4 bytes of the data (data at addresses 0x2017-0x2014) from the read bus 141.
The lower 4 bytes are data (0x7-
0x4 address) is selected and the write buffer 139 is selected.
To be stored. The data stored in the write buffer 139 is sent to the main memory device interface 105 through the write bus 140, and at that time, the physical address generation device 13
It is written in the 8-byte area starting from the address 0x2010 generated in 3. This completes the write-back of the 0x7-0x4 relocation data.

By repeating the above operation, all the rearranged data are written back to the main memory 106.

FIG. 3 is a block diagram of an essential part of an information processing apparatus according to another embodiment of the present invention, and FIG. 4 is a conceptual diagram of memory access in the embodiment. In the embodiment described with reference to FIGS. 1 and 2, a data relocation storage device 109 is provided as a dedicated storage device and a data relocation storage device interface 108 is provided as an interface for the data relocation memory space. . Since the data relocation storage device 109 requires less storage capacity than the main storage device 106, it is possible to use a high-speed storage device.
Since the data to be used is explicitly rearranged prior to its use, the effect is considered sufficient. However, in a general-purpose system, it is necessary to reduce the number of devices as much as possible to reduce the cost. Therefore, in the embodiment shown in FIGS. 3 and 4, it is possible to arrange the relocation data on the main storage device by omitting the storage device dedicated to the data relocation and expanding the software for memory management. . Less than,
This embodiment will be described.

As shown in FIG. 3, in this embodiment, the data relocation storage device 109 and the data relocation storage interface 108 are removed from the embodiment of FIG.
The internal structure of the address translation device 107 is changed so that the relocation address generation device 132 and the physical address generation device 133 are changed.
Is selected by the selector 301 and supplied to the main memory device interface 105 and the cache memory interface 103 through the address bus 302.

When data is to be relocated, the application program issues a system call to the OS or the like, and as shown in FIG.
A data relocation virtual address space 402 is secured above.
At this time, the data relocation physical address space 403 corresponding to the data relocation virtual address space 402 is allocated in the physical address space 404. After that, the application program sets the relocation information similar to the embodiment of FIG. 1 in the special register 131. The address rearrangement process is the same as that of the embodiment of FIG.
When the desired data is stored in the selector 301, the selector 301 selects the address generated by the relocation address generator 132 and sends it to the main memory device interface 105. This allows data to be relocated to the data relocation physical address space 403 of the main storage device 106.

Also when writing back the rearranged data, the processing proceeds in substantially the same manner as in the embodiment of FIG. However, since the relocation data exists in the main storage device 106, when loading the relocation data into the read buffer 136, the selector 30
1 differs in that the address generated by the relocation address generation device 132 is transmitted to the main storage device interface 105, and the main storage device interface 105 sends relocation data to the read buffer 136.

FIG. 5 is a block diagram of the essential parts of an information processing apparatus according to yet another embodiment of the present invention. In the embodiment described with reference to FIGS. 1 and 3, the reference order of the discontinuously arranged data is given to the address conversion device by a mathematical expression to rearrange the continuous data. However, the reference of the discontinuous data is not the regularity that can be shown by a mathematical expression, and the cases shown by the pointer as described below often appear in scientific and technological calculations.

In the case of such processing, the rule of data reference cannot be given to the address translation device by a mathematical expression. Therefore, in the embodiment shown in FIG. 5, in order to cope with such a case, by designating a pointer in which a variable indicating the data storage information is stored, the address translator automatically reads the pointer. The data is relocated. This makes it possible to refer to the discontinuous data by the variable index within the framework of the same rearrangement mechanism.

The embodiment of FIG. 5 is different from the embodiment of FIG.
An address queue 501 is newly provided in the address translation device 107. The address queue 501 is a FIFO that stores the contents of pointer variables stored in the main storage device 106.
It is an O (First In First Out) type cue. Further, the selector 301 sends the contents of the address queue 501 to the TLB 102 via the virtual address bus for address conversion 171.
It is extended so that the address converted to a physical address by sending to can be selected. The operation of this embodiment will be described below with reference to FIGS. 5 and 4, focusing on the differences from the embodiment of FIG.

The application program operating on the processor core 101 secures the data relocation virtual address space 402 in the virtual memory space 401, and then sets the relocation information as described below in the special register 131. -Reference type pointer-Data unit word-Pointer start virtual address 0x1000-Pointer placement rule + 0x10-Number of pointers 100-Relocation virtual address 0x40000

In the case of such rearrangement information, 0x100
It is necessary to load the data at the address indicated by the address stored at address 0 as the first data. Therefore, the sequencer 134 converts the pointer start virtual address 0x1000 set in the special register 131 into a physical address by the TLB 102, and the physical address generator 133 first generates this physical address. At this time, the selector 301 selects this address, and the cache memory interface 103 and the main memory device interface 10 are selected.
Send to 5. The data of the corresponding address (pointer of virtual address expression) read by this is read bus 14
1 is stored in the address queue 501. The pointer stored in the address queue 501 is converted into a physical address by the TLB 102, and the selector 301 selects this address and selects it from the cache memory interface 10.
3 and the main storage device interface 105. The data thus obtained becomes the data to be rearranged, is stored in the read buffer 136, and thereafter, the same rearrangement and address conversion rearrangement as in the embodiment of FIG. 3 are performed.

Similarly, when the rearranged data is written back to the main storage device 106, the address queue 501
Load the data pointer, load the required data,
After rearrangement, it will be written back. If the pointer has been rewritten before rewriting after rearrangement, the data is rewritten to the location indicated by the new pointer variable, and therefore the address translation device 107 can be used for copying the data.

[0053]

As described above, according to the present invention, a series of data existing discontinuously in the main memory is relocated as data of consecutive addresses in another memory area, and the data after the relocation is relocated. Is targeted for caching and is targeted for access by the application program, the locality of memory access during execution of the application program is enhanced, and the cache hit rate is improved accordingly, and the execution processing speed of the application program is improved. In the present invention, the data rearrangement process is an overhead, but once the rearrangement is performed, the subsequent rearrangement is unnecessary, and therefore a series of data existing discontinuously in the main memory is accessed many times. In such a case, it does not matter so much.

Further, according to the configuration using the data relocation area on the main storage device, the amount of hardware can be reduced and the cost can be reduced as compared with the case of using the dedicated data relocation storage device. is there.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an information processing apparatus according to an embodiment of the present invention.

2 is a conceptual diagram of memory access in the information processing apparatus of the embodiment of FIG.

FIG. 3 is a block diagram of a main part of an information processing apparatus according to another embodiment of the present invention.

FIG. 4 is a conceptual diagram of memory access in the information processing apparatus of the embodiment of FIG.

FIG. 5 is a block diagram of essential parts of an information processing apparatus according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional vector computer.

FIG. 7 is a conceptual diagram of a register window.

[Explanation of symbols]

101 ... Processor core 102 ... TLB (Translation Lookaside Buffer) 103 ... Cache memory interface 104 ... Cache memory 105 ... Main memory device interface 106 ... Main memory device 107 ... Address translation device 108 ... Data relocation memory device interface 109 ... Data re- Arrangement storage device 131 ... Special register 132 ... Relocation address generation device 133 ... Physical address generation device 134 ... Sequencer 135 ... Conversion information table device 136 ... Read buffer 137 ... Shifter 138 ... Multiplexer 139 ... Write buffer 140 ... Write bus 141 ... Read bus 151 ... Processor data bus 152 ... Main storage device data bus 153 ... Cache data bus 154 ... Main storage device internal data bus 155 ... Data relocation storage Device data bus 156 ... Data relocation storage device internal data bus 157 ... Address translation device read data bus 158 ... Address translation device read data bus 159 ... Address translation device write data bus 160 ... Address translation device write data bus 161 ... Write data bus for address translation device 162 ... Read data bus for address translation device 165 ... Processor virtual address bus 166 ... Main memory physical address bus 167 ... Cache address bus 168 ... Main memory internal address bus 169 ... Data relocation Physical address bus 170 ... Internal address bus for data relocation 171 ... Virtual address bus for address translation 172 ... Physical address bus for address translation 173 ... Physical address bus for address translation main memory device 17 ... Address translation / relocation storage device access physical address bus 175 ... Address bus 181 ... TLB control line 182 ... Special register access control line 183 ... Address translation device-cache information transmission signal line 184 ... Translation information table input / output bus 185 ... Sequencer control line 186 ... Address translator-signal line for transmitting TLB information 201 ... Virtual address space 202 ... Data relocation virtual address space 203 ... Data relocation memory space 204 ... Physical address space 205 ... On virtual address space Relocation data 206 ... Discontinuous allocation data on virtual address space 207 ... Relocation data on data relocation memory space 208 ... Discontinuous data on physical address space 301 ... Selector 302 ... Address translation Physical address for access to main storage device Bus 401 ... virtual address space 402 ... data relocation virtual address space 403 ... data relocation physical address space 404 ... physical address space 405 ... relocation data on virtual address space 406 ... discontinuous data on virtual address space 407 ... data relocation Relocation data 408 on physical address space ... Discontinuous data 501 on physical address space ... Address queue

Claims (4)

[Claims] 1. A data relocation storage device for storing relocated data, and a series of data that is discontinuous in a main storage device and continuous in the data relocation storage device. And a cache memory that holds a copy of the contents of the data relocation storage device and the contents of the main storage device, and uses a series of data that exist discontinuously on the main storage device. An information processing apparatus, wherein the application program is configured to access the relocated data. 2. A cache memory for holding a copy of the contents of the main memory, and for storing the relocated data,
A data relocation area on the main storage device; and an address translation device for relocating a series of data existing discontinuously on the main storage device as a series of continuous data on the data relocation area. An application program that uses a series of data that exists discontinuously on a storage device
An information processing apparatus configured to access the data after the rearrangement. 3. When the addresses of a series of data existing discontinuously on the main storage device have a certain regularity, the address translator should relocate according to the relocation information indicating the regularity. The information processing apparatus according to claim 1, wherein the information is read. 4. A rearrangement indicating a storage address of a pointer when the address of a series of data existing discontinuously on the main memory is indicated by a pointer stored at another location on the main memory. 3. The information processing device according to claim 1, wherein the address translation device reads out data to be rearranged according to information according to information.