JPH06119238A - Method and device for controlling main storage - Google Patents

Abstract

PURPOSE:To optimize a partial write operation and to control it at a high speed by providing a comparator for comparing occasionally a partial write exclusive address register and an address, in a main storage controller. CONSTITUTION:In the case actuated memory write is partial write, first of all, the contents of a partial write exclusive register 5 in a main storage controller 3, and the contents of an address register 6 latched at the time of actuating the memory write are compared by a comparator 7. In the case a result of comparison is formed, and also, the contents of a flag 8 set from a central processing unit 1 are set to an effective mode, an output of an AND gate 9 becomes '1' and a partial write hit is decided. An output of the hit is sent to selectors 19-22 of a data input and a memory data register 10. In such a way, data existing in the register 10 is used again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory control method and apparatus capable of speeding up partial write access (partial write).

[0002]

2. Description of the Related Art Conventionally, in partial write access, all word data for an address to be accessed is first read, and the data written to that data is merged and merged. Generate an ECC code according to the write data,
I was writing to main memory. That is, when performing a partial write access in the main memory device using the ECC system, the memory data for the address to be accessed is temporarily fetched in the memory read data register in the main memory control device and The write data received from the central processing unit or the I / O control unit is executed to perform the charr write, and an ECC code is generated for the written write data to generate the main memory. I was writing to the device. Therefore, the general memory access mode requires the longest access time. Further, conventionally, a method using a buffer storage device such as a cache memory is the most general method in order to speed up data transfer with the main storage device. For example, JP-A-3-2696
In the "buffer storage device" described in Japanese Patent Publication No. 50, the move-in operation for registering in the buffer (comparing whether the addresses match) and the store operation by the store instruction are integrated into one, and the main storage device side is provided. On the other hand, by changing partial write to full store (byte mark in store buffer
Rewrite according to the content), to speed up the store operation. This device is provided with a write address register and a data register. However, since the read data from the main memory is not held in the data register for writing, the read from the main memory can be omitted when the partial write continues. No, it wasn't always enough.

[0003]

As described above, the conventional E
In the partial write control for the CC type main memory device, all the word data of the address to be written is fetched into the temporary main memory control device before the memory write control, and this data and the central data are stored. The write data received from the processing unit or the I / O control unit is merged, the ECC code is regenerated based on the result, and the write process is performed on the main storage unit. Therefore, in the main memory at the time of the partial write access, the memory read control is required in addition to the memory write control, which has been a bottleneck in shortening the access time. SUMMARY OF THE INVENTION An object of the present invention is to solve such a conventional problem, and when a partial write is continuously performed to the same address, a main memory control method and apparatus capable of shortening access time and speeding up memory access. To provide.

[0004]

To achieve the above object, a main memory control device of the present invention comprises: (a) a central processing device or a processing device having a function equivalent to this; and a main memory device having an ECC. In a processing system having a main memory control device for controlling the main memory device, all word data previously read from the main memory device is stored in the main memory controller, and the next partial write is performed. When the access is at the same address as the last time, one or more memory data registers whose contents are read instead of being read from the main memory and all words of the partial write address last accessed to the main memory Partial write dedicated address register that stores the address corresponding to, the partial write dedicated address register and the central processing unit or another processing unit -Compare the write write addresses and if they match, the part of the memory data register corresponding to the above partial write address is merged with the write data output from the central processing unit or another processing unit. And comparing means for writing the merged data to the main memory. Further, according to the main memory control method of the present invention, (b) when partial writing is executed in the main memory device, all word data corresponding to the partial write address are read from and read from the main memory device. In a main memory control method in which the changed data is partially changed, an ECC code is generated for the partially changed data, and then the changed data and the generated ECC code are written. , The address register storing the previously accessed partial write address is compared with the partial write address accessed this time, and if the comparison results match, all words read last time are read. A memory write in which the portion corresponding to the partial write address of the memory data register in which the data is stored is rewritten to the memory write data to be accessed this time and rewritten to the main memory device. The ECC code generated from the data of the register and the data of the memory write register is stored in the memory data register, and when the comparison result does not match, the main memory corresponds to the partial write address. Read all read data, store the read data in the memory data register, and replace the part corresponding to the partial write address of the stored data with the memory write register. The memory write data and the ECC code generated from the memory write data are simultaneously stored in the main memory and the memory data register. In addition, (c) a flag for judging the validity of the data stored in the memory write register is provided in the address register storing the previously accessed partial write address, and when the system power is turned on. And when a failure occurs, the flag is set to invalid, when the partial write address is updated normally in the address register, it is set to valid. When the flag is invalid, the previously accessed partial write address is set. It is also characterized in that the comparison result when the stored address register is compared with the partial write address accessed this time is forcibly made to be inconsistent. Also,
(D) When a full write is activated from the central processing unit or another processing unit, the write address at the time of activation is compared with the contents of the address register that stores the previously accessed partial write address, and the comparison result If the two match, the contents of the address register are updated to the contents of the write address.

[0005]

In the present invention, by using the address register dedicated to the partial write and the means for comparing the addresses at any time, all the word data for the address to be written can be obtained before the partial write. It is determined whether a fetch operation is required once in the main memory, and when writing to the same address, skip the fetch operation to realize memory access optimization and speedup at the time of partial write. . That is, at the time of starting the partial write from the central processing unit or the I / O control unit,
If the results of the comparison circuit match, the data of all the words of the address to be written in the partial write access performed before this activation is already present in the main memory control device, so the memory memory is rewritten. It is not necessary to perform the read operation, and it is sufficient to manage the write data received at the time of start-up and the existing data, generate the ECC code, and perform only the memory write control. That is, since the appearance is the same as the full write control for the main storage device, the speed of the partial write access can be increased.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a main memory control device to which the present invention is applied. In FIG. 1, reference numeral 1 is a central processing unit, 2 is a main memory unit, 3 is a main memory control unit, 4 is a memory write register for holding write data from the central processing unit 1, and 5 is a partial address dedicated to partial write. ,
6 is an address register, 7 is a comparator for comparing the contents of the registers 5 and 6, 8 is a flag for controlling whether the comparison result is valid, 9 is the result of comparison by the comparator, and 8 is the flag. AND gate to invalidate the condition, 1
0 a memory data register for accumulating data read from the main memory 2, 11 a timing control circuit for generating a control signal for the main memory 2, 12 a data fetched in the memory data register 10 An ECC checker for performing an ECC check, 13 an ECC generation circuit for generating an ECC when writing to the main memory 2, and 14 a data between the main memory 2 and the main memory controller 3. Bidirectional driver for controlling data direction
Margin selectors 19 to 22 for performing charlight
Is a data input selector for the memory data register 10 and is connected so as to select a normal memory read data bus 26 and a memory write data bus 27. Reference numeral 23 is a byte enable indicating a byte position to be partially written, 24 is a data bus, 25 is an address bus, and 28 is a dedicated address register 5 for partial write.
Is an address update-dedicated bus used for updating the contents of the address register 6 to the contents of the address register 6.

FIG. 2 is an operation flowchart in FIG. Here, the speeding up of the partial write will be described by taking the partial write access from the central processing unit 1 as an example. When the memory write is activated from the central processing unit 1 (step 51), it is first judged based on the information in the byte enable 23 whether the memory write mode is the partial write (step 52). ).
When the activated memory write is a partial write, the comparator 7 first causes the partial memory in the main memory control device 3 to be accessed.
The contents of the dedicated write dedicated register 5 are compared with the contents of the address register 6 latched when the memory write is activated (step 53). If the comparison result is satisfied and the content of the flag 8 set by the central processing unit 1 is valid mode.
If it is set to the read mode, the output of the AND gate 9 becomes 1 and a partial write hit is judged. The output of the hit is sent to the data input selectors 19 to 22 and the memory data register 10. As a result, the data existing in the memory data register 10 is reused. That is, by the memory write activation before the memory write access activated this time, the memory data register 10 in the main memory control device 3 has the same contents as the data in the main memory device address which is about to be partially written. Since it has already been fetched, it is not necessary to carry out the memory read processing, and the contents of the memory data register 10 and the memory write register 4 are read by the selectors 15 to 18 according to the information of the byte enable 23.
(Step 54). Then, based on the merged data, the ECC generating circuit 12 newly generates an ECC code (step 55), and a memory write process is performed (step 56). As a result, the partial write process ends.

In FIG. 2, when the comparison by the comparator 7 does not match (step 53), the memory data register 10 is prepared for the next memory partial write access.
The contents of the above are also fetched via the selectors 19 to 22 with the write data for which the memory has been written, and updated (step 57). Thus, in the memory write process, the write mode activated by the central processing unit 1 is
Even in the Charle write mode, the main memory 2 can be processed in the full write mode without performing the read modify write. As a result, the memory read processing at the time of executing the partial write, which was indispensable in the past, can be omitted, so that the access time at the time of the partial write to the main memory 2 can be shortened. Thus, even if the activated memory write access is a partial write, when the comparison result of the comparator 7 does not match (step 5).
3) Like the conventional partial write access processing, first, the contents of all words of the main memory 2 are stored in the memory.
The data is fetched into the memory data register 10 by performing the read processing (step 57), and the comparison result of the comparator 7 does not match. Therefore, the contents of the partial address dedicated register 5 are also updated via the dedicated address update bus 28. The contents of the memory write activation address of this time are updated (step 58). Thereafter, the contents of the memory data register 10 and the contents of the memory write register 4 in which the memory write data received from the central processing unit 1 are latched are
Marging is performed by the selectors 15 to 18 (step 5
4) Based on the result of the merge, an ECC code is generated using the ECC generation circuit 12 (step 55), memory write processing is performed, and at the same time the written data is selected by the selector 1
The memory data register 10 is updated via 9 to 22 (step 56).

On the other hand, when the mode of the memory write process started from the central processing unit 1 is not the partial write but the full write (step 52), the partial write mode is set. Similarly, the contents of the address register 6 in which the address received by the memory write access this time is latched by the comparator 7 are compared with the contents of the address register 5 dedicated to the partial write (step 59). If the comparison results of the comparator 7 match, the contents of the address register 5 dedicated to the partial write are transferred to the address register 6 via the bus 28 dedicated to the address update.
(Step 60). Thereafter, the contents of the memory write register 4 in which the memory write data received from the central processing unit 1 are latched are changed to the selector 15
Through 18 and use the ECC generation circuit 12 to E
The CC code is generated (step 55), the memory full write is executed, and at the same time, the memory write data is selected by the selector 19
22 to 22 to update the memory data register 10 (step 56). Similarly, the mode of memory write processing is not partial write (step 5
2) and when the comparison result of the comparator 7 is inconsistent (step 59), the contents of the address register 5 for exclusive use of the partial write and the contents of the memory data register 10 are not updated, and the central processing unit 1 The contents of the memory write register 4 in which the data received from the memory 15 are passed through the selectors 15 to 18, and the ECC code is generated using the ECC generation circuit 12 (step 55).
Memory full write is executed (step 56).

As described above, in this embodiment, the central processing unit 1 and the main memory 2 having the ECC and the main memory control unit 3 are used for the partial write to the same address as the previous partial write access. If access occurs,
An address register 5 dedicated to partial write and a memory data register 10 are provided in the main memory controller 3,
Addresses and write data are stored in these registers at the time of a charal write access, and when the next partial write address is equal to the content of the partial write dedicated address register 5, the data is read from the main memory device 2. Since the data is read from the memory data register 10 instead of being read, the access time can be shortened.

[0011]

As described above, according to the present invention,
It is possible to optimize the partial write operation and control the speedup. That is, the main memory controller is provided with a special address register for partial write and a comparator for comparing the addresses at any time, so that all word data for the addresses to be written before the partial write is performed. Since it is determined whether or not it is necessary to temporarily take the data into the main storage device, it is possible to optimize and speed up the memory access during the partial write.

[0012]

[Brief description of drawings]

FIG. 1 is a block diagram of a main memory control device showing an embodiment of the present invention.

FIG. 2 is a flowchart of the partial write operation in FIG.

[Explanation of symbols]

 1 central processing unit 2 main memory unit 3 main memory control unit 4 memory write register 5 partial write dedicated address register 6 address register 7 comparator 8 flag 9 AND gate 10 memory data register 11 timing control circuit 12 ECC check circuit 13 ECC generation circuit 14 Bidirectional driver 15 to 22 selector 23 Byte enable 24 Data bus 25 Address bus 26 Memory read data bus 27 Memory write data bus 28 Address update dedicated bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaaki Yamamoto 1-31-31 Nagara Nishi, Kita-ku, Osaka City, Osaka Prefecture Hitachi Nishi Service Engineering Co., Ltd.

Claims (4)

[Claims] 1. A central processing unit or a processing unit having a function equivalent to the central processing unit, and a main storage unit having an ECC,
In a processing system having a main memory control device for controlling the main memory device, all word data previously read from the main memory device is stored in the main memory control device, and the next partial is stored. One or more memory data registers whose contents are read instead of being read from the main memory when the write access is at the same address as before;
A partial address for exclusive use of a partial write for storing an address corresponding to all the words of the partial write address previously accessed to the main memory, the partial register for exclusive use of the partial write and the above central processing unit or other Compare the partial write address from the processor,
If they match, the portion of the memory data register corresponding to the partial write address is merged with the write data output from the central processing unit or another processing unit, and the merged data is merged. A main memory control device, comprising: a comparison unit for writing the data into the main memory device. 2. When partial writing is executed in the main memory, all word data corresponding to the partial write address is read from the main memory and the read data is partially changed. In the main memory control method of writing the changed data and the generated ECC code after the ECC code is generated for the partially changed data, the previously accessed partial is used. The address register storing the write address is compared with the partial write address accessed this time. If the comparison result is the same, all the word data read out previously are stored. The data corresponding to the above partial write address of the memory data register is rewritten into the memory write data to be accessed this time, and the data of the memory write register is rewritten into the above main memory device. And an ECC code generated from the data of the memory write register is stored in the memory data register, and when the comparison result is inconsistent,
All read data corresponding to the partial write address is read from the main memory, the read data is stored in the memory data register, and the partial of the stored data is stored. The portion corresponding to the write address is replaced with the memory write register, the replaced memory write data and the E generated from the memory write data.
A main memory control method characterized in that a CC code is stored in the main memory device and the memory data register at the same time. 3. The main memory control method according to claim 2, wherein the address register storing the previously accessed partial write address stores the validity of the data stored in the memory write register. A flag for determining whether the flag is set, the flag is set to be invalid when the system is powered on and a failure occurs, and is set to be valid when the partial write address is normally updated in the address register. If it is invalid, the comparison result of comparing the address register that stores the previously accessed partial write address with the currently accessed partial write address is forcibly set as a mismatch. Main memory control method. 4. The main memory control method according to claim 2, wherein when a full write is activated from the central processing unit or another processing unit, the write address at the time of activation and the partial write accessed last time. A main memory control method comprising: comparing the contents of an address register in which an address is stored, and updating the contents of the address register to the contents of the write address if the comparison result is a match.