JPH04245334A - Instruction prereading control system for information processor - Google Patents

Abstract

PURPOSE:To prevent the instruction in an erroneous branching destination address from being read owing to the switching of an addressing mode when an instruction is read by a predicted branching destination address. CONSTITUTION:The information processor is equipped with an associative memory for a branching instruction and prereads instructions, and the system consists of the associative memory (branching destination associative memory) 10 for storing branching destination information on the branching instruction, an instruction unit 20 which prereads and decodes the instruction, an arithmetic unit 40 which executes the instruction, and a main memory 50 housing the instruction and data. In this case, an address mode register 16 and a predictive address mode register 17 are added to the associative memory 10 of conventional constituion and address modes are stored in a pair with the instruction address and branching destination address of the branching instruction.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetch control method for an information processing device equipped with a branch destination associative memory (hereinafter simply referred to as an associative memory), and in particular, in a branch instruction that switches address modes, The present invention relates to a technique that is effective when applied to an instruction prefetch control method for an information processing device that can prevent reading of branch destination instructions due to erroneous switching.

0002

2. Description of the Related Art Conventionally, as described in Japanese Patent Laid-Open No. 59-177653, an information processing device equipped with an associative memory has been known to store the address of a branch instruction and the branch destination address of this branch instruction. There are some items that are stored as a pair in an associative memory, and are controlled to branch to a branch destination address registered in the associative memory when the instruction prefetch address and the branch instruction address registered in the associative memory match. .

For example, as shown in FIG. 4, an associative memory has an instruction address register 1 that stores an instruction prefetch address or a branch instruction address, a branch destination address register 2 that stores a branch destination address, and an instruction address and a branch destination address. an associative memory device 3 which stores the predicted branch instruction address and the predicted branch destination address in the KEY section and the DATA section respectively; an instruction address comparator 4 which compares the instruction address and the predicted branch instruction address; a predicted branch destination address register 5 that stores a predicted branch destination address when a match is reported;
The address of the predicted branch destination address register 5 is used to prefetch the branch destination instruction.

0004

However, in the prior art as described above, the address mode is not stored in the associative memory, so when the address mode is switched, the branch destination address is incorrect. There is a problem in that the instruction must be read ahead again using the correct address.

As an example, depending on the address mode, 2
The case of switching between a 4-bit address space and a 31-bit address space will be explained with reference to FIG. In this case, when the address mode value indicates “0”, 2
4-bit address space (address “00000000” ~
When the value of the address mode indicates "1", the address space is switched to a 31-bit address space (the space width of addresses "00000000" to "7FFFFFFFF").

For example, when the address mode is "0", the address "000" which is the next address after "00FFFFFF" is
When the address mode is “1”, the next address after “00FFFFFF” is “01000000” and “7FFFF” is wrapped around to address “00000”.
The data is wrapped around to address "00000000" which is the next address after address "FFF".

At this time, if the branch destination address predicted by the associative memory is "00FFFFFF", then
In the conventional technology, the address mode is not considered, so it is difficult to determine whether the next instruction to be prefetched after instruction b at address "00FFFFFF" is instruction c at address "01000000" or instruction a at address "00000000." Can not.

[0008] Suppose that using the address mode value at the time of prefetching (assumed to be "0"), "0000" is written next to instruction b.
If instruction a at address 0000 is read out, if the address mode has been switched to 1 between the time of read-ahead and the processing of the branch instruction for which the read-ahead address has been predicted, the predicted The read-ahead address was incorrect, and the correct address “010000”
It is necessary to read out the instruction c again using address 00''.

Therefore, in the conventional instruction prefetching method, there is a problem in that processing performance deteriorates due to rereading when the address mode is switched.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an instruction prefetch control method for an information processing device that can eliminate the instruction readout at an erroneous branch destination address due to address mode switching when reading an instruction using a predicted branch destination address. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0012

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

That is, the instruction prefetch control method of the information processing apparatus of the present invention includes a branch destination associative memory that stores the address of a branch instruction and the branch destination address of the branch instruction, and an address mode that is the address space width. An instruction look-ahead control method for an information processing apparatus, comprising an address mode switching means for executing an instruction, wherein the branch destination address and an address mode corresponding to the branch destination address are stored as a pair in the branch destination associative memory; When prefetching is performed, the branch destination address and the address mode are read from the branch destination associative memory, and the branch destination instruction is read using the branch destination address corresponding to the address mode.

[0014]

[Operation] According to the instruction prefetch control method of the information processing device described above, when performing instruction prefetch, the branch destination address and the address mode corresponding to this branch destination address are read from the branch destination associative memory, and the branch destination instruction is read out from the branch destination associative memory. By reading , even if the address space width is switched before the execution of a branch instruction, the address mode at the time the branch destination address was generated is referenced when prefetching an instruction using the predicted branch destination address. be able to.

[0015] Thereby, it is possible to eliminate prefetching of instructions in an incorrect address space due to address mode switching, and it is possible to prevent deterioration in processing performance due to errors in reading predicted branch destination instructions.

[0016]

[Embodiment] FIG. 1 is an overall configuration diagram showing an information processing device which is an embodiment of the instruction prefetch control method of the information processing device of the present invention, and FIG. 2 is a configuration diagram showing an associative memory in the information processing device of the present embodiment. , FIG. 3 is a configuration diagram showing an instruction unit in the information processing apparatus of this embodiment.

First, the configuration of the information processing apparatus of this embodiment will be explained with reference to FIG.

The information processing device of this embodiment is an information processing device that includes an associative memory for branch instructions and performs prefetching of instructions, and includes an associative memory (branch destination associative memory) 10 that stores branch destination information of branch instructions. and prefetching of instructions.
An instruction unit 20 for decoding, an arithmetic unit 40 for executing instructions, and a main memory 5 for storing instructions and data.
0, and signals are mainly transferred through signal lines 101 to 106.

As shown in FIG. 2, the associative memory 10 includes an instruction address register 11, a branch destination address register 12, an associative memory device 13, and an instruction address comparator 14.
In addition to the conventional configuration of the predicted branch destination address register 15, an address mode register 16 and a predicted address mode register 17, which are features of the present invention, are added, and the instruction address and branch destination address of the conventional branch instruction are It stores information with added modes. Then, the instruction address is K of the content addressable memory 13.
The branch destination address and address mode are stored in the DATA section.

The instruction address register 11 receives an IC (Instruction Count) from the instruction unit 20.
) receives an instruction prefetch address or a branch instruction address at the time of writing via the signal line 101 of the signal line 201,
The address is sent to the associative memory device 13 via 202.

The branch destination address register 12 is a register that receives a branch destination address when writing to the associative memory device 13, and receives ADDR (Address) from the instruction unit 20.
ss) receives the branch destination address via the signal line 105,
The branch destination address is stored in the content addressable memory device 1 via the signal line 204.
Send to 3.

The associative memory device 13 uses a part of the instruction address sent from the instruction address register 11 via the signal line 202 as an index address, and stores an instruction address sent from the instruction address register 11 via the signal line 201; The branch destination address sent from the branch destination address register 12 via the signal line 204 and the address mode information sent from the address mode register 16 via the signal line 203 are held in the KEY section and the DATA section, respectively. 205 to the instruction address comparator 14, a signal line 207 to the predicted branch destination address register 15, and a signal line 206 to the predicted address mode information to the predicted address mode. Send to register 17.

The instruction address comparator 14 compares the instruction address sent from the instruction address register 11 via the signal line 201 with the predicted branch instruction address read from the associative memory device 13 via the signal line 205. Then, the result is sent to the predicted branch destination address register 15 and the predicted address mode register 17 via the signal line 208.

When the instruction address comparator 14 reports a match of instruction addresses via the signal line 208, the predicted branch destination address register 15 receives the predicted branch destination address read from the associative memory device 13, and registers the PTA. (Pre
dict Target Address) signal line 1
03 to the instruction unit 20.

The address mode register 16 is a register that receives address mode information when writing to the associative memory device 13, and receives AM (Address) information from the instruction unit 20.
ss Mode) via the signal line 104, and sends the address mode information to the content addressable memory device 13 via the signal line 203.

When the instruction address comparator 14 reports a match of instruction addresses via the signal line 208, the predicted address mode register 17 receives the predicted address mode information read from the content addressable memory device 13, and registers the PAM ( P
redirect Address Mode) signal line 1
02 to the instruction unit 20.

The instruction unit 20 includes, for example, as shown in FIG. 3, instruction buffer registers 21 and 22 for temporarily storing a prefetched instruction sequence, an aligner 23 for cutting out instruction words,
An instruction counter 24 that stores the instruction address of the instruction word, an instruction register 25 that stores the instruction word, an adder 26 that adds 4 to the instruction address, a decoder 27 that decodes the instruction word, an address calculator 28 that calculates the address, and an address. an addressing circuit 29 that addresses a predicted branch destination address based on address mode information, a comparator 30 that compares the address mode and address in pairs, an addressing circuit 31 that addresses a predicted branch destination address based on predicted address mode information, and selects one of the two addresses. In addition to the address select circuit 32, which is a feature of the present invention, an address mode setting register (address mode switching means) 33 is added to determine the size of the address space.

[0028] Then, the instruction buffer registers 21 and 22
IDATA (Instruct) from main memory 50
A signal line 106 of the main memory 50 is input, and when an instruction string is transferred from the main memory 50, the instruction string is stored. In this case, the instruction buffer register 21
. is stored in the instruction buffer register 22 until the next branch instruction appears.

Furthermore, when the instruction in the instruction register 25 is decoded, the next instruction is taken out from the instruction buffer registers 21 and 22 via the aligner 23 and newly set in the instruction register 25.

Furthermore, since the instruction counter 24 stores the instruction address of the instruction word currently in the instruction register 25, its value is 4 (corresponding to the byte length of one instruction word).
The value added becomes the instruction address of the next instruction word. The aligner 23 then takes out the next command word using the signal line 305 to which the value of the command counter 24 is output. In this case, the address output from the instruction counter 24 is incremented by +4 by the adder 26, and is stored in the instruction counter 24 when the next instruction word is stored in the instruction register 25.
At the same time, it is output to the associative memory 10 via the signal line 101 of the IC.

Further, the address referred to by the instruction word in the instruction register 5 is generated by the address calculator 28, and is sent to the addressing circuit 29 using the signal line 304 for addressing. After that, the address select circuit 32
and is output to the associative memory 10 and main memory 50 via the ADDR signal line 105.

On the other hand, the address mode setting register 33 always stores information indicating the address space width in which the instruction sequence being executed exists. When the contents of the address mode setting register 33 are rewritten, the size of the address space is switched, and the address space is outputted to the content addressable memory 10 via the AM signal line 104.

The arithmetic unit 40 has the same configuration as the conventional one, is connected to the instruction unit 20 and the main memory 50, reads out data stored in the main memory 50 according to instructions from the instruction unit 20, and executes instructions. It is.

The main memory 50 has the same configuration as the conventional one, is connected to the instruction unit 20 and the arithmetic unit 40, and stores instructions and data.

Next, the operation of this embodiment will be explained.

The instruction prefetch control system of this embodiment is executed by two operations: a predictive read operation, which is a pre-operation, and a main read and predicted address verification operation, which are main operations.

First, the predictive read operation of the previous operation will be explained.

First, before the instruction unit 20 decodes the instruction, the content addressable memory 13 is searched for the instruction address. In this case, if a word containing it exists,
The branch destination address and address mode information in the word are sent to the instruction unit 20 via PAM and PTA signal lines 102 and 103, respectively.

Furthermore, the instruction unit 20 addresses the sent branch destination address using the address mode information, sends it to the main memory 50 via the ADDR signal line 105, and reads the branch destination instruction string from the main memory 50. Perform reading. In this case, the branch destination instruction sequence is input from the main memory 50 to the instruction unit 20 via the IDATA signal line 106.

Next, the pre-read and predicted address verification operations, which are the main operations, will be explained.

First, when a branch destination instruction is decoded in the instruction unit 20, the address of the branch destination instruction word is obtained, and addressing is performed using the address mode.
It is sent to the main memory 50 via the R signal line 105. Then, the branch destination instruction string is read from the main memory 50 via the IDATA signal line 106.

In this case, reading the branch destination instruction string in this operation compares the branch destination instruction address and address mode information in this operation with the predicted branch destination address and predicted address mode information in the previous operation. , is not done when the comparison matches. Further, if the comparison does not match, the branch destination instruction string in this operation is read out and the associative memory 10 is rewritten.

Next, the predictive read operation will be explained in detail.

First, an instruction sequence is read from the main memory 50 by prefetching the instructions. At this time, the instruction address is transferred to the associative memory 10 via the signal line 101 of the IC. and,
The value on the signal line 101 of the IC is the instruction address register 11
The match between the instruction addresses stored in the instruction address register 11 is then sent to the content addressable memory device 13 via the signal line 202.

Furthermore, at this address, the associative memory device 13
and reads out the address of the branch instruction stored in the corresponding KEY section and the branch destination address and address mode information stored in the DATA section. Then, the instruction address sent from the instruction address register 11 via the signal line 201 and the address of the branch instruction read from the KEY section are compared by the instruction address comparator 14, and if they match, the branch destination is predicted. holds true.

Thereafter, when the prediction is established, the branch destination address and address mode information read from the DATA section are set in the predicted branch destination address register 15 and the predicted address mode register 17, respectively, and the signal line 1 of the PTA is set.
03 and the instruction unit 20 via the PAM signal line 102.
Send to.

Further, the predicted branch destination address inputted to the instruction unit 20 is addressed by the addressing circuit 31 according to the predicted address mode information inputted at the same time. Then, the addressed predicted branch destination address is sent to the address select circuit 32 via the signal line 307.
and is sent to the main memory 50 via the ADDR signal line 105.

Thereafter, using this predicted branch destination address, a branch destination instruction string is read out from the main memory 50 via the IDATA signal line 106 and input to the instruction unit 20.

Then, in the instruction unit 20, the branch destination instruction string is stored in the free instruction buffer register 2.
1 or stored in the instruction buffer register 22.

Next, the actual readout and predicted address matching operations will be explained in detail.

The main operation in this case starts when the instruction word is stored in the instruction register 25 and decoded, and it is first checked whether the instruction in the instruction register 25 is a branch instruction. The following operation is performed only when the instruction is a branch instruction.

First, the address calculator 28 is used to find the branch destination address, and the branch destination address is sent to the addressing circuit 29 via the signal line 304, and then sent from the address mode setting register 33 via the signal line 104. Addressing is performed using the address mode information obtained.

The addressed branch destination address is sent to the address select circuit 3 via the signal line 306.
2 and sent to the main memory 50 via the ADDR signal line 105. Thereafter, the branch destination instruction string for the branch destination address is transferred to the instruction unit 20 via the IDATA signal line 106.

At this time, the branch destination address generated by the address calculator 28 and the value of the address mode setting register 33 are sent as a pair to the comparator 30 via the signal lines 304 and 104, respectively, and the PTA is A comparison is made between the predicted branch destination address via the signal line 103 and the predicted address mode information via the PAM signal line 102 as a pair.

As a result, only when they are not equal, the branch destination instruction string read from the main memory 50 via the IDATA signal line 106 is stored in the instruction buffer register 22 of the instruction unit 20. At this time, the previous operation is invalidated and the processing of the main operation is executed.

After that, the instruction address register 11, branch destination address register 12, and address mode register 16
The values of the signal lines 201 and 201, respectively, are set using a part of the instruction address sent via the signal line 202 as an index address.
It is written to the associative memory device 13 via 203 and 204.

On the other hand, when the results of the comparator 30 are equal,
The operation after this operation is not performed, and the processing of the previous operation is continued.

Therefore, according to the instruction prefetch control system of this embodiment, even if the address space width is switched before execution of a branch instruction, when prefetching an instruction at a predicted branch destination address, the branch Since the address mode at the time of generating the destination address can be referenced, prefetching of an instruction in an incorrect address space can be eliminated by switching the address mode.

[0059] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

[0060]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.

That is, when a branch destination address and an address mode corresponding to this branch destination address are stored as a pair in a branch destination associative memory and instructions are prefetched, the branch destination address and address mode are stored from the branch destination associative memory. By reading the branch destination instruction using the branch destination address that corresponds to the read address mode, even if the address space width is switched before the execution of the branch instruction, it is possible to read ahead the instruction using the predicted branch destination address. Furthermore, since the address mode at the time of generation of the branch destination address can be referred to, it is possible to eliminate prefetching of an instruction in an incorrect address space due to address mode switching.

As a result, it is possible to prevent a decrease in processing performance due to an error in reading a predicted branch destination instruction.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram showing an information processing device that is an embodiment of an instruction prefetch control method for an information processing device according to the present invention.

FIG. 2 is a configuration diagram showing an associative memory in the information processing device of the embodiment.

FIG. 3 is a configuration diagram showing an instruction unit in the information processing apparatus of the embodiment.

FIG. 4 is a configuration diagram showing an associative memory of an information processing device as an example of the conventional technology.

FIG. 5 is an explanatory diagram showing an address space of an information processing device that is an example of the conventional technology.

[Explanation of symbols]

1 Instruction address register 2 Branch destination address register 3 Content addressable memory device 4 Instruction address comparator 5 Predicted branch destination address register 10 Content addressable memory (branch destination addressable memory) 11 Instruction address register 12 Branch destination address register 13 Content addressable memory device 14 Instruction address comparison unit 15 predicted branch destination address register 16 address mode register 17 predicted address mode register 20 instruction unit 21 instruction buffer register 22 instruction buffer register 23 aligner 24 instruction counter 25 instruction register 26 adder 27 decoder 28 address calculator 29 addressing circuit 30 comparison device 31 addressing circuit 32 address select circuit 33 address mode setting register (address mode switching means) 40 arithmetic unit 50 main memory

Claims (1)

[Claims] 1. An information processing device comprising: a branch destination associative memory for storing an address of a branch instruction and a branch destination address of the branch instruction; and address mode switching means for switching an address mode, which is an address space width. In the instruction prefetch control method, the branch destination address and the address mode corresponding to the branch destination address are stored as a pair in the branch destination associative memory, and when performing instruction prefetch, the An instruction prefetch control method for an information processing apparatus, characterized in that a branch destination address and the address mode are read out, and a branch destination instruction is read out using the branch destination address corresponding to the address mode.