JPS6027418B2 - Instruction preemption control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction prefetch control device in an information processing system that employs an advanced instruction prefetch control method.

With the rapid advancement of technology for the use of modern electronic computers,
The desire to increase size and speed is increasing.

In order to achieve a balance between the speed of the main memory and the speed of the arithmetic processing unit, control methods for increasing speed include a method of overlapping each function through buffering and parallelization of the arithmetic processing unit, or a method using high-speed buffer memory. There are generally known methods for substantially increasing the speed of main storage devices by using . The instruction prefetch control method is one means of improving the arithmetic processing speed of the above-mentioned high-speed control method, and it is possible to perform each processing step from instruction presentation to execution in the processing of one instruction word as simultaneously as possible. It prefetches the command word so that it can be executed.

However, in this method, if the prefetched instruction is updated, it is necessary to rewrite it with a new instruction. In conventional devices of this type, it is technically difficult to rewrite disabled instruction words and operand words during preparation for execution, as will be explained in more detail later. In practice, the data had to be retrieved from the main memory or high-speed buffer memory again. However, since not only the invalidated instruction word but also all subsequent prefetched command words are invalidated and re-fetched, there is a drawback that the processing time of the instruction is adversely affected. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an instruction prefetching device capable of directly updating an invalidated prefetching instruction program during preparation for execution. In order to achieve the above object, the instruction prefetching device of the present invention rewrites the instruction register or instruction word buffer that holds the prefetched instruction word in its control circuit when the instruction word prefetched by the preceding instruction is rewritten. It has the function of

According to the present invention, there is provided an instruction register that stores an instruction to be executed read from the main memory or high-speed buffer memory, and an instruction that executes the instruction to be executed that has been retrieved and decoded from the instruction register and issues an output. In a processing device comprising an execution unit, an output data register, an instruction counter, and an operand address register that operate in response to the output, the contents of which are updated by the preceding instruction of a prefetched instruction, the instruction register is at least It is composed of two blocks, and is further provided with a change block designation circuit having a function of designating a vacant block from among at least two blocks according to the contents of an instruction counter, so that the preceding command is stored in the main memory or in a high-speed buffer. In response to an operation that changes the contents of memory, the contents of the operand address register of the preceding instruction and the contents of the instruction counter are used to instruct the contents of the instruction register to change and specify the change effective block in the instruction register. An instruction prefetch control device is obtained that allows only blocks that have been received to be replaced by the contents of the output data register. Next, a detailed description will be given with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a slave instruction prefetch control device and a main storage device.

First, let me explain the names of each block. 1 1 is the main memory or high-speed buffer memory, 1 "2 and 1
3 is a buffer register, 14 to 16 are instruction registers, 1
7 and 18 indicate data registers, and 19 and 2 operand address registers, respectively. 12 to 20 surrounded by broken lines constitute an instruction prefetching section 21. 2
Reference numeral 2 denotes an instruction read control section, which is paired with an instruction prefetch section 21 to form a prefetch control section.

Furthermore, 24 is an instruction execution unit, 25 is an associative memory or comparator, 216 is an instruction counter (working register), and 28
indicate address switching circuits, respectively. Yet another 29
and 30 indicate an input data register and an output data register, respectively, and 24 to 30 roughly constitute an arithmetic unit. In the prefetch control system having the above configuration, the prefetch control units 21 to 22 execute the instruction word following the instruction and the operand word of the instruction decoded from this instruction word in parallel with the execution of the instruction in the calculation units 24 to 30. Preparation for execution of the instruction is made in advance by fetching it from the main storage device or high-speed buffer memory, and immediately after the preceding instruction has been executed in the calculation units 24 to 30, the next instruction is passed from the prefetch control unit 21 to 22 to the calculation unit. . At this time, the number of prefetches is determined in relation to the fetching from the main memory or high-speed buffer memory 11. In general, if the prefetch control is faster than the main memory or high-speed buffer memory 11, the number of prefetches can be increased, but the number of prefetch times does not affect the actual processing speed. Stay within range. By the way, in this method, the preemption control unit 21-2
2 and the arithmetic units 24 to 30' are operating simultaneously, and when the instruction currently being executed in the arithmetic unit is a store instruction, if an instruction prefetch control method that increases the number of prefetch words is adopted, There is a high probability that the contents of the prefetched instruction word or operand word will be changed, and if the contents of the prefetched instruction word or operand word are actually changed, the contents of the prefetched instruction word or operand word become obsolete and cannot be used.

In order to solve this inconvenience, the preemption control unit 21-22
Then, the address of the prefetched instruction word or operand word is added to the associative memory 26 with an index that distinguishes the instruction word and the operand word.
When there is a write request from the arithmetic unit to the main memory, a check is made to see if the write address matches the address held by pre-fetching. If a match occurs, the prefetch word corresponding to that address is invalidated and the memory is stored in the main memory or high-speed buffer memory 1 again.
Take it out from 1. That is, when a match is detected in the instruction word, all the prefetched instruction words of the matching instruction word are invalidated, and the instruction words are read out from the main memory device or the high speed buffer memory 11 again from the matching address. Only the matched operand words are retrieved again. FIG. 2 shows a state in which the prefetched instruction/word or operand word in the above description becomes invalid if its contents are changed by a preceding store instruction.

Here, symbols 1 to 4 in the figure represent an instruction register read cycle, an instruction decode cycle, an operand logic cycle, and an instruction execution cycle, respectively.
However, the above-mentioned solutions for updating these invalidated instructions are by no means desirable. One reason is that the only instruction that should be invalidated in this button is instruction ○ in the case of Figure 2, but in reality all subsequent instructions up to G are invalidated, so there is no use in the extraction method. , Second, extra time is required for re-fetching from the main memory or high-speed buffer memory 11, and this time is compared to the processing time when re-reading the instruction execution unit is not required. This is quite large, and therefore these two causes have the disadvantage of reducing the overall speed of the device. The above-mentioned drawbacks could be overcome if the contents of the invalidated instruction words could be updated at the execution preparation stage, but this is practically difficult to achieve with the conventional approach.

One reason is that instruction words are generally decoded for each instruction using prefetch control to prepare for instruction execution, so changes at this stage are technically complex.
This is because in order to realize this, the number of logic gates in the device increases considerably. Particularly when there are many prefetch steps, for example in the case of Figure 1, the number of prefetch steps that advance to the execution preparation stage may exceed 10, but the number of logic gates required to realize it is enormous. Therefore, it is difficult to realize it practically. Therefore, in the past, despite the above-mentioned drawbacks, a method was sought in which the instructions that were prefetched and became invalid were retrieved again from the main memory or high-speed buffer memory. .

Note that the above explanation has focused on instruction words, and since operations such as decoding are not required for operand words, this does not pose much of a problem. FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention.

In this device, an instruction word is stored in an instruction register 32 from a main memory device or a high-speed buffer memory 11 through a changeover switch 31. However, this operation must be executed before the instruction is executed by the instruction execution unit 24. When another instruction is executed by the instruction execution unit 24, the instruction reading control unit 22 has the instruction next to this executed instruction read from the instruction register 32 and decoded.
The decoded signal is then sent to the instruction execution unit 22 through the signal line 221. The instruction execution section receives the sent instruction when the instruction being executed is completed. At this time, the instruction counter 26 updates the contents of the counter through signal lines 261 and 241. The lower four bits of the instruction counter 26 are sent to the instruction register 32 through the signal line 262 in order to read the next instruction to be decoded with the updated contents. The instruction register 32 is formed of four blocks, and when one instruction ends in the instruction execution unit 24, the empty condition of the instruction register 32 is checked, and if two blocks out of the four blocks are empty, a signal is sent. A write command is sent to the instruction read control unit 22 through the line 242, and at the same time, the operand address register 27 is sent through the signal line 243.
Send the address for reading the command word to the signal line 2.
71 to the main memory or high-speed buffer memory 11
A request for issuing an order is issued through the unillustrated line x1x.

When two blocks of instruction words are retrieved from the main storage device or high-speed buffer memory in accordance with this operation, a signal 222 from the instruction read control unit 22 is sent through the changeover switch 31.
The instruction word is stored in a predetermined block. In this way, instruction prefetch control is performed by checking the empty space of the instruction register 32 in the instruction execution section 24 at the same time as the execution of the instruction. Next, execution of a command while performing prefetch control will be further explained.

When the instruction that has been decoded by the instruction read control unit 22 and sent to the instruction execution unit 24 is an instruction to issue to the main storage device 11, the instruction execution unit 24 immediately sends a read address to the operand address register 27 through the signal line 243. , and further issues a request to the main storage device or high-speed buffer memory 11. At this time, if the requested data is available in the high-speed buffer memory 11, the proposed data enters the input register 29 through the signal line 111 in one cycle. The data is then sent to the instruction execution unit 24 via a signal line 291 and stored in a predetermined general-purpose register (not shown). When the instruction execution section 24 receives a decoded instruction, the instruction counter 26 outputs signals to the signal lines 261 and 24 by the instruction execution section 24.
1 to update the contents of the instruction counter itself. Further, the read address of the instruction register 32 is passed through the lower 4 bit signal line 262 of the instruction counter 26. When the contents of the instruction counter 26 are updated, the next instruction to be executed is sent from the instruction register 31 to the instruction read control unit 22 through the signal line 311, decoded here, and sent to the instruction execution unit 24 as a result of the decoding. Finish preparing to pass.
This is one cycle of instruction execution. Next, the instruction control unit 2
When the above instruction decoded by 2 and sent to the instruction execution unit 24 is a store instruction to the main memory 11, the write address is sent to the address register 27 through the signal line 243.
The write data is sent to the output data register 30' via the signal line 244.

After that, the write address and write data are sent to the signal line 271.
x and 301Y and then sent to the main storage device 11.
At this time, the contents of the operand address register 27 and the contents of the instruction counter 26 are compared by a comparator 33. If a match between the two contents is detected by this comparison, a part of the instruction fetched in advance into the instruction register 32 becomes invalid. Conventionally, it was difficult to update this invalidated data, so it was further removed from the main storage device or high-speed buffer memory 11, but in the present invention, this is done as follows.

That is, in the present invention, when the comparator 33 compares addresses corresponding to four blocks of addresses in the instruction register 32, that is, addresses excluding the lower 4 bits of the instruction counter 26 and the operand address register 27, and they match, the signal line is A signal is sent to the instruction execution unit 24, instruction read control unit 22, and changeover switch 31 through 331, 332, and 333. Up until now, we have not discussed the structure of each address individually, but we will explain it all together next. FIG. 4 shows the structure of the above address. The read address of the instruction register 32 is made up of the lower 4 bits excluding the least significant bit, and the write address is made up of each block. Each block consists of an address excluding the lower two bits. However, when writing to the instruction register 32, in this embodiment, two blocks of instruction words read from the main storage device or high-speed buffer memory 11 are treated as one write operation. The comparison in the comparator 33 described above is performed using addresses excluding the lower 4 bits, and the upper 2 bits of the lower 4 bits are used to control the instruction issuing control section 22. Note that each bit is expressed in binary. Here, when the aforementioned comparator 33 detects a match, the 3
To explain the two signals, a signal outputted to the signal line 333 is used to switch the write data (instruction word) from the main storage device or high-speed buffer memory 11 side to the output data register 30 side at the changeover switch 31, and the signal outputted to the signal line 332 The output signals are for sending the instruction register 32 change request signal and the block address to be changed, that is, the upper 2 bits of the lower 4 bits of the address register 26 (see FIG. 4) to the instruction output control unit 22. Signal line 33
The signal outputted from 1 is a coincidence report signal to the instruction execution section 24, and is passed from the instruction output control section 22 to the instruction execution section 24 via the signal line 2.
The decode signal sent through the instruction register 32 is made invalid until the modification of the instruction register 32 is completed.

The signal sent to the signal line 262 as the output of the instruction counter 26 becomes the various addresses of the instruction register 32, and is also sent to the change block designation circuit 34 to designate a change effective block. FIG. 5 shows the above change effective block designation circuit 34.
This is a diagram showing an example in detail, in which the upper first and second two bits of the four bits used for the read address of the instruction register described earlier and shown in FIG. 4 are expressed in binary. The configuration is such that a signal specifying any one of the first to fourth blocks is generated by the following.

FIG. 6 shows the blocks specified by the above configuration, and when the instruction counter indicates the position of the black triangle mark in the figure, the shaded area is specified as a valid block. This example shows two cases.

A change valid block designation signal having such characteristics is sent to the instruction logical output control unit 22 through the signal line 341, and is sent through the signal line 222 together with the change request signal and the change block address from the signal line 332 described above. It is sent to the instruction register 32. At this time, the changeover switch 31 has switched the data to be written to the instruction register 32 via the signal line 333, that is, the instruction word, to the output data register 30 side as described above, so the write data is passed from the signal line 301 to the signal line 311. The instruction register 32 is written to the block to be changed. When writing is completed, a write end signal is sent to the instruction execution unit 2 through the signal line 221.
4, the decoded signal for executing the next instruction becomes valid in the instruction execution unit 24 through the signal line 242,
Execution of the command begins. FIG. 7 shows that in the apparatus of the present invention described above, the instruction word prefetched into the instruction register 32 is
3 is a diagram showing a state changed by a preceding store instruction executed by an instruction execution unit 24. FIG.

In this case, unlike the case of the conventional device shown in FIG. can be made movable. However, despite these advantages, the main difference from conventional devices is only the addition of a change effective block designation circuit, and the addition of this circuit requires only slight changes in other circuits. It is enough. In the above embodiment, the instruction register 32 is made up of four blocks, but this is just an example, and any number of blocks may be used as long as there are two or more blocks. The number and the number of change effective block designation circuits may be set according to the number of blocks.

As explained above, according to the instruction prefetch control device of the present invention, in the instruction execution preparation stage, the prefetched instruction words are neither invalidated nor re-fetched to the main memory. It is possible to deal with instruction updates, and the actual processing speed of instructions can be further increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a conventional instruction prefetch control device together with a main memory, and FIG. 2 is a block diagram showing an example of the configuration of a conventional instruction prefetch control device, and FIG. FIG. 3 is a block diagram showing the implementation of the instruction prefetch control device of the present invention.
FIG. 4 is a diagram showing an example of the address structure in the present invention, FIG. 5 is a diagram showing an example of a change effective block designation circuit used in the device of the present invention, and FIG. FIG. 7 is a diagram showing a state in which a prefetched instruction word is changed by a preceding store instruction in the apparatus of the present invention. Explanation of symbols: 11 is the main storage device or high-speed buffer memory, 22 is the instruction issuing control section, 24 is the instruction execution section, 26 is the instruction counter, 27 is the operand address register, 2
9 is an input data register, 30 is an output data register,
31 is a switching circuit, 32 is an instruction register, 33 is a ratio, and 34 is a change effective block designation circuit. Figure 1 Figure 2 Figure 3 Younger brother Figure 5 Figure 7 Figure 6

Claims (1)

[Claims] 1: an instruction register that stores an instruction to be executed read from the main storage device or high-speed buffer memory; an instruction execution unit that executes the instruction to be executed that has been read and decoded from the instruction register and issues an output; A processing device comprising an output data register, an instruction counter, and an operand address register that operate in response to a prefetched instruction, the contents of which are updated by a preceding instruction, wherein the instruction register is composed of at least two blocks. and further comprising a change block designation circuit having a function of designating a vacant block from among the at least two blocks according to the contents of the instruction counter, wherein the preceding instruction is stored in the main storage device or the high-speed buffer memory. Depending on the action of changing the contents of
Based on the contents of the operand address register of the preceding instruction and the contents of the instruction counter, an instruction to change the contents of the instruction register and a change effective block in the instruction register are specified, and only the specified block is specified. An instruction prefetch control device that allows replacing the output data register with the contents of the output data register.