JP2542565B2 - Branch predictive control method - Google Patents

Description

The present invention relates to a branch prediction control method for increasing the speed of branch instructions.

[Conventional technology]

As a technique for speeding up a branch instruction, there is a method of storing a history of the branch instruction and predicting whether the branch is successful or unsuccessful and the branch destination based on the past result. (For example, IEEE COMPUTER 1984 January issue
P6 to P22) [Problems to be solved by the invention] In the above-described branch prediction, a branch history buffer for holding an instruction word address including a branch instruction and a branch destination address of the branch instruction is provided, When the instruction includes a branch instruction, the branch destination address is obtained. On the other hand, the branch success / failure of the branch instruction can be known only when the branch instruction is executed. Therefore, until that time, it is necessary to hold the address of the branch instruction and the branch destination address.
The hardware for holding these is required, and there is a drawback that the amount of hardware increases.

[Means for solving problems]

In the branch prediction control method of the present invention, the instruction word address register that holds the range of the prefetched instruction word address for detecting the rewriting of the prefetched instruction word is shared with the register for holding the write address to the branch history buffer. .

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention is such that a virtual address register 1 for storing a virtual address given from the outside, an address from this register 1 and an address of a fetch instruction address register (L) 10 are "1". Switching circuit that selects and outputs either one of the
A branch history buffer (K) 3 for storing the address of the branch instruction at the position designated by the lower bit of the output from the switching circuit 2, and a branch history buffer for holding the branch destination address at the position designated by the lower bit. (D) 4, a comparison circuit 5 for comparing the contents of the branch history buffer (K) 3 with the address from the register 1, and
6, a switching circuit 7 for selectively outputting the output of the branch history buffer (D) 4 in response to the match detection of either one of the comparison circuits 5 and 6, a store instruction for holding a write address to the memory by the store instruction Address register 8, fetch instruction address register (U) 9 that holds the upper limit address of the fetched instruction address range, fetch instruction address register (L) 10 that holds at least one set of the lower limit address of this address range A counter 11 for adding "1" to the contents of the register 10, a comparison circuit 12 for comparing the address from the register 8 and the address from the register 9, an address from the register 8 and an address from the register 10. It is composed of a comparison circuit 13 for comparison, and an AND gate 14 which takes the logical product of the outputs of these comparison circuits 12 and 13.

The register 10 may be composed of a register file.

 Next, the operation of the embodiment of the present invention will be described in detail.

Referring to FIG. 2, the virtual address of the instruction word calculated in the instruction word address conversion cycle (AI) is sent to the cache memory (not shown) and at the same time, stored in the virtual address register 1 at the end of this AI cycle. To be done. Then, in the address translation cycle (PI) for fetching the instruction word, the branch history buffer (K) 3 and the branch history buffer (D) 4 are indexed.

The branch history buffer (K) 3 and the branch history buffer (D) 4 have the same structure as a well-known two-level set associative cache memory. The branch history buffer (K) 3 stores the upper part of the instruction address of the branch instruction and the valid bit indicating its effectiveness as the index key data. Branch history buffer (D) 4
Holds the branch destination address corresponding to the branch instruction held in each entry of the branch history buffer (K) 3.

In this embodiment, the fetch instruction registers 9 and 10 have three sets of registers. This makes it possible to prefetch three sets of instruction streams including a maximum of two branch instructions.

First, when nothing is registered in the branch history buffer (K) 3 and the branch history buffer (D) 4, the registration process is performed as follows according to the execution of the branch instruction.

When the branch instruction is an unconditional branch instruction or a conditional branch instruction and the branch is made, the instruction address of this branch instruction is stored in the branch history buffer (K) 3 and the branch destination address is stored in the branch history buffer (D) 4. Second each
It is registered in the E cycle of instruction execution shown in the figure. For this registration, out of the fetch instruction address register (L) 10,
The contents of the entry holding the instruction address being executed and the contents of the other entry holding the branch destination address are used. That is, when executing a branch instruction that has not hit the branch history buffer (K) 3 and the branch history buffer (D) 4, the branch destination address of the branch instruction is determined in the A cycle of this branch instruction. This branch destination address is set in the virtual address register 1. This address is set in the other fetch instruction address registers 9 and 10 as the instruction address of the new stream. One clock before the E cycle of this branch instruction,
The instruction address being executed is transferred from the fetched instruction address register (L) 10 to the virtual address register 1. Then, when it is decided to branch in the E cycle of this branch instruction, the branch instruction address from the virtual address register 1 is registered in the corresponding entry of the branch history buffer (K) 3, and the branch history buffer (D) 4 is registered. The branch destination address of the fetch instruction address register (L) 10 is registered in the corresponding entry of.

At this time, the level of the branch history buffer having two levels to be set depends on a well-known replacement algorithm.

Next, in the state registered in the branch history buffer (K) 3 and the branch history buffer (D) 4, the following processing is performed according to the execution of the branch instruction.

The match of the branch history buffer (K) 3 indexed by the contents of the virtual address register 1 indicates the comparison circuit 5 or 6.
Then, the switching circuit 7 selects the level of the branch history buffer (D) 4 for which the comparison circuit 5 or 6 detects a match. If the corresponding valid bit indicates "valid", the output of the switching circuit 7 is sent together with the branch prediction hit signal as a branch prediction address for the branch destination instruction fetch access of the cache memory. By fetching an instruction using this branch predicted address output, the fetching of the branch target instruction word is accelerated, and the branch instruction is executed at high speed.

Next, the contents already registered in the branch history buffers 3 and 4 became invalid due to the fact that the instruction was rewritten so that it was no longer a branch instruction, the branch destination address was changed, the branch direction was changed, etc. In this case, a branch prediction failure is detected in the E cycle of the branch instruction.
As a result, the validity indication bit (vari bit) in the branch history buffer (K) 3 is reset, and the corresponding entry becomes invalid.

However, for the DO loop control branch instruction used in a FORTRAN program, etc., since the same loop may be used many times, the corresponding entry is not invalidated even if the branch prediction fails. . That is,
Branch prediction always fails when exiting the DO loop,
At this time, if the corresponding entry in the branch history buffer is invalidated every time, the branch prediction will fail even when this loop is used again, and the performance will deteriorate.

Next, the operation of the fetch instruction address registers 9 and 10 will be described.

The fetched instruction address register 9 holds the final address of the fetched instruction, and the fetched instruction address register 10 holds the start address of the instruction not executed among the fetched instructions. Therefore, the instruction in the address area sandwiched between the fetched instruction address registers 9 and 10 is the fetched instruction and the unexecuted instruction. In order to retain the range of this fetch instruction, the fetch instruction address register 10 is set to "1" via the counter 11 after each instruction is executed.
Incremented. Further, the fetched instruction address register 9 is updated to hold the final address of the fetched instruction at the time of fetching the instruction. By thus managing the fetch instruction address registers 9 and 10, the comparison circuits 12 and 13 compare with the store address to detect that writing has occurred in the range. When the rewriting is detected, the process is restarted from the instruction re-fetching. The instruction buffer for holding the fetched instruction and fetched instruction address registers 9 and 10 have three sets as described above, and each control stream has a control bit (valid bit) indicating whether or not it is in use. This manages whether the fetch of the branch destination instruction can be continuously executed or whether the fetch instruction address registers 9 and 10 must wait for a vacancy.

As a result, it can be determined that the first instruction is fetched if this valid bit indicates that it is not used, and that the subsequent instruction is fetched if this valid bit indicates that it is in use. At the time of fetching the first instruction at the branch destination, instruction addresses are set in both the fetch instruction address registers 9 and 10, but at the second and subsequent instruction fetches, only the fetch instruction address register 9 is set.

Referring to FIG. 2, the performance at the time of branch prediction is compared with the conventional method. When the branch prediction is successful, the branch instruction execution time is significantly improved. In the conventional method, branch success / failure is determined in the operation cycle of the conditional branch instruction. If the branch is successful, the address calculation cycle of the branch target instruction starts from the next cycle, and therefore four machine cycles are required from the completion of execution of the branch instruction (end of E cycle) to the end of E cycle of the branch target instruction. On the other hand, when branch prediction is performed, the branch prediction buffer is indexed in the fetch instruction PI cycle of the branch instruction, whereby the branch destination address can be obtained when the fetched instruction includes the branch instruction of the branch success prediction. The branch destination instruction is fetched and decoded using this address, and the branch destination instruction is executed in the cycle next to the E cycle of the branch instruction. The execution time of the branch instruction is four times faster.

〔The invention's effect〕

According to the present invention, the instruction word address register that holds the range of the prefetched instruction word address for detecting the rewriting of the prefetched instruction word is shared with the register for holding the write address to the branch prediction buffer to reduce the amount of hardware. We are also working to improve performance.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the effect of branch prediction. 1 and 2, 1 ... Virtual address register, 2, 7 ... Switching circuit, 3 ... Branch prediction buffer (K), 4 ... Branch prediction buffer (D), 5, 6, 12, 13…
Comparator circuit, 8 ... Store address register, 9 ... Extraction instruction address register (U), 10 ... Extraction instruction address register (L), 11 ... Counter.

Claims (2)

(57) [Claims] 1. A branch history buffer holding a plurality of pairs of a branch instruction address and a branch destination address of the branch instruction for prefetching a branch destination instruction word of a branch instruction, and the most recently prefetched. A prefetch instruction word having a first register group for storing the address of the instruction word and a second register group for storing the address of the instruction word previously prefetched, and detecting occurrence of rewriting of the prefetched instruction word Rewriting detection means, wherein the first register of the second register group stores the address of the instruction word currently being executed, and the second register of the second register group stores the branch destination address. If the address of the stored and prefetched branch instruction is not held in the branch history buffer, the contents of the first register of the second register group are stored when the branch instruction is executed. Registered in Toki history buffer as the address of the branch instruction, the branch prediction control scheme in which a content of the second register of the second register group and registers as a branch destination address in the branch history buffer. 2. When the branch prediction of a branch instruction is unsuccessful, the branch history buffer further comprises invalidating means for invalidating the contents of the entry corresponding to the branch instruction, and the invalidating means is for loop control. 2. The branch prediction control method according to claim 1, wherein when the branch prediction of the branch instruction is failed, the contents of the corresponding entry in the branch history buffer are not invalidated.