JPH03177926A - Information processor - Google Patents

Abstract

PURPOSE:To omit the unnecessary prefetching operations by checking an un matched state based on the information received from a branch estimation table at the time point when an instruction is read out of an instruction cache and feeding the checking result back to the immediately subsequent instruction prefetching operation. CONSTITUTION:The contents are read out of an instruction cache 3 and a branch estimation table 4 in parallel with each other with an index obtained via an address received from a register 1 which holds the address of a prefetched instruction. Then plural instructions given from the cache 3 are decoded by a decoder 5 to undergo the decision whether they are equal to the branch instructions or not. A selector 6 selects one of these deciding results based on the contents pointed by the bits 29 and 30 of a branch instruction address part 41. The selected result is given to a control circuit 15, and the circuit 15 performs a fetching operation based on the branching destination address received from the table 4 only when the instruction shown by the contents of the part 41 is equal to a branch instruction. If not, the estimation is neglected. Thus it is possible to prevent the deterioration of performance due to the unnecessary prefetching operations.

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a branch prediction table for executing branch instructions at high speed.

BACKGROUND OF THE INVENTION In recent years, an instruction prefetching method using a branch prediction table has been adopted as a method for prefetching instructions from memory prior to instruction execution. This technique is used for high-speed processing of branch instructions, and details of this technique can be found in US Pat.
, 559, 1.83 and JP-A-59-9155.
Reference may be made to Publication No. 2.

Generally, a branch prediction table is a table that holds a set of execution results for one branch instruction, that is, a branch direction, a branch destination address when the branch is taken, and the address of the branch instruction. When the same branch instruction is executed next time, it is predicted that the branch will be executed in the same direction and address as in the previous execution, and that information is acquired by indexing the branch prediction table when the instruction is prefetched. The instruction preemption direction is determined based on .

At this time, in addition to branch prediction failure, there is a case where the actual instruction execution order and the prediction δ-1 of the branch prediction table become inconsistent due to the following factors.

When the instruction word is rewritten or the address space is switched in the virtual memory space, the branch flu table predicts a mismatch even though the instruction is not a branch instruction. Or, the address of the branch instruction indicated by the contents of the branch prediction table does not point to the beginning of the instruction word.

This is the case.

Conventionally, such problems have been dealt with as follows.

The first solution is to have a copy of the branch prediction table, and every time a rewrite occurs, the copy of the branch prediction table is indexed, and when the instruction word corresponding to the branch prediction table is rewritten, the corresponding entry is It is deleted from the child 71111 table.

However, this method has the disadvantage of increasing the amount of hardware because it requires a copy of the branch prediction table.

The second method is to check whether the change in the instruction sequence preempted by the contents of the branch prediction table is due to an actual branch instruction, after arranging the actual instructions in the order of execution. .

In this method, an instruction word read from an instruction cache is temporarily stored in an instruction buffer, and then given to an instruction register via an instruction alignment circuit, and then decoded by a decoder to determine whether it is a branch instruction. There is. This decoding confirms that the change in the instruction sequence was indeed made by a branch instruction.

However, in the method of detecting a mismatch in an instruction sequence based on the storage state in an instruction register, the subsequent prefetched instruction word has already been stored in the instruction buffer when a mismatch is detected. Therefore, the stored subsequent prefetching instruction word must be canceled, and there is a drawback that performance is degraded due to excessive prefetching.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an information processing apparatus that eliminates the above-mentioned performance drawback by not prefetching unnecessary instructions.

Structure of the Invention According to the present invention, the address and prefix 71[1
A branch 71 that stores the branch destination addresses that are set to 1 in pairs.
P1 table means, instruction cache memory means for storing at least a part of a copy of the instruction word stored in the main memory, and branch δP1 table means for decoding the operation code of the instruction word stored in the instruction cache memory means. 111 determination means for determining whether the instruction word indicated by the intra-word address of is a branch instruction; means for ignoring said branch prediction table means when it is determined that said branch prediction table means; An information processing apparatus characterized in that the information processing apparatus includes means for invalidating the contents of the instruction prefetching buffer means and retrieving the instruction word when a contradiction occurs between the delimitation of the instruction word from the buffer means and the prediction pointer. Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention includes a prefetched instruction address register 1 that holds the address of a prefetched instruction.
, an address adder circuit 2 that increases the contents of this register 1 by 8.
, an instruction cache 3 for reading out a copy of the instruction stored in the main memory from the position specified by the address of the instruction address register 1, a branch prediction address section 41 for a branch instruction, and a branch destination address section 42 for the branch instruction. table 4
, a decoder 5 that decodes the instruction given from the instruction cache 3, a selector 6 that selects the output of this decoder 5 by the address bits (2 and 30) of the address section 41 of the branch instruction, an instruction from the instruction cache 3, and a branch prediction. an instruction buffer 7 for storing a pre-11P1 pointer and a validity bit from table 4; an instruction alignment circuit 8 for aligning the bits of the instruction from this instruction buffer 7; an instruction aligned by this instruction alignment circuit 8, a prediction pointer and a validity bit; This instruction register 9 stores the gender bit.
Detects a discrepancy between the instruction word delimiter and the pre-APL pointer as an inconsistency based on the instruction code and prediction bit from the instruction buffer 7, and displays the validity bit corresponding to the instruction word prefetched in the instruction buffer 7 as invalid. A detection circuit 10, an address generation circuit 11 that generates an address based on the contents of the instruction register 9 and the contents of the mismatch detection circuit 10, a real address register 12 that holds the address generated by this address generation LliJ path 11, and this real An operand cache 13 that reads an operand from a position specified by an address from an address register 12, an arithmetic circuit 14 that executes an operation using the operand from this operand cache 13, a selector 6, and a mismatch detection circuit 10.
The control circuit 15 controls the contents of the instruction address register 1 based on the output of the instruction address register 1.

Next, the operation of one embodiment of the present invention will be explained in detail.

Instruction register 1 stores the start address for instruction fetch given from line 16. After this, the control circuit 15
Regarding subsequent instruction fetches, it is determined whether to perform address sequential fetching according to instructions from the branch prediction table 4 or according to the contents of the branch destination address field 42. That is, the address from register 1 indexes instruction cache 3 and branch prediction table 4.

With this index, the branch instruction address section 41 of table 4
When the address and the index address match, the control circuit 15 recognizes from the signal from the line 19 that the instruction stored in the register 1 is a branch instruction, and transfers the branch destination address to the register via the line 2o. Store in 1. If line 1
When no match is given via 9, the control circuit 15
controls the address addition circuit 2 to add the contents of the register 1.

The first mismatch detection of branch prediction tables, which is one of the features of the present invention, is performed as follows.

Contents are read in parallel from the instruction cache 3 and branch prediction table 4 using the above-mentioned index. A plurality of instructions from the instruction cache 3 are H-readed by a decoder 5 to determine whether or not they are branch instructions. The selector 6 selects one of these determination results according to the content indicated by bits (29, 30) of the address section 41 of the branch instruction. The control circuit 15, which is given this selection result via the line 21, performs a fetch using the branch destination address from the branch prediction table 4 only when the instruction indicated by the contents of the address field 41 in the table 4 is a branch instruction. , and ignores the prediction unless it is a branch instruction.

The second branch prediction table, which is another feature of the present invention,
Inconsistency detection is performed as follows. Next, the instruction read from the instruction cache 3 is stored in the instruction buffer 7. When a branch instruction is included in the stored instruction word, the address (29, 30) of the branch instruction output from the branch prediction table 4 is also entered as a predicted pointer for the address within the word of the branch instruction. This prediction pointer indicates that the instruction indicated by the pointer value of the instruction word stored in the instruction buffer 7 is a branch instruction.

When the instruction can be supplied, the instruction is stored from the instruction buffer 7 via the instruction alignment circuit 8, and the prediction pointer and validity bit are stored in the instruction register 9. At this time, there may be a case where a contradiction occurs between the instruction word delimiter and the value of the pre-IIPJ pointer. This mismatch detection circuit 1
Detected at 0 via line 22, the instruction word already prefetched into the instruction buffer 6 is canceled. Thereafter, the address generator 11 is activated again by a signal via line 23, and the instruction following the branch instruction is fetched.

That is, the address generating circuit 9 generates the subsequent address of the branch instruction, and the generated address is stored in the address register via the real address register 12 and line 16. A subsequent instruction is indexed, read out, and fetched by the address of address register l.

Effects of the Invention According to the present invention, based on the information from the branch prediction table 4 when instructions are continuously issued from the instruction cache 3, inconsistencies are first checked simply and the results are fed back to the immediately following instruction prefetch. This has the effect of eliminating the need for unnecessary pre-emption.

In a case where this detection fails, for example, in a case where the part is not the pointer or OP code indicated by the branch prediction table 4, but happens to be the OP code of a branch instruction, the instruction register 9, which is actually aligned with the instructions, Check the OP code again. If such a case of inconsistency is detected, the subsequent instructions prefetched into the instruction buffer 7 will be canceled and the instruction prefetching will have to be repeated again. However, such cases are considered to be extremely rare.

With the above-described configuration, the present invention can detect cases of mismatch between the branch prediction table and actual instruction prefetch in the branch prediction aIIJ method using relatively little hardware, and can minimize unnecessary prefetching to avoid branching. This has the effect of not damaging the prediction results.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. Explanation of symbols of main parts 1...Instruction prefetch address register 2...
・Address addition circuit 3...Branch cache 4...Branch prediction table 7...Instruction buffer 8...Instruction alignment circuit 10...None Matching detection circuit 11 Address generation circuit 3 Oblong cache 4 Arithmetic circuit 5 Control circuit 1 Branch instruction Address part 2...Branch destination address part

Claims (1)

[Claims] (1) branch prediction table means for storing a branch instruction address and a predicted branch destination address in pairs; instruction cache memory means for storing at least a portion of a copy of an instruction word stored in main memory; determining means for decoding the operation code of the instruction word stored in the instruction cache memory means and determining whether or not the instruction word indicated by the intra-word address of the branch prediction table means is a branch instruction; means for ignoring the branch prediction table means when it is determined that the read instruction word is not a branch prediction target instruction of the branch prediction table means; and the instruction word read from the instruction cache memory means and the branch prediction table. When a discrepancy occurs between an instruction prefetch buffer means for storing a prediction pointer from the instruction prefetch buffer means and the instruction word delimiter from the instruction prefetch buffer means and the prediction pointer, the contents of the instruction prefetch buffer means are invalidated and the instruction is read again. An information processing device comprising: means for extracting words.