JP2540959B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that executes instructions at high speed using a cache memory.

[Conventional technology]

An information processing apparatus such as a computer generally stores instructions to be executed in a main storage device. In the central processing unit, instructions are sequentially read from the main memory, the instructions are decoded, the execution address is read, the processing is executed, and the result is stored in the execution address.

In such an information processing apparatus, a central processing unit that executes instructions is accelerated by a logic circuit such as a large scale integrated circuit. On the other hand, although the recording capacity of the main storage device in which the instruction is stored is increasing, the speed of accessing the instruction is lower than that of the central processing unit. Therefore, even if the central processing unit is speeded up, the processing speed of the information processing apparatus is limited to the processing speed of the main storage device.

In order to solve such a problem, there is an information processing device in which a high speed cache memory is arranged between a main storage device and a central processing unit. Since the cache memory is generally expensive and has a smaller capacity than the main memory, it is a memory that can be accessed at a sufficiently high speed as compared with the central processing unit. The addresses of instructions and data read from the main memory in a limited time according to a general program are
It is highly likely that they exist in a certain range in close proximity. Therefore, a part of the main storage area required at a certain time is sufficient. Therefore, some of the required instructions and data are stored in a cache memory capable of high-speed processing to apparently speed up access to the main storage device.

A decode information cache has been proposed to enable higher speed processing. This achieves speeding up of the processing by appropriately omitting the time for decoding the instruction read from the main storage device into a form necessary for the operation of the instruction execution unit. That is, the decoded instructions are stored in the cache memory in the central processing unit,
If the next instruction is in the cache memory, it is not decoded and the already decoded instruction is used. The decode information cache is particularly effective when the time required for decoding becomes longer as the instructions become more complicated than the execution of the instructions.

In a central processing unit that has a decode information cache,
If an instruction already exists in the decode information cache when the instruction is executed, the instruction is not accessed from the main memory and the decoding need not be performed, so that the instruction can be executed at high speed.

[Problems to be Solved by the Invention]

However, when an instruction is executed, it is often necessary to calculate the execution address that stores the information required by the instruction and the execution address that saves the execution result of the instruction, and then read or write data from this execution address. appear.
This calculation of the execution address may involve reading of the main storage device or reading of the register in the central processing unit, and thus it may not be possible to perform it at high speed. For this reason, there are cases where it becomes an obstacle to high-speed processing of the information processing apparatus.

Then, the objective of this invention is providing the information processing apparatus which can process at a higher speed.

[Means for solving the problem]

An information processing apparatus according to the present invention includes a main storage device that stores an instruction to be executed and data required to execute the instruction, an instruction reading unit that sequentially reads the instructions to be executed from the main storage device, and an instruction reading unit that reads the instruction. Corresponding to the instruction read by the instruction reading unit, the decoding unit for decoding the instruction read by the instruction reading unit, the execution address calculating unit for obtaining the execution address of the data on the main memory necessary for executing the instruction read by the instruction reading unit, A first memory for storing the decoding information output from the decoding means; and a second memory for storing the execution address output from the execution address calculation means and a flag indicating whether the execution address is valid or invalid. Output of decoding means provided and decoding means when the instruction to be executed is not stored in this decoding information cache First writing means for storing the code information in the first memory and the execution address output from the execution address calculating means in the second memory, and setting the flag to a value indicating that the execution address is valid; When the instruction to be executed is not stored in the decode information cache, the first selecting means for selecting the decode information output by the decoding means and the execution address output by the execution address calculating means, and the instruction to be executed are stored in the decode information cache. And a flag corresponding to the instruction indicates that the execution address is valid, the second selection means selects the decode information stored in the first memory and the execution address stored in the second memory, The instruction to be executed is stored in the decode information cache and the flag corresponding to that instruction has no execution address. The selecting output to perform address of the first stored in the memory decode information and execution address calculating means when represents a 3
And the execution flag output by the execution address calculation means when the execution address output by the execution address calculation means is selected by the third selection means and the execution address output by the execution address calculation means is stored in the second memory. Is set to a value indicating that is valid, instruction executing means for executing an instruction based on the decode information and execution address selected by the first to third selecting means, and this instruction. When the execution means executes an instruction based on the execution address stored in the second memory and the execution address changes, the flag corresponding to the instruction is changed to a value indicating that the execution address is invalid. And means.

That is, in the information processing apparatus of the present invention, in addition to the information indicating where in the decode information cache the stored decode information is the instruction, and the output information of the decoding unit, Of the execution address, information indicating from what the execution address was generated, and information indicating whether the execution address was invalidated by the execution of the instruction.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

The information processing device includes a central processing unit 11. The instruction reading unit 12 of the central processing unit 11 sequentially reads the instructions from the main storage device 14 connected by the data bus 13 and supplies them to the instruction decoding unit 17 through the data bus 16.
The main storage device 14 stores instructions and data executed by the central processing unit 11.

The instruction decoding unit 17 creates decode information by decoding the supplied instruction, and also calculates an execution address indicating the address of the data on the main memory required by the instruction. In this embodiment, the execution address is calculated from the designated relative address and the value of the register (not shown). The instruction decoding unit 17 supplies the decode information through the bus 18 and the execution address through the bus 19 to the instruction executing unit 21 and the decode information cache 22, respectively.
The instruction decoding unit 17 supplies the instruction address of the instruction being executed to the decode information cache 22 via the bus 23.

The decode information cache 22 stores the decode information, the execution address and the instruction address as a group in the first memory 24, the second memory 26 and the third memory 27, respectively. The decode information cache 22 includes a control unit (not shown). The control unit compares the instruction address supplied from the instruction decoder 17 with the contents of the third memory 27, and confirms whether the instruction address has already been registered. When it is confirmed that the instruction has been registered, the decode information cache 22 stores the decode information corresponding to the instruction in the bus.
28, execution address via bus 29, instruction execution unit
Supply to 21. The registration status signal 31 is also supplied to the instruction execution section 21 at the same time. In the third memory 27, the second memory
An execution address valid bit 32 indicating whether the execution address stored in 26 is valid is added to each corresponding instruction address.

The instruction executing unit 21 executes an instruction from the decode information and the execution address supplied from the instruction decoding unit 17 or the decode information cache 22. The instruction execution unit 21
As a result of executing the instruction, a register or main storage device not shown
If rewriting 14 is performed, the decoding information cache 22
The rewrite information 33 is output to.

Next, the operation of the information processing apparatus thus configured will be described.

When the central processing unit 11 executes an instruction, the instruction reading unit 12
Sequentially read the instructions from the main memory 14 via the data bus 15. The instruction read by the instruction reading unit 12 is supplied to the instruction decoding unit 17 via the data bus 16.

The instruction decoding unit 17 supplies the instruction address of the instruction supplied from the instruction reading unit 12 to the decoding information cache 22. The instruction decoding unit 17 decodes the instruction supplied from the instruction reading unit 12, and creates decode information necessary for the instruction executing unit 21 to execute the instruction. Further, the instruction decoding unit 17 simultaneously calculates the execution address indicating the address of the data on the main memory 14 required by the instruction. The decode information and the execution address are supplied to the instruction execution unit 21 and the decode information cache 22 through the buses 18 and 19, respectively.

The control unit (not shown) of the decode information cache 22 compares the instruction address supplied from the instruction decode unit 17 through the bus 23 with the content of the third memory 27 to check whether or not the instruction address has already been registered. In the case of main registration, the instruction decoding unit 17
The instruction address supplied from is stored in the third memory 27. The decode information and the execution address calculated by the instruction decoding unit 17 are stored in the respective areas of the first memory 24 and the second memory 26 through the buses 18 and 19 in association with the instruction address, and It is supplied to the execution unit 21. The instruction executing section 21 executes the instruction using the decode information and the execution address supplied from the instruction decoding section 17.

If the instruction address is already registered and the execution address valid bit 32 is set, the decode information cache 22 supplies the registration status signal 31 to the instruction executing section 21 and the instruction decoding section 17. The decode information cache 22 is
At the same time, the instruction execution unit 21 receives the decode information and execution address registered in the first memory 24 and the second memory 26.
Supply to. Upon receiving the supply of the registration status signal 31, the instruction executing unit 21 executes the instruction from the decode information and the execution address supplied from the decode information cache 22 without waiting for the decoding in the instruction decoding unit 17. Registration status signal
The instruction decoding unit 17, which has been supplied with 31, cancels the generation of the decode information and the calculation of the execution address.

As a result of executing the instruction in the instruction executing unit 21, there are cases where the main memory 14 or the register (not shown) of the central processing unit 11 is rewritten. Since the execution address is changed by rewriting these, the execution address calculated by the instruction decoding unit 17 and already stored in the second memory 26 becomes invalid. Therefore, the instruction execution unit 21 supplies the rewrite information 33 to the decode information cache 22. Decode information cache 22
Refers to the execution address generation information in the first memory 24 with the supplied rewriting information 33, and clears the execution address valid bit 32 of the instruction using the rewritten information.

Although the instruction address from the instruction decoding unit 17 has already been registered, if the execution address valid bit 32 is cleared, the decode information cache 22 sends the registration status signal 31 indicating that the execution address is invalid to the instruction execution unit 21 and It is supplied to the instruction decoding unit 17. When the decode information cache 22 receives the supply of the instruction execution unit 21, only the decode information registered in the first memory 24 is transmitted via the bus 28 to the instruction execution unit 21.
Supply to 21. On the other hand, the instruction decoding unit 17, which receives the supply of the registration status signal 31, calculates only the execution address, and outputs it to the instruction execution unit 21 and the decode information cache via the bus 19.
Supply to 22. The instruction execution unit 21 includes the decode information supplied from the decode information cache 22 and the instruction decode unit 17
The instruction is executed according to the execution address supplied from
The decode information cache 22 stores the invalid execution address stored in the second memory 26 into the instruction decode unit 17
It is rewritten to the execution address newly supplied from.

By performing the above operation for each instruction, the decode information cache 22 is gradually filled with the decoded instructions. A general instruction string often executes the same instruction many times, and the instruction already in the decoding is executed and the instruction in the decode information cache 22 is used more frequently as the instruction is executed. In this case, it is not necessary to read and decode the instruction and calculate the execution address, and the instruction can be executed at high speed.

In the embodiment described above, even if the data in the main memory or the register (not shown) is rewritten by the execution of the instruction and the execution address stored in the second memory becomes invalid, this can be detected. Since it is configured, there is no contradiction in the execution of instructions by rewriting. The execution address valid bit is not necessary in the case of an information processing device for a specific purpose in which the execution address does not change even if the instruction execution unit executes the instruction.

〔The invention's effect〕

As described above, according to the present invention, not only the decode information but also the execution address is stored in the decode information cache in correspondence with the instruction address, so that the instruction can be executed at a higher speed. Further, when the execution address stored in the decode information cache changes as a result of executing the instruction, a flag indicating that the execution address is invalid is set. When this flag indicates that the execution address is invalid, the value stored in the decode information cache is used for the decode information, and the newly calculated value is used for the execution address. As a result, even for an instruction whose execution address changes due to the execution of the instruction, the decoding time can be shortened by using the cache memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing the circuit configuration of an information processing apparatus according to an embodiment of the present invention. 11 ... Central processing unit, 12 ... Instruction reading unit, 17 ... Instruction decoding unit, 21 ... Instruction execution unit, 22 ... Decode information cache, 24 ... First memory, 26 ... Second memory , 27 ... Third memory.

Claims (1)

(57) [Claims] 1. A main storage device for storing an instruction to be executed and data necessary for executing the instruction, an instruction reading means for sequentially reading out the instructions to be executed from the main storage device, and an instruction read by the instruction reading means. Decoding means for decoding, execution address calculating means for obtaining an execution address of data on the main storage device necessary for executing the instruction read by the instruction reading means, and instruction corresponding to the instruction read by the instruction reading means, A first memory for storing the decode information output from the decoding means, a second memory for storing the execution address output from the execution address calculation means, and a flag indicating whether the execution address is valid or invalid. And a decode information cache with an instruction to execute if the decode information cache is not stored in the decode information cache. Storing the decode information output by the means in a first memory, the execution address output by the execution address calculating means in the second memory, and setting the flag to a value indicating that the execution address is valid; 1 writing means, and 1st selection means for selecting the decode information output by the decode means and the execution address output by the execution address calculation means when the instruction to be executed is not stored in the decode information cache, When the instruction to be executed is stored in the decode information cache and the flag corresponding to the instruction indicates that the execution address is valid, the decode information stored in the first memory and the second memory are stored. Second selecting means for selecting the executed execution address, and an instruction to be executed in the decode information cache. A third information storage unit that selects the decode information stored in the first memory and the execution address output by the execution address calculation unit when the flag corresponding to the instruction indicates that the execution address is invalid. When the execution address output by the execution address calculation means is selected by the selection means and the third selection means, the execution address output by the execution address calculation means is stored in the second memory and the corresponding flag is executed. Second writing means for setting a value indicating that the address is valid; instruction executing means for executing an instruction based on the decode information and the execution address selected by the first to third selecting means, As a result of the instruction execution means executing the instruction based on the execution address stored in the second memory, the execution address changes. The information processing apparatus characterized by comprising a flag change means for executing address the flag corresponding to the instruction to change a value representing an invalid time.