JP2659007B2 - Information processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an information processing apparatus.
In particular, non-writable addresses
A first memory having an area for reading and writing the first memory;
A second memory that can be accessed faster than the memory.
The present invention relates to an information processing method and apparatus suitable for the case.

[0002]

2. Description of the Related Art As a means for apparently increasing the speed of data access from a central processing unit (CPU) to a low-speed large-capacity main memory, there is a method using a high-speed small-capacity cache memory. In this method, the memory access of the CPU is first performed on the cache memory in which a part of the data of the main storage device is copied, and the access to the main memory is performed only when the desired data does not exist in the cache memory. . In a normal program, data access has locality. Therefore, if appropriate data in the main memory is copied to the cache memory, only data access from the CPU to the cache memory, which is almost high-speed, is sufficient. Can be.

FIG. 2 shows an example of a configuration of a direct map system (also referred to as a congruent system) which is one system of a cache memory.

The cache memory 17 is information indicating a BS (Buffer Storage) 3 in which a copy of the data of the main memory 4 is stored, and information indicating which address of the data in the BS 3 is the data of the BS 3. AA in which the address tag is stored (address, array , Add
[ress Array] 2. AA2 and BS3 are addresses 9 among addresses 9 output from CPU1.
Addressing is performed by the lower bit section 10. on the other hand,
The remaining upper bit part 11 is A
Store it in A2. When the CPU 1 accesses the memory, the comparator 5 compares the address upper bit portion 11 with the address tag 12 read from the AA 2. If the result of the comparison is a match, the result is called a hit, and if the result is not a match, the result is a mishit. This information is output from the comparator 5 as hit information 13.

When a hit occurs during memory reading (hereinafter referred to as a read hit), the data selector 7 selects BS data 14 based on the hit information 13 and sends the data to the CPU 1 through the data bus 16. When a miss occurs during memory reading (hereinafter referred to as a read mishit), the data selector 7 selects the main memory data 15 based on the hit information 13 and sends the data to the CPU 1 through the data bus 16. Further, when a read miss occurs, the main memory data 15 is copied to the BS 3 through the data buffer 8, and the upper bit portion 11 of the address is written to the AA 2 through the address buffer 6.

On the other hand, at the time of memory write, the following operation is performed to keep the contents of the BS 3 and the contents of the main memory 4 coincident. When a hit occurs during a memory write (hereinafter referred to as a write hit), the contents of both the BS 3 and the main memory 4 are updated. If a miss occurs during a memory write (hereinafter referred to as a write miss), only the main memory 4 is updated.

[0007] As a method of an information processing apparatus using such a cache memory, a journal of Information Processing Society of Japan, Vol.
21, No. 4 (Apr. 1980) PP332-34
0 "Cache Storage".

In the memory space of the CPU 1, in addition to the main memory to be copied to the cache memory, a ROM (R
In general, an ead only memory (Ead Only Memory ) or an I / O (Input / Output) device is mapped. When the CPU 1 accesses a device that is not to be copied,
Access these devices directly, bypassing cache memory. For example, a cache controller 82385 manufactured by Intel Corporation of the United States has an NCA ( Non-Cacheab).
le Access) is provided so that the cache memory can be bypassed. For the cache controller, refer to the 82385 data sheet 290143-0 issued by Intel Corporation of the United States.
01, pp17.

FIG. 3 shows how the cache memory is updated when the copy target area is accessed to the cache memory and when the cache memory is accessed outside the copy target area.

[0010]

The ROM stores a program for starting up the system, a basic input / output program, and the like. In addition, normal programs and data are transferred from a magnetic storage device or the like to a main memory and then transferred to a main memory.
Generally, access is made from U1, but the transfer can be made unnecessary by storing such information in the ROM.

However, in the above-mentioned conventional technology, there is a problem that the address area of the ROM is not to be copied to the cache memory, so that programs and data on the ROM cannot be accessed at high speed using the cache memory. Was.

An object of the present invention is to store information stored in a first memory having a read-only address area in the first memory .
The information can be copied and stored in the second memory while maintaining the security of the information, and the information stored in the first memory can be processed at a higher speed. To provide a simple information processing method and apparatus.

[0013]

An object of the present invention, in order to solve the problem] is, reading
A first memory with dedicated address area out, the
Means for storing a second memory for faster access to the first memory, a copy of the first information at least partially in the storage memory to the second memory, the second Of the information of the first memory stored in the memory of
This is achieved by providing means for prohibiting updating of the information when an update access is attempted to the copy .

A copy of information stored in at least a part of the first memory is stored in the second memory, and a copy of information of the first memory stored in the second memory is stored.
In contrast, this is achieved by prohibiting updating of the information when an update access is attempted.

Further, means for storing a copy of information stored in at least a part of the first memory in the second memory, and means for storing a copy of the information in the first memory stored in the second memory .
This is achieved by providing means for invalidating the information when an update access is attempted for a copy of the information.

A copy of information stored in at least a part of the first memory is stored in the second memory, and a copy of information in the first memory stored in the second memory is stored.
In contrast, this is achieved by invalidating the information when an update access is attempted.

According to a preferred embodiment, the second menu is provided.
Next access to invalid memory information
At the time when the data is stored in at least a part of the first memory.
A copy of the information is stored in the second memory again.

[0018]

According to the above construction, reading of the first memory is performed.
Access- only address area to the first memory.
When a region to be copied to the second memory is used to speed up the access, even if a write access to the information copied to the second memory is performed, the read-only area of the first memory is used.
Can be controlled so that processing mismatch does not occur between the information stored in the address area for use and the information copied to the second memory. Therefore, the information stored in the first memory having the read-only address area is copied and stored in the second memory, which is readable and writable and can be accessed at high speed, while maintaining the security of the information. Can be.
Thereby, in processing the information stored in the first memory, the information can be processed with the high-speed accessible second memory in which the information is copied, so that the information can be processed at a higher speed. Becomes

[0019]

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG.
Has a memory space of 16 MB (M = 2 ²⁰ ) , of which 1 MB from address 000000H (H at the end represents HEX and a hexadecimal number) to the main memory area, and 6 MB from address FF0000H to address FFFFFFH.
4 KB (K = 2 ¹⁰ ) is allocated to each ROM area. FIG. 5 shows a configuration diagram of the present embodiment. The main memory area decoder 18 decodes the value of the address 9 and
In the case of the main memory area of 0000H to 0FFFFFH, the main memory area signal 19 is activated. ROM
The area decoder 20 decodes the value of the address 9 and
In the case of the ROM area of F0000H to FFFFFFH, the ROM area signal 21 is activated. The OR gate 22 is connected to the main memory area signal 19 and the ROM area signal 21.
Is active, the copy target area signal 2
3 is activated. Cache memory control unit 24
AA2 and BS constituting the cache memory 17 as shown in FIG.
3 update control. The feature of this embodiment is that the ROM area is used as an area to be copied to the cache memory 17.

FIG. 6 is a block diagram of a second embodiment of the present invention. The feature of this embodiment is that an AND gate 25 is added to the first embodiment. RO gate
ROM area signal 21 output from M area decoder 20
, An RD signal 27 indicating read access is input. The AND gate 25 activates the ROM area read signal 26 when both inputs are active. The OR gate 22 is connected to the main memory area signal 19
If either the read signal 26 or the ROM area read signal 26 is active, the copy target area signal 23 is made active.
As a result, in the write access to the ROM area, the copy target area signal 23 is not activated.
FIG. 1 shows updating of AA2 and BS3 performed by the cache memory control unit 24 based on the copy target area signal 23. As shown in FIG. 1, even if a hit occurs during a write access to the ROM area, the contents of BS3 are unchanged, and the consistency with the ROM whose contents do not change by the write access is maintained.

FIG. 7 is a block diagram of a third embodiment of the present invention. A bit 31 indicating the validity of each content of AA2 is added to AA2. The area signal 23 to be copied to the cache memory is, as in the first embodiment, an OR gate 22 of the main memory area signal 19 and the ROM area signal 21.
Is obtained by inputting On the other hand, the ROM area signal 21
And a WT signal 29 indicating write access,
An input to the AND gate 28 and a ROM area write signal 30
Get. For a write access in which the ROM area write signal 30 is active, the cache memory control unit 24 sets the V bit 31 added to the content of AA2 referred to in the write access to a value indicating invalidity. As a result, when the address for which the write access has been performed is read next, the V bit 31 is invalid and is treated as a mishit. In the case of a read miss, since the ROM is directly referred to, the updated contents of BS3 are not referred to when a hit occurs in the write access.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention. The feature of this embodiment is that a register 32 for setting an area to be copied to the cache memory is provided in addition to the second embodiment shown in FIG. Register 32
Has an M bit 33 and an R bit 34 and correspond to a main memory area and a ROM area, respectively. The setting for the register 32 is performed by the CPU 1 using the bus for the address 9 and the data 16. M bit 33 value and R bit 34
Are the main memory area enable signal 35 and RO
Each of them is output as an M area enable signal 36.
When the main memory enable signal 35 and the main memory area signal 19 are both active, the AND gate 37 makes the main memory copy signal 38 active. Similarly, when the ROM area enable signal 36 and the ROM area read signal 26 are both active, the AND gate 39 outputs the ROM copy signal 4
0 is active. Then, the main memory copy signal 3
8 or the ROM copy signal 40 is active, the OR gate 22 makes the copy target area signal 23 active. This allows the main memory area or ROM
Reference and update of the cache memory when accessing an area can be independently permitted or prohibited for each area.

FIG. 9 is a flowchart for performing a memory check of the main memory 4 by the information processing apparatus including the fourth embodiment shown in FIG. First, before the memory check of the main memory 4, “0” is set to the M bit 33 and “1” is set to the R bit 34 of the register 32. As a result, only the ROM area becomes an area to be copied to the cache memory. Next, a read / write check is performed on the main memory 4. At this time, since the main memory area is not to be copied, the main memory 4 can be directly read / written.

Also, the read / write check program is stored in the RO
By setting the value in M, the program can be referred to at high speed, and the check of the main memory 4 can be completed in a short time.

The present invention is not limited to the embodiment described above. For example, the addresses of the ROM area and the main memory area need not be the addresses shown in the embodiment. The cache memory system is not limited to the direct map system, but may be a set associative system or the like. The writing method at the time of writing may be a write-through method or a copy-back method.

[0026]

According to the present invention, reading of the first memory is performed.
Accessible of the dedicated address area, to said first memory
In the case where the data is copied to the second memory for speeding up the operation , even if a write access to the information copied to the second memory is performed, the read-only area of the first memory is used.
Can be controlled so that processing mismatch does not occur between the information stored in the address area and the information copied to the second memory. Therefore, the information stored in the first memory provided with the read-only address area can be copied and stored in the second memory for speeding up access while the security of the information is maintained. . Thereby, in processing the information stored in the first memory, the information can be processed with the high-speed accessible second memory in which the information is copied, so that the information can be processed at a higher speed. Becomes

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation in one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a cache memory.

FIG. 3 is an operation diagram of the cache memory.

FIG. 4 is a diagram showing a memory map in one embodiment of the present invention.

FIG. 5 is a configuration diagram in one embodiment.

FIG. 6 is a configuration diagram in another embodiment.

FIG. 7 is a configuration diagram in another embodiment.

FIG. 8 is a configuration diagram in another embodiment.

FIG. 9 is a flowchart of a main memory check method according to the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... AA, 3 ... BS, 4 ... Main memory, 9 ...
Address, 17: cache memory, 18: main memory area decoder, 20: ROM area decoder, 22: OR gate, 24: cache memory control unit, 25: AND gate, 27: RD signal, 29: WT signal.

Claims (5)

(57) [Claims] 1. A first memory device having a read-only address area.
And speed up access to the first memory
And a second memory that, said first means for storing a copy of the information at least partially stored in the second memory of the memory, the first stored in the second memory
Means for prohibiting updating of the information when an update access is attempted to a copy of the information in the memory. 2. A first memory having a read-only address area.
And speed up access to the first memory
And a second memory that, said first means for storing a copy of the information at least partially stored in the second memory of the memory, the first stored in the second memory
Means for invalidating the copy of the information in the memory when an update access is attempted. 3. A next copy of the information stored in at least a part of the first memory when accessing invalidated information in the storage contents of the second memory next time.
3. The information processing apparatus according to claim 2, wherein the information is stored in the memory again. 4. A first memory having a read-only address area.
A copy of the information stored in at least a portion of
A second memo for speeding up access to the first memory
Stored in the first memory and the first memory stored in the second memory.
Update access attempted for a copy of memory information
Information processing, wherein updating of the information is prohibited.
Method. 5. A first memory having a read-only address area.
A copy of the information stored in at least a portion of the
A second memory for accelerating access to the first memory
In the first memory stored in the second memory.
Update access was attempted to a copy of Mori's information
Information processing method, wherein the information is invalidated
Law.