JPH04205535A - Copy on write system - Google Patents

Abstract

PURPOSE:To eliminate the useless transfer of data and to improve the processing efficiency of a main storage by writing the data into a data area to be changed out of a shared area after copying the data for each cache block and rewriting a copying side physical address into a copied side physical address. CONSTITUTION:When an access request is received, it is decided for processing whether the data on a chache block 3 including the address received the access request is changed or not by reference to the block change information 1-3 on the entry of a page table 1 corresponding to the logical address that received the access request. Therefore the data are written into a data area to be changed out of a shared area after copying the data for each block 3. Furthermore the copying side physical address stored in a tag memory 3-1 of a cache is rewritten into a copied side physical address. Thus it is possible to eliminate the useless transfer of data, to reduce the overhead, and to improve the processing efficiency of a main storage.

Description

[Detailed Description of the Invention] [Summary] Regarding the copy-on-write method of copying and writing data in a changed area of a shared area, there is a method of copying and writing data in a changed area of a shared area. Write after copying in units,
The purpose is to eliminate unnecessary data transfers, reduce overhead, and improve main memory processing efficiency.The page table entries for converting logical addresses to physical addresses include the copy source physical page address and the copy destination physical page. Addresses and block change information indicating whether data has been changed in units of cache blocks are provided, and in response to an access request, block change information of the page table entry corresponding to the logical address requested for access is provided. access the physical address consisting of the copy destination physical page address and intra-page displacement extracted from the entry when it is found that the data in the cache block including the address requested for access has been changed; Read from the physical address consisting of the copy source physical page address and intra-page displacement taken from the entry when it is found that it has not been changed and when a read request is made, or a new copy destination when it is found that it has not been changed and when it is a write request. The configuration is such that the physical page address is registered in the entry, copied and written in units of cache blocks, and block change information is set to change.

[Industrial application field]

The present invention relates to a copy-on-write method for copying and writing data in a changed area of a shared area. The method of setting a shared memory space between multiple processes can save main memory when the libraries used by the processes are shared, or when multiple identical processes are running, and also saves the main memory of the program. This is an effective method as it eliminates the need to load In particular, in recent years, advances in semiconductor technology and packaging technology have made processors smaller (and more sophisticated), and systems that combine multiple microprocessors and memory in a hex are attracting attention due to their high cost performance.In such systems, In order to perform effective parallel processing, it is desirable to share memory in small units.

[Conventional technology]

Generally, the address translation mechanism has a configuration as shown in FIG. 2(a), and is performed as follows.

A physical address in page units of the main memory is held in each entry of the lowest table (=page table) for converting a logical address to be converted into a physical address. When converting a logical address to a physical address, the address translation mechanism traces the top level translation table (segment table), which is different for each process, several times until it reaches the page table, and then extracts the physical address of the page. Then, the physical address is obtained by adding the intra-page displacement of the logical address to this, and information such as protection of access to the page is extracted. The address translation mechanism is
Based on the access protection information, if the access protection information is violated, an interrupt is generated to the central processing unit and access is prohibited.

Conventionally, in order to share memory among multiple processes, an address translation mechanism was used to give the same physical address to entries in translation tables and page tables, and access the shared main memory area from multiple logical addresses. That's what I was doing.

For example, if a process is divided into two, it is necessary to make the data area unique to the process except for some shared data areas. The areas were set to coexist, and when a write to the data area occurred, the page for which the write request was made was copied and written to it.

[Problem to be solved by the invention]

Therefore, even if there is no need to change the area near the written area, it is necessary to copy in page units (generally 2 to 4 kilobytes), resulting in unnecessary data transfer and overhead. There was a problem with this. In particular, a system in which parallel processors are connected to a bus has a problem in that the load on the bus becomes heavy, degrading system performance.

The present invention aims to improve the processing efficiency of main memory by writing after copying the data area to be changed in the shared area in cache block units, eliminating unnecessary data transfers and reducing overhead. I'm taking it.

[Means to solve the problem]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, page table 1 has data changed in units of copy source physical page address 1-1, copy destination physical page address 1-2, and cache block 3 for converting logical addresses into physical addresses. This table stores block change information 1#1-3 indicating whether or not the block is changed.

The cache program 3 is the size (block) of data stored in the Canon memory 3-2.

[Effect]

As shown in FIG. 1, in response to an access request, the present invention refers to the block change information 1-3 of the entry in the page table 1 corresponding to the logical address to which the access request was made. When it is determined that the data in cache block 3 containing the address has been changed, accesses the physical address consisting of the copy destination physical page address 1-2 retrieved from the entry and the displacement within the page, while the physical address that has not been changed is accessed. Read from the physical address consisting of the copy source physical page address 1-1 and the displacement within the page retrieved from the entry at the time of a read request, or read from the new copy destination physical address when it is determined that it has not been changed and at the time of a write request. After the page address is registered in the entry and copied in units of cache blocks 3, it is written and the block change information 1-3 is set to change. Further, when it is determined that no change has been made and a write request is made, a new copy destination physical page address is registered in the entry and the copy source physical address in the tag memory 3-1 of the cache is rewritten to the copy destination physical address.

Therefore, writing is performed after copying the data area to be changed in the shared area in units of cache blocks 3, and further writing is performed in the cache tag memory 3-1.
By rewriting the copy source physical address to the copy destination physical address, it is possible to eliminate unnecessary data transfer, reduce overhead, and improve the processing efficiency of the main memory.

[Embodiment] Next, the configuration and operation of an embodiment of the present invention will be explained in detail using FIGS. 1 to 4.

In FIG. 1(a), process A is a process that accesses the data area and shared area of process A on the main memory 2 to perform processing.

Process A'' is a process that was split during the execution of process A, and may refer to the data area of process A. However, when changing the data area of process A, the data in the data area of process A is changed to the data of process A°. This is the process of writing after copying to an area, or accessing a shared area to perform processing.

At this time, the physical page address of the data area of the copy destination process A° is registered in page table 1, and block change information 1-3 is set to change (change for each cache block 3). .

In Figure 1 (B), page table 1 is shown in Figure 1 (B).
b) Information stored in one entry of the page table, which indicates whether data has been changed in units of copy source physical page address 1-1, copy destination physical page address 1-2, and cache block 3. It stores block change information 1-3 and the like. Here, for block change information 1-3, for example, one page is 2 kilohide (21
5 hides), and 1 cache block is 64 hides.
(2h bytes), 32 bits,, t (=22"
-'=2'=32) is required.

The cache block 3 is the size of data to be stored in the cache memory 3-2.

The tag memory 3-1 is the cache memory 3 of the cache.
This is a memory that registers the physical address of the data (data in cache block units) stored in -2. This tag memory 3-1 is searched to determine whether the corresponding data is stored in the cache memory 3-2 (hit/miss).

FIG. 2 shows an explanatory diagram of an address translation mechanism according to the present invention.

FIG. 2(A) shows the overall configuration.

In FIG. 2(a), the translation table entry register is a register for setting the start address of the translation table, and for example, in the translation table corresponding to the space of process A in FIG. 1(a) or the space of process A'. This register sets the start address of the corresponding conversion table.

The logical address register is a register that stores a logical address to be converted into a physical address.

The conversion table is a table for finding the page table 1 storing the corresponding physical page address by tracing as shown in the figure based on the upper bits of the logical address.

As shown in FIG. 2 (b), page table 1 contains access protection information (Read/Write/Excute/
Copy-Write), valid information (information on whether it exists on main memory), physical address information (copy source physical page address 1-1, copy destination physical page address 1)
-2, block change information 1-3) is stored.

The physical address register is a register that stores a physical address after converting a logical address as shown by the arrow in the figure.

FIG. 2(b) shows an example of a page table. Here, as access protection information, Read, Write, Ex
It has ecute and Copy-Write bits, and when it is ■, it is protected, and when it is 0, it is not protected. Specifically, when the Read bit is 1, reading from the main memory of the page address is prohibited. When the -rite bit is 1, writing of page addresses to main memory is prohibited. When the Execute bit is 1, the execution of the program stored in the main memory at the page address is prohibited.0 When the Copy-Write bit according to this embodiment is 1, the result is YES in FIG. 3rd related to
Copy-on-write (writing data after copying from the copy source physical address to the copy destination physical address during write) is performed by the processing in [phase] to [phase] in the figure. When the Copy-Write bit is 0, the If the result is No in Figure 3 ■, Read/1llrite/Excute
Process according to bits.

Next, the operations of the configurations in FIGS. 1 and 2 will be explained in detail in accordance with the order shown in the flowchart in FIG. 3.

In FIG. 3, ■ receives a Read/Write command. In this case, the address translation mechanism shown in FIG. 2 receives a Read/Write command from the host (central processing unit).

(2) retrieves the access protection information of the entry in page table 1 corresponding to the logical address. This is done by tracing the page table corresponding to the logical address notified by the Read/Write command received in ① from the corresponding page table 1 entry by tracing the conversion table in Figure 2 (B) as shown. Figure 2 (b) Access protection information (Re
ad/Write/Execute/Copy-Wri
te bit).

0 means that the copy-three bits extracted in ■ are 1.
(Copy-on-write according to this embodiment is performed) is determined. If YES, perform copy-on-write, etc. according to this embodiment by processing [phase] to ■.
If NO, access protection information (Read/Write/Execution) retrieved from page table 1 in [phase]
(cut bit).

That is, Read bit, Write bit, Execute
If the te bit is 1, the operation is prohibited.

Processing such as copy-on-write according to this embodiment will be described in detail below.

In step (2), it is determined whether or not the block change information has been changed.

This refers to the block change information 1-3 taken out from page table 1 corresponding to the logical address received with the Read/Write command at 0, and executes the Read/Write command.
Determine whether the cache block 3 containing the address to be copied is set to change, that is, whether the contents of the cache block 3 of the copy source physical page have already been copied to the copy destination physical page. do. YES
In this case, the data of the cache block to be Read/Write L/ has already been copied to the copy destination physical page, so use ■ to read to the copy destination physical address.
d/Write, end (END), while
If NO, the data of the cache block to be read/lIr1teL has not been copied to the copy destination physical page, so [phase]
te, and when reading, use O to read from the physical address of the copy source and transfer it to the host, while when writing, copy-on-write (write after copying) with processing from [phase] to ■. do.

[Phase] secures a new copy destination physical address (secures a copy destination physical address for copying the data of the copy source physical address).

@ registers the copy destination physical address (in the [phase], transfer the copy destination physical page address part of the copy destination physical address newly secured to the copy destination physical page address 1-2 in Figure 1 (b)). registration).

[Phase] changes the copy source address of the tag memory 3-1 of the cache to the copy destination address (=copy in units of cache blocks 3). This is cache memory 3-
It is assumed that the content of the tag memory 3-1 having the address of the copy source data stored in 2 is changed to the copy destination physical address and is essentially copied.

(1) -writes to the copy destination physical address (-writes in units of cache block 3). This is done by changing the address of tag memory 3-1 to the copy destination physical address in [phase] to make it essentially equivalent to copying, and at the time of swanni-out, from the cache memory 3-2 to the copy destination page address of main memory 2. Write in units of cache block 3.

As described above, in response to receiving a Read/Write command from the host, Copy-Wr of the entry in page table l corresponding to the specified logical address is executed.
When the ite bit is 1, block change information 1
-3 is the modified cache block 3, Read/Write to the copy destination physical address (Fig. 3 ■),
On the other hand, when the block change information 1-3 is a cache block that has not been changed and it is Read, it is read from the copy destination physical address and transferred to the host (Fig. 3 0), on the other hand, W
By performing copy-on-write using @ or 0 when writing, only the changed part in each cache block 3 is copied to the copy destination physical address and then written, and the remaining part is shared, eliminating unnecessary data transfer and reducing overhead. It becomes possible to reduce the

FIG. 4 shows a specific circuit example of the present invention.

In FIG. 4, the address conversion mechanism 4 is a mechanism that converts a logical address into a physical address, and includes a page table 1 that registers a physical page corresponding to a logical address, and a page table 1 that registers a physical page corresponding to a logical address. The upper address translation unit 5 converts into an entry address, the address translation control circuit 6 performs translation control from a logical address to a physical address, and the copy source physical address (page) l- is selected based on the selection signal from the address translation control circuit 6. 1
Alternatively, a selector 7 that selects one of the copy destination physical addresses (pages) 1-2, a physical address register 8 that holds a physical address consisting of the physical page address selected by this selector 7 and the displacement within the page of the logical address, etc. It consists of:

The tag memory 3-1 is a memory that stores addresses of data in units of cache blocks 3 stored in the cache memory 3-2.

The cache control circuit 3-3 controls the tag memory 3-1 and the cache memory 3-2, and here searches the tag memory 3-1 for the copy source physical address sent from the physical address register 8. , find it, and change it to the physical address of the copy destination (Figure 3 [phase]).

Next, the operation of the configuration shown in FIG. 4 will be explained.

(1) Access protection information (Read/Write/Execute/C
opy-Write), obtain block change information 1-3, copy source physical address, and copy destination physical address. Cop
When the y-Write bit is 1, the process proceeds to the following according to the present embodiment.a (1: opWhen the Y-Write bit is 0, normal processing is performed, that is, the access protection information (Re
ad/Write/Execute) (Fig. 3 ■NO1o).

(2) The address conversion control circuit 6 is the central processing unit 9
Find out in which cache block 3 within the page the data to be read exists from the logical address given from , and check whether the cache block 3 is set to change "I" from the block change information 1-3. Check (
O) in FIG. 3, it is determined whether to use the copy source physical address 1-1 or the copy destination physical address 1-2.

(3) When writing to cache block 3 where block change information 1-3 is 0 (cannon block 3 has not been changed) (in the case of 0YES, ■No, [phase]-rite in Figure 3), , sets the copy destination physical address in the tag memory 3-1, passes the copy source physical address 11 to the cache control circuit 3-3, swaps in from the main memory 2 when there is a miss, and swaps in from the main memory 2 when there is a hit. Transfer the relevant data (Fig. 3 [phase]).

(41 Furthermore, when reading from cache block 3 whose block change information 1-3 is O (Fig. 3 0 YES, [phase]
In the case of NO1 [phase] Read), read from the copy source physical address. Also, block change information [1-3 is 1
When accessing cache block 3 (Figure 3)
If YES or @IYEs), read from the copy destination physical address or perform a needle ite to the copy destination physical address.

〔Effect of the invention〕

As explained above, according to the present invention, the data area to be changed in the shared area is written after copying in units of the cache block 3, and furthermore, the data area to be changed in the shared area is written in the copy source physical area of the tag memory 3-1 of the cache. Since a configuration is adopted in which addresses are rewritten to copy destination physical addresses, it is possible to eliminate unnecessary data transfers, reduce overhead, and improve main memory processing efficiency. As a result, (11) only the necessary portion is copied and the remaining portion is shared, improving the storage efficiency of the main memory.

(2) Since the unit of sharing is small compared to a cache block (for example, 64 bytes) and a page size (for example, 2 kilobytes), unnecessary data transfer processing is unnecessary and the processing speed of the system is improved.

(3) It can be easily realized without preparing a special mechanism for copying data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is an explanatory diagram of an address translation mechanism according to the present invention. FIG. 3 is a flowchart for explaining the operation of the present invention. FIG. 4 shows an example of a specific circuit of the present invention. In the figure, 1: Page table 1-1: Copy source physical page address 1-2 = Copy destination physical page address 1-3 = Block change information 2: Main memory 3: Cache block 3-1: Tag memory 3-2: Cache memory 3-3: Cache control circuit 4 Near address translation mechanism 5: Upper address translation unit 6: Address translation control circuit 9: Central processing unit

Claims (2)

[Claims] (1) In the copy-on-write method that copies and writes data in a shared area that has been changed, the source physical page address is entered in the page table (1) entry for converting a logical address to a physical address. (
1-1), copy destination physical page address (1-2), and block change information (1-3) indicating whether data has been changed in units of cache block (3), and respond to access requests. Then, refer to the block change information (1-3) of the entry in the page table (1) that corresponds to the logical address that received the access request, and change the data in the cache block (3) that includes the address that received the access request. accesses the physical address consisting of the copy destination physical page address (1-1) retrieved from the relevant entry and the displacement within the page when it is determined that the relevant entry has been The copy source physical page address extracted from the entry (
1-1) and the displacement within the page, or when it is determined that it has not been changed and a write request is made, register the new copy destination physical page address in the entry and copy it in units of cache block (3). After writing, block change information (1
-3) A copy-on-write method characterized in that it is configured to set change. (2) If it is determined that the above change has not been made and a write request is made, register the new copy destination physical page address in the relevant entry and change the copy source physical address in the cache tag memory (3-1) to the copy destination physical address. A copy-on-write system according to claim 1, characterized in that the copy-on-write system is configured as follows.