JPH06139147A - Cache memory system - Google Patents

Abstract

PURPOSE:To enhance the availability a cache memory and to improve the throughput of the whole information processing system by speeding up access. CONSTITUTION:In an information processing system provided with the 1st and 2nd cache memories 1, 2 between a main storage device 11 and a processor 8, a cache memory system is provided with a collating means 4 for collating the identification(ID) information of data stored in the 1st and 2nd cache memories 1, 2 based upon ID information for specifying read request signal outputted from the processor 8, a transfer means 5 for transmitting/receiving data between the memories 1, 2 and a control means 6 for controlling respective parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to a technique for providing a buffer memory (cache memory) between a processor and a main memory to speed up data access time.

[0002]

2. Description of the Related Art Recently, there has been a demand for speeding up information processing, and the processing speed of information processing systems has been improved. For example, an arithmetic processing speed is improved by a multiprocessor system in which a plurality of processing devices (processors) are operated in parallel.

However, since the processing speed of the entire information processing system is based on the device having the slowest processing speed in the system, the capacity of the main storage device is expanded in response to the above-mentioned speeding up of the arithmetic processing. However, the speedup has not been made to the extent that the speedup of the arithmetic processing unit is commensurate. Therefore, the delay in the access speed of the main storage device has been a hindrance in improving the processing speed of the system.

Therefore, in order to eliminate this adverse effect, a buffer memory device (hereinafter, referred to as
A cache memory) is provided. This cache memory has a smaller capacity than the main storage device, but has a characteristic that the access speed is high. Then, of the contents stored in the main storage device in the cache memory, the frequently used information is copied and stored. As a result, the instruction processing device determines whether or not an instruction word or an operand required to execute a program is stored in the cache memory, and if the instruction word or operand is stored in the cache memory, the instruction processing device can read from the cache memory. it can. That is, high-speed processing of the program becomes possible, and the processing capacity of the entire information processing system can be improved.

Here, the internal structure of the cache memory is
The storage area is divided into fixed-length block units. And
When copying the contents of the main memory device to the cache memory, the contents of the main memory device are logically divided into blocks having the same length as the cache memory.

As a mapping method for copying the contents of the main storage device to the cache memory, a full associative method and a set associative method are mainly known. A specific example of the full associative method is shown in FIG.

In this full associative system, it is possible to copy an arbitrary block of the main memory device to an arbitrary block of the cache memory. That is, if there is an unused (empty state) block in the cache memory, block replacement for newly rewriting a copied block does not occur. As a result, the cache memory has a feature of improving the usage efficiency.

In this full associative method, when the instruction processing device accesses the cache memory, the cache memory stores information irregularly.
It is necessary to compare the addresses for each block. Therefore, the number of comparators is the same as the number of blocks in the cache memory.

Next, a concrete example of the set associative system is shown in FIG. In the set associative method, a set number is given to each block of the main storage device, and when an arbitrary block is copied to the cache memory, it is stored in the block of the cache memory corresponding to this set number.
This is a fixed mapping method.

In the figure, the blocks of the main storage device are divided into four groups, and set numbers (1) to (3) are assigned to the respective groups. Correspondingly, the cache memory is divided into four blocks, that is, set to set.
For example, in order to copy "data" of "address" in the figure to the cache memory, the set number of the group to which "data" belongs is, so the set number is copied to "block" in the cache memory.

In the case of this set associative system, since the data storage position is fixed by the set number, whether or not the target data is stored in the block corresponding to the predetermined set number by the single address comparator. All you have to do is determine. That is, this set associative method has a characteristic that the hardware configuration is simple.

When the instruction processing device receives a memory access instruction, it reads the block of the set number in the cache memory based on the set number of the block to be accessed, and obtains these address information and the in-group address of the block to be accessed. By comparison, if they match, the cache memory is accessed, and if they do not match, the main storage device is accessed.

An n-way cache memory having n blocks in each set can be considered. In this case, as many address comparators as the number of ways are required. Also, the first
A hierarchical cache memory system in which a second cache memory is provided between the cache memory and the main storage device can be considered.

[0014]

However, in the above-described full associative system, the number of comparators is the same as the number of blocks, which complicates the configuration of the information processing system and, in the case of block replacement, causes a problem. There is a problem that an algorithm for determining whether or not the block of (1) should be rewritten (replaced) is complicated and this algorithm becomes complicated.

On the other hand, in the set associative method, since the area to which the information is to be copied is fixed, it must be rewritten (replaced) even if the other area is empty and the copy destination is in the storage state. Therefore, thrashing that frequently causes rewriting occurs, and the high-speed effect as a cache memory is reduced by half. Further, in order to avoid thrashing, a method of optimizing the arrangement of the code / data of the program can be considered, but this is not practical because the burden on the programmer / compiler is heavy.

Further, when the cache memory is hierarchized, there is a problem that the second cache memory is larger in scale than the first cache memory, has a large redundancy, and has a large overhead at the time of a mishit.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to improve the processing efficiency of the entire system by improving the use efficiency of the cache memory and accelerating the access. And

[0018]

In order to solve the above-mentioned problems, the present invention is as follows. This will be described based on the principle diagram of FIG.

A first memory is provided between the main memory 11 and the processor 8.
The information processing system including the cache memory 1 and the second cache memory 2 is provided with the collation unit 4, the transfer unit 5, and the control unit 6.

The collating means 4 uses the first cache memory 1 and the second cache memory 1 based on the identification information for identifying the individual data.
Search the data stored in the cache memory 2,
It is to check whether or not the data that matches the identification information is stored. The collation unit 4 may include a first collation unit 4a that searches for data in the first cache memory 1 and a second collation unit 4b that searches for data in the second cache memory 2. In this case, the first collating means 4a and the second collating means 4b are operated simultaneously.

The transfer means 5 sends and receives data between the first cache memory 1 and the second cache memory 2. The control means 6 controls the operations of the matching means 4 and the transfer means 5 described above.

Further, discrimination information indicating whether or not data is stored in each area of the first cache memory 1 and whether or not the data in the area is accessed a predetermined number of times or more may be registered. Good. In this case, when newly writing data in the first cache memory 1, a discriminating unit 3 for discriminating an area in which data should be written based on the discrimination information is provided.

Here, the second cache memory 2
May have a smaller storage capacity than the first cache memory 1. The mapping method of the first cache memory 1 and the second cache memory 2 may be a full associative method or a set associative method.

[0024]

According to the present invention, when the processing device 8 issues the data read request, the control means 6 detects the identification information of the read data and notifies the collation means 4 of this identification information.

In the collating means 4, the first collating means 4a and the second collating means 4b operate simultaneously. That is, the first collation unit 4a accesses the first cache memory 1 and collates the identification information with the identification information of the data stored in the first cache memory 1. On the other hand, the second matching means 4
b accesses the second cache memory 2 and collates the identification information with the identification information of the data stored in the second cache memory 2.

When the data matching the identification information of the request data is not stored in both the first cache memory 1 and the second cache memory 2, the control means 6 reads the request data from the main storage device 11. .

At this time, the control means 6 determines whether or not the data exists in the area where the data should be written in the first cache memory 1. When the data already exists in the area, the transfer unit 5 transfers and stores the existing data in the area to the second cache memory 2. As a result, the data read from the main storage device 11 can be stored in the free area after the data transfer.

When the requested data is stored in the second cache memory 2, the transfer means 5 can transfer and store the requested data in the first cache memory 1. Further, when the discrimination information is registered in each area of the first cache memory 1, the control unit 6 causes the discrimination unit 3 to operate when newly writing data in the first cache memory 1. That is, the determination unit 3 accesses the area to which the data is written and refers to the determination information. When the area is empty, the data is written in the area.

If data already exists in the area to be written, it is determined from the discrimination information of the area whether or not the number of accesses reaches a predetermined number. Here, if the access count is less than the predetermined count, the data is written in this area. On the other hand, if the access count is the predetermined count or more, the transfer unit 5 transfers the data in the area to the second cache memory 2. After storing, the data is written in this area.

[0030]

EXAMPLES Specific examples of the present invention will be described below. (Embodiment 1) FIG. 2 is a block diagram showing the overall configuration of the data processing system according to the first embodiment.

The data processing system according to the first embodiment controls the system while processing the data.
Between the PU (CENTRAL PROCESSING UNIT) 8 and the main memory 11 for storing various data, the first
The cache memory 9 and the second cache memory 10 are provided via the memory management system 25.

The second cache memory 10 in the first embodiment has a smaller capacity than the first cache memory 9 described above. Further, the memory management system 25 includes a data transfer circuit 12, an address comparator (1) 13, an address comparator (2) 14 as a collating means according to the present invention, a replace judging circuit 15 as a judging means, and a data output circuit 16. , And a control circuit 17.

The data transfer circuit 12 transfers data between the first cache memory 9 and the second cache memory 10. The address comparator (1) 13 compares the tag of the first cache memory 9 with the address of the data requested by the CPU 8.

The address comparator (2) 14 compares the tag of the second cache memory 10 with the address of the data requested by the CPU 8. The replacement determination circuit 15 compares the attributes of each data stored in the first cache memory 9 and determines the area where the stored contents should be rewritten (hereinafter referred to as “replace”).

The data output circuit 16 outputs the request data of the CPU 8 from the first cache memory 9 or the second cache memory 10 to the CPU 8. The control circuit 17 controls each of the above parts.

Here, FIG. 3 shows the internal structure of the first cache memory 9 in the first embodiment. The first cache memory 9 according to the first embodiment includes storage areas for a TAG field, a valid bit field (VALID), and a data field (DATA).

The TAG field is an area for storing the attribute information of the data stored in each data field (DATA). Valid bit field (VALID)
Is "1" when the data stored in each data field (DATA) is valid, and "when it is invalid"
This is an area for storing "0", and the valid here means a state in which arbitrary data is stored in the data field (DATA). On the other hand, invalid means that the data is stored in the data field (DATA). Indicates a state in which it has not been performed.

The data field (DATA) is an area for storing arbitrary data. Next, referring to FIG.
2 shows an internal configuration of the second cache memory 10 in FIG.

The second cache memory 10 in the first embodiment is a memory element having a smaller storage capacity than the first cache memory 9 described above. And the above-mentioned first
Similar to the cache memory 9, it has a TAG field, a valid bit field (VALID), and a data field (DATA).

The address comparator (1) 13 and the address comparator (2) 14 in the first embodiment are the CPU 8 and
Based on the address information of the data requested by the TA
By referring to the G field and the VALID bit field, it is determined whether the requested data is stored in the cache memory (hit) or not (miss hit). That is, in each of the address comparators (1) 13 and (2) 14, the address information of the data requested by the CPU 8 and the information of the TAG field match,
Moreover, the data in the data field in which the VALID bit is valid is selected. In the first embodiment, the address comparator (1) 13 and the address comparator (2) 14 operate simultaneously.

The operation process of the memory management system in the first embodiment will be described below with reference to the flowchart of FIG. CPU8, when executing an arbitrary program,
An access request for data necessary for executing each module is issued (step 501).

In the memory management system 25, the control circuit 1
7 recognizes the data access request, and detects the data identifier of the accessed data, that is, the address information (step 502). Then, the address information is notified to the address comparator (1) 13 and the address comparator (2) 14 (step 503).

Here, the address comparator (1) 13 accesses the first cache memory 9, and the address comparator (2) 14 accesses the second cache memory 10 (step 504).

Each address comparator compares the address information with the attribute information of each TAG field, and determines whether the first cache memory 9 or the second cache memory 10 stores the data corresponding to the address information. It is determined (step 505).

Here, when the data corresponding to the address information is stored in the first cache memory 9, the address comparator (1) 13 refers to the VALID bit in the area where the address information matches. (Step 50
6), it is determined whether or not the VALID bit is "1" (step 507).

When the VALID bit is "1", the control circuit 17 notifies the data output circuit 16 of the attribute information stored in the TAG field of the area (step 508).

The data output circuit 16 accesses the first cache memory 9 based on the attribute information and outputs the data of the data field corresponding to the attribute information to the CPU 8 (step 509).

In step 505, information matching the address information is stored in the first cache memory 9
If not stored in the second cache memory 10, the control circuit 17 reads the requested data from the main storage device 11 (step 510).

Further, in step 507, V
If the ALID bit indicates invalid, the control circuit 17
Reads the request data from the main storage device 11 (step 511).

Next, the control circuit 17 operates the replacement determination circuit 15 to cause the first cache memory 9 to operate.
The area to store the data read from the main storage device 11 is accessed. Then, the VALID bit of the area is referred to (step 512), and it is determined whether or not it is valid (step 513).

Here, when the VALID bit of the area is valid, the data transfer circuit 12 transfers / stores the data stored in the area to the second cache memory 10 (step 514). Then, the data read from the main storage device 11 is stored in the free area (step 515).

On the other hand, when the VALID bit of the area to be written indicates invalid in the above step 513, the data read from the main storage device 11 is written to the area (step 515).

As described above, according to the first embodiment, the second cache memory 10 having a storage capacity smaller than that of the first cache memory 9 is provided, and the address comparator (2) 14 is provided in the second cache memory 10. As a result, it is possible to improve the efficiency of data access with less hardware.

(Second Embodiment) In the data processing system according to the second embodiment, an area for storing the REFERENCE bit is provided in the first cache memory 9 in addition to the structure of the first embodiment. This configuration is shown in FIG.

The first cache memory 9 in the second embodiment has a structure in which a REFERENCE bit is added in addition to the data field, the TAG field, and the VALID bit field in the structure of the first embodiment.

The REFERENCE bit is cleared to "0" when data is stored in each data field, and is set to "1" when accessed thereafter. As a result, the replacement determination circuit 15 refers to the REFERENCE bit of the replacement target area when replacing the first cache memory 9.
Then, in the case of "0", the replacement is performed regardless of whether the data in the area is stored or not, and in the case of "1", the data in the area is transferred to and stored in the second cache memory 10, Replace.

FIG. 7 is a flow chart showing the operation process of the memory management system 25 in the second embodiment.
When executing an arbitrary program, the CPU 8 issues an access request for data required for executing each module (step 701).

In the memory management system 25, the control circuit 1
7 recognizes the data access request and detects the data identifier of the accessed data, that is, the address information (step 702). Then, the control circuit 17 notifies the address comparator (1) 13 and the address comparator (2) 14 of this address information (step 703).

The address comparator (1) 13 accesses the first cache memory 9, and the address comparator (2) 14 accesses the second cache memory 10,
Each TAG field is searched (step 704).
Then, each address comparator receives the corresponding address information and each TA.
The information in the G field is collated to determine whether or not the information that matches the address information is stored (step 705).

Here, when the information matching the address information is stored in the first cache memory 9, the address comparator (1) 13 causes the VAL of the storage area of the information.
The ID bit is referred to (step 706), and it is determined whether or not the VALID bit is "1" (step 70).
7).

When the VALID bit is "1", the control circuit 17 notifies the data output circuit 16 of the information in the TAG field of the area (step 708). The data output circuit 16 is provided in the first cache memory 9,
The data field corresponding to the TAG field information is accessed, and the data in the data field is stored in the CPU.
8 (step 709).

In step 705, if the information matching the address information is not stored, that is, if the requested data is not stored in either the first cache memory 9 or the second cache memory 10, the control circuit. 17
Accesses the main storage device 11 and reads the requested data (step 710).

Further, in step 707, VAL
When the ID bit is "0", the control circuit 17 accesses the main memory device and reads the requested data (step 711).

After the processing of steps 710 and 711, the control circuit 17 sends the requested data to the data output circuit 1.
6 outputs the data to the CPU 8 and, in the first cache memory 9, refers to the VALID bit of the area in which the requested data is to be stored, and determines whether or not the data in the area is valid. If the data in the area is invalid, the same processing as that in the above-described first embodiment is performed, and thus the description thereof is omitted.

On the other hand, when the VALID bit indicates valid, the replacement judgment circuit 15 determines that the REF of the area concerned.
The ERENCE bit is referred to (step 712), and it is determined whether the data stored in the area has been accessed a predetermined number of times or more (step 713).

When the data in the area is accessed a predetermined number of times or more, the control circuit 17 causes the data transfer circuit 1 to operate.
2 is operated to transfer / store the data in the area to the second cache memory 10 (step 714). After the data transfer, the main storage device 11 is stored in the free area.
The data read from is stored (step 715).

In step 713, when the number of times of accessing the data in the area is less than the predetermined number of times,
The data read from the main memory 11 is stored in the area (step 715). That is, the data in the area is replaced without being transferred to the second cache memory 10.

As described above, according to the second embodiment, when the data hit in the second cache memory 10 is stored in the first cache memory 9, which area of the data field should be replaced is automatically and optimally selected. It becomes possible to do.

(Third Embodiment) The configuration of the memory management system 25 in the third embodiment is the same as that in the second embodiment, and the data transfer circuit 12, the address comparator (1) 13,
Address comparator (2) 14, replacement determination circuit 15,
It is composed of a data output circuit 16 and a control circuit 17.
Here, the control circuit 17 in the third embodiment includes the CPU 8
When the requested data from the data hits in the second cache memory 10, it has a function of storing this data in the first cache memory 9.

Here, FIG. 8 shows an operation flow of the memory management system 25 in the third embodiment. The CPU 8 issues an access request for data necessary for executing each module when executing an arbitrary program (step 80).
1).

In the memory management system 25, the control circuit 1
7 detects the data identifier of the accessed data (step 802). Then, this data identifier is notified to the address comparator (1) 13 and the address comparator (2) 14 (step 803).

The address comparator (1) 13 and the address comparator (2) 14 have a first cache memory 9 and a second cache memory 2, respectively.
The cache memory 10 is accessed at the same time, and the T
The AG field is searched (step 804). TAG
When searching the field, the address comparator (1) 13,
(2) 14 collates the address information with the information in each TAG field. Then, it is determined whether or not there is a TAG field that stores information that matches the address information (step 805).

Here, when the information that matches the address information is stored in the second cache memory 10, the address comparator (2) 14 refers to the VALID bit of the area (step 806) and the VALID bit. But"
It is determined whether or not it is "1" (step 807).

When the VALID bit is "1", the control circuit 17 notifies the data output circuit 16 of the information stored in the TAG field of the area (step 808).

The data output circuit 16 accesses the second cache memory 10, reads data from the data field corresponding to the information, and outputs it to the CPU 8 (step 809).

Further, the replacement determination circuit 16 is
The cache memory 9 is accessed, the VALID bit of the data storage target area is referred to (step 810), and VA
It is determined whether the LID bit is "1" (step 81).
1).

Here, when the VALID bit is "1", the replacement determination circuit 16 causes the REFER of the area concerned.
Referring to the ENCE bit (step 812), REFE
It is determined whether or not the RENCE bit is "1" (step 813).

The REFERENCE bit of the area is "
In the case of 1 ″, the data transfer circuit 12 transfers / stores the data of the area in the second cache memory 10 (step 814), and the requested data read from the second cache memory 10 into the empty area. Is stored (step 815).

On the other hand, when the respective bits are "0" in the above steps 811 and 813, the request data read from the second cache memory 10 is stored in the data storage target area, that is, the data storage. Replace the data in the target area without transferring it.

When the data corresponding to the address information of the requested data is not stored in the first cache memory 9 and the second cache memory 10 in the above step 805, and in the step 807, the VALID bit is "0". In the case of, the control circuit 17
1 to access the requested data (steps 816 and 817).

Then, the replacement judgment circuit 15 has the first
The cache memory 9 is accessed, the VALID bit of the data storage target area is referred to (step 818), and it is determined whether or not this VALID bit is "1" (step 819).

Here, when the VALID bit is "1", the replacement determination circuit 15 further refers to the REFERENCE bit of the area (step 82).
0). Then, the REFERENCE bit is "1".
(Step 821), and if “1”, the data transfer circuit 12 sets the data in the area to the second value.
Transfer / store in cache memory 10 (step 82)
2).

The control circuit 17 stores the data read from the main storage device 11 in the free area after the data transfer (step 823). On the other hand, in step 819 and step 821 described above, each bit is "
In the case of 0 ″, the control circuit 17 stores the data read from the main storage device 11 in the area (step 82).
3). That is, the replacement is performed without transferring the data in the area.

As described above, according to the third embodiment, it is possible to store frequently used data in the first cache memory 9 or the second cache memory 10. (Embodiment 4) In the data processing system according to the fourth embodiment, in place of the first cache memory 9 and the second cache memory 10, a storage address (physical address) of data in the main storage device 11 and a logical address corresponding thereto are provided. Address translation pair buffer (TLB; TR
ANSLATION LOOKASIDE BUFFER (hereinafter abbreviated as first TLB) 18 and second TLB 19 are applied.

Each of the TLBs 18 and 19 is a table in which an address translation pair which is a pair of a logical address of each data and a physical address corresponding to the data is registered in a table format.
Based on the logical address of the data to be processed
The physical address corresponding to the logical address is detected by referring to B. Then, the physical memory obtained by performing the address conversion by this TLB is used to access the main memory device 11 and read the requested data. This specific description will be described later.

The TLBs 18 and 1 in the fourth embodiment are also
9 is provided in the CPU 8 as a high speed storage element. FIG. 9 shows the constituent blocks of the data processing system according to the fourth embodiment.

In the figure, the data processing system is
Comprised of the main memory 11 and the CPU 8, the CP
U8 is a first TLB 18, a second TLB 19, a data transfer circuit 12, an address comparator (1) 22, an address comparator (2) 23, a replacement determination circuit 15, a data output circuit 16, a control circuit 17, an access protection information determination circuit ( 1)
20, an access protection information determination circuit (2) 21, and a read circuit 24.

The data transfer circuit 12 is the first TLB.
The logical address and the physical address information corresponding thereto are exchanged between the 18 and the second TLB 19. The address comparator (1) 22 uses the logical address of the first TLB 18 and the CPU.
It is to compare with the logical address of the data requested by the No. 8.

The address comparator (2) 21 has a second TLB.
The logical address of 19 is compared with the logical address of the data requested by the CPU 8. The replacement determination circuit 15 compares the additional information of each data stored in the first TLB 18 and determines the area to be replaced.

The data output circuit 16 outputs the physical address of the data requested by the CPU 8 from either the first TLB 18 or the second TLB 19. The access protection information determination circuit (1) 20 refers to a protection information storage area, which will be described later, in the accessed storage area of the first TLB 18, and determines whether or not the accessed data is read-permitted or write-permitted. , And whether or not execution is permitted.

The access protection determination circuit (2) 21 is
In the storage area of the accessed data of the TLB 19, by referring to a protection information storage area described later, it is determined whether the accessed data is read-permitted, write-permitted or not, and execution-permitted. Determine.

The reading circuit 24 carries out a reading process of the data requested by the CPU 8. Control circuit 17
Controls the above-mentioned respective parts.

Next, the first TLB 18 in the fourth embodiment will be described.
FIG. 10 shows the internal configuration of the. First T in Example 4
The LB 18 registers address pair information including physical address information of individual data stored in the main storage device 11 and logical address information corresponding to the physical address information.

Furthermore, additional information consisting of protection information, VALID bit, and REFERENCE bit is registered in each address pair information. Here, the protection information includes write control information (W in the figure), read control information (R in the figure), and execution control information (E in the figure) of corresponding logical address information and physical address information. , W = 0 indicates write prohibition, R = 0 indicates read prohibition, and E = 0 indicates execution prohibition. on the other hand,
W = 1 indicates write permission, R = 1 indicates read permission, and E = 1 indicates execution permission.

Other, VALID bit, REFER
The ENCE bit is the same as that in the second embodiment described above, and thus the description thereof is omitted. FIG. 11 shows the second TLB1 in the fourth embodiment.
9 is an internal configuration diagram of FIG.

In the figure, the second TLB 19 comprises a logical address information storage area, a VALID bit storage area, a protection information storage area, and a physical address storage area. Each of the storage areas has the same function as that of the first TLB 18 described above, and thus the description thereof will be omitted.

Here, in the fourth embodiment, when the control circuit 17 issues an access request for arbitrary data from the CPU 8, the control circuit 17 detects the logical address of the accessed data, and the logical address information is detected. To the address comparator (1) 22 and the address comparator (2) 23,
Both address comparators are operated simultaneously.

Then, the area for storing the logical address that matches the logical address information is detected, and the physical address information corresponding to the logical address is output from the area. Next, the operation process of the memory management system according to the fourth embodiment will be described with reference to the flowchart of FIG.

In the fourth embodiment, when the CPU 8 executes an arbitrary program, the CPU 8 issues a physical address read request for data required for executing the program (step 1201).

In this system, the control circuit 17 detects the logical address of the accessed data (step 12).
02), this logical address information is used as an address comparator (1)
22 and the address comparator (2) 23 are notified (step 1203), and both address comparators are simultaneously operated.

The address comparator (1) 22 has the first TLB1
8 and the address comparator (2) 23 receives the second TL.
B19 is accessed to refer to the logical address storage area in each TLB (step 1204).

Each address comparator (1) 22 and address comparator (2) 23 determines whether or not the logical address information that matches the logical address information is stored (step 1205).

Here, if the logical address information that matches the logical address information is not stored, the control circuit 17 prompts the read circuit 24 to access the main memory device 11 (step 1212). On the other hand, when the matching logical address information is stored, the address comparator (1) 22 or the address comparator (2) 23
Refers to the VALID bit of the area (step 1206). Then, it is determined whether or not the VALID bit is "1" (step 1207).

When the VALID bit is "0", the control circuit 17 instructs the read circuit 24 to read the main memory 1
Prompt access to 1 (step 1213). On the other hand, when the VALID bit is “1”, the address comparator (1) 22 or the address comparator (2) 23 determines the address in the TLB of the area where the logical addresses match and the VALID bit is “1”. Information (hereinafter abbreviated as TLB address) is notified to the control circuit 17 (step 12).
08).

The control circuit 17 includes the access protection information determination circuit (1) 20 or the access protection information determination circuit (2) 2.
1 is operated. Access protection information determination circuit (1) 20
Alternatively, the access protection information determination circuit (2) 21 accesses the area based on the TLB address and refers to the protection information (step 1209). Then, it is determined whether or not this area is read-out, that is, R = 1 (step 1210).

Here, when R = 0, the control circuit 17
Indicates that the physical address information cannot be read.
Notify U8 (step 1224). On the other hand, when R = 0, the control circuit 17 recognizes whether or not the storage area of the logical address is the second TLB 19 (step 1211), and in the case of the first TLB 18, the data output circuit 16 determines The physical address information corresponding to the logical address is output to the CPU 8.

Further, in the case of the second TLB 19, the control circuit 17 operates the replacement determination circuit 15 to operate the first determination circuit.
The TLB 18 is accessed (step 1214). The replacement determination circuit 15 determines whether or not there is an empty area in the first TLB 18 (step 1215).

If there is no free area in the first TLB 18, the VALID bit storage area is accessed and V
It is determined whether or not the ALID bit having "0" is absent (step 1216).

If the VALID bit of "0" is absent, the REFERENCE bit storage area is further referred to and the REFERENCE bit is "0".
It is determined whether or not the area of
7).

When the REFERENCE bit "0" is absent, the control circuit 17 determines the area of the first TLB 18 having the oldest information storage time (step 1
218), and access protection information determination circuit (1) 20
Alternatively, the access protection information determination circuit (2) 21 determines whether R = 1 and W = 1 with reference to the protection information (step 1219).

When R = 1 and W = 1, the control circuit 1
7 and the data transfer circuit 12 store the logical address information read from the second TLB 19 in the area of the first TLB 18 (step 1220). Then, the logical address information previously stored in the replaced area of the first TLB 18 is stored in the area of the second TLB 19 previously stored in the area (step 1221).

Here, if there is a free area in the first TLB 18 in the above step 1215, if there is an area in which the VALID bit is "0" in the above step 1216, and in the REFERENCE bit "
If there is a 0 "area, the access protection information determination circuit (1) 20 or the access protection information determination circuit (2)
The reference numeral 21 refers to the protection information of the area and determines whether or not R = 1 (step 1222).

When R = 0, the control circuit 17 notifies the CPU 8 that replacement is impossible (step 1224). On the other hand, when R = 1, the data transfer circuit 12 transfers / stores the logical address information read from the second TLB 19 in the area of the first TLB 18 (step 1223).

As described above, according to the fourth embodiment, when any data is required, the main memory device is accessed and the address information section in the main memory device 11 is collated with the address information of the accessed data. You can save time. That is, since a huge amount of data is stored in the main storage device 11, it takes a huge amount of time and labor to detect the accessed data, but according to the TLB, the CPU 8 causes the TL
Based on the physical address information detected from B, the accessed data can be accessed in a short time, and the logical address can be smoothly converted into the physical address.

[0115]

According to the present invention, frequent replacement by a single cache memory can be prevented, and the cache memory usage efficiency can be improved. Furthermore, the processing capability of the entire information processing system can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an overall configuration diagram of a data processing system according to the first embodiment.

FIG. 3 is an internal configuration diagram of a first cache memory according to the first embodiment.

FIG. 4 is an internal configuration diagram of a second cache memory according to the first embodiment.

FIG. 5 is a flowchart showing an operation process of the memory management system according to the first embodiment.

FIG. 6 is an internal configuration diagram of a first cache memory according to the second embodiment.

FIG. 7 is a flowchart showing an operation process of the memory management system according to the second embodiment.

FIG. 8 is a flowchart showing an operation process of the memory management system according to the third embodiment.

FIG. 9 is a configuration block diagram of a data processing system according to the fourth embodiment.

FIG. 10 is an internal configuration diagram of a first TLB in the fourth embodiment.

FIG. 11 is an internal configuration diagram of a second TLB in the fourth embodiment.

FIG. 12 is a flowchart showing an operation process of the cache memory system according to the fourth embodiment.

FIG. 13 is an internal configuration diagram of a cache memory in a conventional full associative system.

FIG. 14 is an internal configuration diagram of a cache memory in a conventional set associative system.

[Explanation of symbols]

 1-first cache memory 2--second cache memory 3--discrimination means 4--collation means 5--transfer means 6-control means 8--CPU 8a-read-out means 9-first cache memory 10-Second cache memory 11-Main storage device 12-Data transfer circuit 13-Address comparator (1) 14-Address comparator (2) 15-Replacement determination circuit 16-Data output circuit 17 Control circuit 18 First TLB 19 Second TLB 20 Access protection information determination circuit (1) 21 Access protection information determination circuit (2) 22 Address comparator (1) 23 Address comparison Device (2) 24 .. Readout circuit 25 .. Memory management system

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Miyamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (5)

[Claims] 1. An information processing system comprising a first cache memory (1) and a second cache memory (2) between a main storage device (11) and a processing device (8), the processing device (8). The first cache memory (1) based on identification information that specifies read request data from the
And a collating unit (4) for collating identification information of data stored in the second cache memory (2), and exchanging data between the first cache memory (1) and the second cache memory (2). Transfer means (5)
And a control unit (6) for controlling the respective units, the control unit (6), when receiving a data read request from the processing device (8), causes the collation unit (4) to
The identification information of the data stored in each cache memory is collated with the identification information of the request data, and the data that matches the identification information of the request data is the first data.
When not stored in the cache memory (1) and the second cache memory (2), the requested data is read from the main storage device (11) and an area in the first cache memory (1) where the data should be written. Determines whether data already exists in the area, and when the data exists in the area, the transfer means (5) transfers / stores the existing data in the area to the second cache memory (2), Main memory device (11)
A cache memory system characterized in that data read from the cache memory is stored in the area. 2. The control means (6) causes the transfer means (5) to cause the data to be read from the processing device (8) when the data requested to be read is stored in the second cache memory (2). The data is transferred and stored in the first cache memory (1).
The described cache memory system. 3. Registering discrimination information indicating whether or not data is stored in each area of the first cache memory (1) and whether or not the data in the area is accessed a predetermined number of times or more. When writing new data to the first cache memory (1), there is provided a discriminating means (3) for discriminating an area in which the data should be written based on the discrimination information, the first cache memory (1) When newly writing data, the discriminating means (3) discriminates whether or not data already exists in these regions by referring to the discriminating information of the regions in which the data can be written. If the data already exists, the control unit (6) determines whether or not the number of times of access of the area is satisfied based on the determination information. When the number of times is not satisfied, the data is written in the area, and when the number of access times of the writable area satisfies a predetermined number, the transfer unit (5) writes the existing data in the area to the first number. 2. The cache memory system according to claim 1, wherein the data is written to the area after being transferred and stored in the two-cache memory (2). 4. The first collating means (4a) for collating the identification information of the data stored in the first cache memory (1) based on the identification information of the request data. And a second collating means (4b) for collating the identification information of the data stored in the second cache memory (2), the control means (6) reading data from the processing device (8). When the request is received, the first collating means (4a) and the second collating means (4b) are simultaneously operated based on the identification information of the request data.
The described cache memory system. 5. The cache memory system according to claim 1, wherein the second cache memory (2) has a storage capacity smaller than that of the first cache memory (1).